JPH0574790A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To provide a method of manufacturing a semiconductor device which is protected against punch-through, where vertical transistors and lateral transistors are concurrently formed through a manufacturing method excellent in conformity, the lateral transistors are lessened in base region resistance, and a semiconductor device application for a high frequency operation. CONSTITUTION:In a lateral transistor, a buried layer 2 and an epitaxial layer 3 are formed on a substrate 1, an emitter region 4, a collector region 5, an intrinsic base region, an outer base compensation diffusion region 9 higher than the epitaxial layer 3 in impurity concentration, and a collector contact region 13 are formed on the epitaxial layer 3, and a field insulating film 23, an emitter lead-out electrode, a collector lead-out electrode, a base lead-out electrode, and an insulating film 25 are formed on the epitaxial layer 3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device having a lateral transistor in which the direction of arrangement of an emitter region, a collector region and a base region is horizontal with respect to a surface of a substrate and its manufacture. Regarding the method.

In recent years, an NPN transistor and a P-type transistor are formed on a common substrate as a means for increasing the multifunctionality and reducing the power consumption of LSIs.
A transistor in combination with an NP transistor has been studied, but in general, one having a vertical type and the other having a horizontal type has been manufactured in order to reduce the number of steps.

However, there has been a problem that the lateral transistor has a large base resistance and cannot cope with high frequency operation. Therefore, improvement in the performance of the lateral transistor is required.

[0004]

2. Description of the Related Art FIG. 4 shows an example of a conventional lateral transistor. FIG. 4 shows a case of a PNP transistor, and 1 is a conductivity type p.
Semiconductor substrate, 2 is an n ⁺ buried diffusion layer, 3 is an n ⁻ epitaxial layer, 4 is a p ⁺ emitter region, 5 is a p ⁺ collector region, 6 is a base region, and 7 is an n ⁻ intrinsic base region. , 8 is an n ⁺ external base region, 10 is an n ⁺ base contact region, 11 is a p ⁺ polysilicon emitter extraction electrode, 12 is a p ⁺ polysilicon collector extraction electrode, and 13 is an n ⁺ polysilicon Base extraction electrode, 23
Is a field insulating film, 24 is an element isolation insulating region, and 25 is an insulating film.

Generally, a lateral transistor is as shown in FIG.
The emitter region 4, the collector region 5, and the base region 6 are characterized by being formed adjacent to each other in the horizontal direction with respect to the surface of the substrate 1.

Further, as can be seen from FIG. 4, since the epitaxial layer 3 is formed on the buried diffusion layer 2 in parallel with the substrate 1, the emitter region 4 and the collector region 5 are formed on the epitaxial layer 3 so that The layer 3 was the intrinsic base region 7 and the extrinsic base region 8 immediately below the intrinsic base region 7.

[0007]

As shown in FIG. 4, when a lateral transistor is formed in the same process as the vertical transistor, the lateral transistor is formed in accordance with the process of the vertical transistor. The impurity distribution in the intrinsic base region 7 of the transistor was not in an optimized state. That is, since the impurity concentration of the intrinsic base region 7 is usually set to be the same as the concentration of the collector region 15 of the vertical transistor, the impurity concentration of the intrinsic base region 7 and the external base region 8 immediately below it are low.
As a result, the resistivity of the base region 6 of the lateral transistor becomes high, and as a result, only a lateral transistor unsuitable for high frequency operation can be produced, and a complementary connected output transistor with excellent performance cannot be realized. there were.

Therefore, according to the present invention, in a semiconductor device in which a vertical transistor and a horizontal transistor are formed on the same substrate, the resistivity of the base region 6 of the horizontal transistor is reduced while the matching with the vertical transistor is excellent. An object of the present invention is to provide a lateral transistor suitable for high frequency operation.

[0009]

As shown in FIG. 1, according to the present invention, a buried diffusion layer 2 having a high impurity concentration and an epitaxial layer 3 having a low impurity concentration are deposited on a substrate 1 and an emitter region 4 is formed on the epitaxial layer 3. The external base compensation diffusion formed in the epitaxial layer 3 immediately below the intrinsic base region 7 under the basic structure of the lateral transistor in which the collector region 5 and the base region 6 are adjacent to each other in the horizontal direction with respect to the surface of the substrate 1. By providing the layer 9 and the intrinsic base region 8 having an impurity concentration higher than that of the epitaxial layer 3, the impurity concentration of the external base region 8 having a low impurity concentration immediately below the intrinsic base region 7 is increased.

[0010]

As shown in FIG. 1, according to the present invention, since the external base compensation diffusion region 9 is formed to increase the impurity concentration of the external base region 8 immediately below the intrinsic base region 7, the n ⁻ intrinsic base region 7 to the n ⁺ The resistance reaching the external base region 8 can be reduced.

Further, as shown in FIG. 3, when a vertical transistor and a horizontal transistor are formed on the same substrate,
If the external base compensation diffusion region 9 is formed by an appropriate process, the impurity distribution of the intrinsic base region 7 can be optimized. Further, if the external base compensation diffusion region 9 is formed immediately below the intrinsic base region 7 of the lateral transistor at the same time as the collector region 14 having a high impurity concentration is formed immediately below the intrinsic base region 7 of the vertical transistor. The lateral transistor can be formed without increasing the manufacturing process of the lateral transistor.

[0012]

FIG. 1 shows an embodiment of the lateral transistor of the present invention. FIG. 1 shows a case of a lateral PNP transistor, and FIG.
The same reference numerals denote the same objects, and description thereof will be omitted.
The point of the present invention that is most different from FIG. 4 is a portion indicated by 9, which is an external base compensation diffusion region formed by increasing the concentration of a region having a low impurity concentration directly below the intrinsic base region 7, For example, 400 [keV] / 1 x 10
^It is formed by ion implantation of ¹³ [cm ⁻² ].

FIG. 3 shows an embodiment of a semiconductor device in which the vertical transistor and the lateral transistor of the present invention are combined. FIG. 3 shows a case where a vertical NPN transistor and a horizontal PNP transistor are formed on the same substrate. The same reference numerals as those in FIG. 1 indicate the same objects, and regarding the vertical transistor,
14 is an n ⁺ emitter region, 15 is an n ⁺ collector region, 16
Is an n ⁺ collector contact region, 17 is a base region, 18
Is the intrinsic base region of p, 19 is the extrinsic base region of p ⁺ , 20
Is an n ⁺ polysilicon emitter extraction electrode, 21 is n
Reference numeral 22 denotes a collector lead-out electrode made of ⁺ polysilicon, and reference numeral 22 denotes a base lead-out electrode made of p ⁺ polysilicon.

The steps of the embodiment shown in FIG. 3 will be described below. [1] The impurity concentration on the substrate 1 is 10 ¹⁹ by a known method.
An n-type buried diffusion layer 2 of about 10 ²⁰ [/ CC] is formed. [2] A thickness of about 0.5 to 1.0 [μm] and an impurity concentration of 1 on the buried diffusion layers 2 of both vertical and horizontal transistors by the CVD method.
N type epitaxial layer 3 of about 0 ¹⁶ to 10 ¹⁷ [/ CC]
Grow. [3] The field insulating film 23 is formed in a predetermined region on the epitaxial layer 3 by the selective thermal oxidation method. [4] The element isolation insulating region 24 is formed between the elements by a known method. [5] By ion implantation, the n ⁺ collector contact region 16 of the vertical transistor and the n ⁺ collector of the lateral transistor are formed ^.
A base contact region 10 is formed. [6] A p ⁺ -doped polysilicon film and an insulating film 25 are formed on the entire surface by a CVD method, and the polysilicon film and the insulating film 25 are continuously etched by a general lithographic process to form a vertical transistor. The base extraction electrode 22, the emitter extraction electrode 11 and the collector extraction electrode 12 of the lateral transistor are formed. Further CVD
After forming the insulating film 25 on the entire surface by the method, the insulating film 25 on the intrinsic base region 18 of the vertical transistor and the intrinsic base region 7 of the lateral transistor is removed by the RIE method to form the emitter window and the base window. At this time, the side wall of the insulating film 25 is formed on the base extraction electrode 22 of the vertical transistor and the emitter extraction electrode 11 and the collector extraction electrode 12 of the horizontal transistor. [7] A screen oxide film for ion implantation is formed in the emitter and base windows by thermal oxidation, P is 400 [keV] · 1 × 10 ¹³ [cm ⁻² ] by ion implantation using the insulating film 25 as a mask. , Vertical transistor collector region 15
And a lateral transistor external base compensation diffusion region 9 are formed. [8] The intrinsic base region 18 of the vertical transistor is formed by ion implantation through the emitter window using the insulating film 25 as a mask.
To form. [9] The screen oxide film is removed by anisotropic etching. However, the screen oxide film on the base region of the lateral transistor is not removed. [10] An n ⁺ -doped polysilicon layer is deposited by the CVD method, and patterned to form the emitter extraction electrode 20 and the collector extraction electrode 21 of the vertical transistor.
And the base lead electrode 13 of the lateral transistor are formed. [11] By the heat treatment, the n-type impurities of the vertical transistor emitter extraction electrode 20 are diffused into the vertical transistor intrinsic base region 17 to become the vertical transistor emitter region 14, and the vertical transistor base extraction electrode 22.
Of the vertical transistor external base region 19 connected to the vertical transistor intrinsic base region 18 by diffusion of the p-type impurities of
Then, the p-type impurity of the emitter extraction electrode 11 of the lateral transistor diffuses to become the emitter region 4 of the lateral transistor, and the collector extraction electrode of the lateral transistor.
The 12 p-type impurities become the collector region 5 of the diffused lateral transistor.

Through the above steps, both the lateral PNP transistor and the vertical NPN transistor of the present invention can be formed. In this method, there is no step for the horizontal transistor only, compared to the case where the vertical transistor is formed independently,
The number of steps does not increase.

Further, in this embodiment, since the emitter region 4 and the collector region 5 of the lateral transistor and the external base compensation diffusion region 9 are defined by the same mask pattern, there is no displacement and the lateral transistor emitter extraction. Ion implantation is performed by using the insulating film 25 covering the electrode 10 and the collector extraction electrode 12 as a mask to form the external base compensation diffusion region 9. Therefore, alignment of the mask is unnecessary and the manufacturing process is simplified.

Here, the formation of both the NPN transistor and the PNP transistor has been described in order to show the compatibility with the vertical transistor. However, in the case of forming the lateral transistor alone, the vertical transistor among the above manufacturing methods is used. The lateral transistor of the present invention can be formed by the steps excluding these steps.

Further, as shown in FIG. 2, by making the impurity concentration of the intrinsic base region higher than that of the epitaxial layer, it is possible to prevent the depletion layer from being crowded and to prevent punch-through.

Specific examples will be shown below. FIG. 5 shows the intrinsic base region 7 when the punch-through is prevented by forming the external base compensation diffusion region 9 and the intrinsic base region 7 as described above.
In the concentration distribution in the vicinity, the boundary surface (corresponding to the straight line D in FIG. 2) between the emitter region 4 and the emitter extraction electrode 11 and between the collector region 5 and the collector extraction electrode 12 is on the straight line C (Y coordinate 1.0 [μm]). .. Ion implantation conditions for making the polysilicon p-type are B 35 [keV] · 3.3 × 10 ¹⁵
[Cm ⁻² ], and the ion implantation condition when forming the external base compensation diffusion region 9 and the intrinsic base region 7 is P = 150
[KeV] ・ 4 × 10 ¹² [cm ^-2 ] and 400 [keV] ・
1 × 10 ¹³ [cm ⁻² ], the annealing condition is 1100
[° C] · 10 [s]. 6 and 7 show the depth [μ
m] and impurity concentration [/ CC] are shown in FIG. 6 on the straight line A passing through the emitter region 4 in FIG. 5 (X coordinate 0.0 [μ
m]), and in FIG. 7, the intrinsic base region 7 in FIG.
7 is a graph on a straight line B passing through (X coordinate 0.6 [μm]). The depth is on the straight line C in Fig. 5 (Y coordinate 1.0 [μ
m]) is set to 0 and the distance from it is shown.

FIG. 8 shows a graph of collector current, current amplification factor and cutoff frequency. As can be seen from FIG. 8, about 10
The current amplification factor of 1 is obtained, and the amplification factor of the conventional lateral transistor is about 2 to 3, so it can be seen that there is a remarkable effect. Further, the cutoff frequency has a value exceeding 1 [GHz], and it can be seen that the purpose of coping with high frequency operation has been achieved.

However, FIG. 8 shows emitter width, collector width,
The base width is 0.4 [μm], the length of each window is 10 [μm],
6 is a graph when the collector-base voltage is 0 [V].

It is not always necessary to make the collector region 15 of the vertical transistor higher than the impurity concentration of the epitaxial layer 3, but this suppresses the Kirk effect and improves the cutoff frequency. A better effect can be obtained as compared to the case where the region 15 is not made higher in impurity concentration than the epitaxial layer 3. Also,
Here, the vertical transistor is the NPN and the horizontal transistor is the PNP. However, when the vertical transistor is the PNP and the horizontal transistor is the NPN, the same process can be performed, and the emitter and the collector may be reversed. .. However, in a vertical transistor, the injection efficiency is improved when the area of the surface where the emitter and the base are in contact is smaller than the area of the surface where the collector and the base are in contact. Therefore, the emitter should have the same positional relationship as in the embodiment of the present invention. It is better to form the region 4 and the collector region 5.

[0023]

As described above, according to the present invention,
In a semiconductor device in which a vertical transistor and a lateral transistor are formed on the same substrate, a high-concentration external base compensation diffusion region 9 is formed immediately below an intrinsic base region of the lateral transistor.
By optimizing the impurity distribution of the intrinsic base region 7 by appropriately forming, it is possible to reduce the resistivity of the base region 6 of the lateral transistor, and thus it is possible to manufacture a semiconductor device adapted to high frequency operation. Become.

Also, when punch-through occurs, punch-through can be prevented by increasing the impurity concentration of the intrinsic base region 7 more than that of the epitaxial layer 3.
Therefore, it greatly contributes to the realization of a multi-functional, low-power-consumption LSI that has high performance, supports high-frequency operation.

[Brief description of drawings]

FIG. 1 is a diagram showing an embodiment of a lateral transistor of the present invention.

FIG. 2 is a diagram showing an embodiment of a lateral transistor for preventing punch through according to the present invention.

FIG. 3 is an embodiment diagram of a lateral transistor when combined with the vertical transistor of the present invention.

FIG. 4 is a conventional example of a lateral transistor.

FIG. 5 is a distribution diagram of the impurity concentration around the intrinsic base region in the lateral transistor for preventing punch through according to the present invention.

FIG. 6 is a diagram showing changes in the concentration of impurities under the intrinsic base region of a lateral transistor when preventing punch-through according to the present invention.

FIG. 7 is a diagram showing changes in the concentration of impurities under the collector region of the lateral transistor in the case of preventing punch through according to the present invention.

FIG. 8 is a relational diagram of collector current, cut-off frequency and current amplification factor in a lateral transistor in the case of preventing punch-through according to the present invention.

[Explanation of symbols]

 1 substrate 2 buried diffusion layer 3 epitaxial layer 4 emitter region 5 collector region 6 base region 7 intrinsic base region 8 external base region 9 external base compensation diffusion region 10 base contact region 11 emitter extraction electrode 12 collector extraction electrode 13 base extraction electrode 14 emitter Region 15 Collector region 16 Collector contact region 17 Base region 18 Intrinsic base region 19 External base region 20 Emitter extraction electrode 21 Collector extraction electrode 22 Base extraction electrode 23 Field insulating film 24 Element isolation insulating region 25 Insulating film

Claims (3)

[Claims] 1. A high-concentration one-conductivity type buried diffusion layer (2) and a low-concentration one-conductivity type epitaxial layer (3) which are sequentially formed on a substrate (1) and are separated from each other by the epitaxial layer (3). And an emitter region (4) and a collector region (5) of opposite conductivity type, and an intrinsic base region (between the emitter region (4) and the collector region (5) of the epitaxial layer (3)). A semiconductor device comprising a lateral transistor having an external base compensation diffusion region (9) formed with an impurity concentration higher than that of the epitaxial layer (3) immediately below the region to be 7). 2. The extrinsic base compensation diffusion region (9) is formed so as to extend from the surface of the intrinsic base region (7) to the buried diffusion layer (2) which becomes the extrinsic base region (8). The semiconductor device according to claim 1. 3. A high concentration one conductivity type buried diffusion layer (2) and a low concentration one conductivity type epitaxial layer (3) on a substrate (1) in sequence.
And a step of forming a lateral transistor formation region of the epitaxial layer (3) into a first region sandwiched between a region where a emitter region (4) is formed and a region where a collector region (5) is formed. In the vertical transistor formation planned region, impurities of one conductivity type are simultaneously introduced into the substrate (1) in the second region immediately below the formation planned region of the emitter region (14), and the impurity concentration of the first region is increased. Is formed higher than other epitaxial layers (3) to form an external base compensation diffusion region (9), and in the second region, the buried diffusion layer (2) is formed from the bottom of the region where the base region (17) is to be formed. ), A high concentration collector region (15) is formed, and in the epitaxial layer (3) in the lateral transistor formation planned region, an emitter region (4) and a collector which are arranged apart from each other are formed. Forming a region (5) and forming a base region (17) in the epitaxial layer (3) in the vertical transistor formation planned region; and forming the base region (17) in the vertical transistor formation planned region in the epitaxial layer (3). And a step of forming a one-conductivity type emitter region (14) in a portion corresponding to the high-concentration collector region (15).