JPS61214569A - Semiconductor device - Google Patents

Abstract

PURPOSE:To make high the speed of a lateral transistor by a construction wherein an emitter region and a collector region which have a lead-out electrode structure are formed in an element region formed on the main surface of a semiconductor substrate. CONSTITUTION:An N<+> type buried layer 2, an N<-> type epitaxial layer 4 and an oxide film 5 for isolating an element are formed on a P-type Si substrate 1. Thereafter an emitter region 7 and a collector region 8 both of P<+> type and of high concentration are formed on the surface of the layer 4. then, lead- out electrodes 9a and 9b of poly Si are formed in an area expanding from openings 6a and 6b of an Si nitride film 6 and an oxide film 5a on the surface of the substrate to the outside of an element region. Thereafter an Si oxide film 11 and an Si nitride film 12 are formed on the electrodes 9a and 9b, and an opening 13 for forming a base is formed in relation to the film 11 and the film 12. Next, N-type impurities are introduced through the opening 13, so as to form an N-type semiconductor region 14 which is to operate as a genuine base region. By this construction, an area occupied by the region 7 and the region 8 is reduced, which makes it possible to reduce junction capacitance and to make high the speed of a lateral transistor.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to semiconductor technology, and relates to a technology effective for use in forming lateral bipolar transistors in semiconductor integrated circuits, for example.

[Background Art] Currently, bipolar integrated circuits are mainly composed of vertical NPN transistors. However, if an attempt is made to configure all the circuits using only NPN transistors, the circuit will become very complicated, but if there are PNP transistors on the same semiconductor substrate, the circuit can be easily assembled in some cases.

However, in conventional bipolar integrated circuits,
This is because the process becomes complicated if you try to make a vertical NPN bipolar transistor and a vertical PNP bipolar transistor on the same substrate.

As shown in Figure 3, the PNP transistor is formed as a lateral transistor that operates in the lateral direction.
(Published June 2016, 419 pages).

That is, in a conventional lateral transistor, a part of a low concentration N-type epitaxial layer 4 formed on a semiconductor substrate 1 by a vapor phase growth method is separated by an isolation region (in WI, a p+ type dispersion layer 21). This N is the base area.
A P-type impurity such as boron is diffused into the surface of the −-type base region at the same time as the base region (P+ diffusion layer) of the NPN transistor (not shown) is formed, and the P-type collector region 8 is
and an emitter region 7.

In the lateral transistor with the above structure,
Compared to the substantial base current flowing from the emitter region 7 along near the surface of the epitaxial layer 4, the wasted base current flowing directly from the emitter region 7 through the N++-containing layer 2 below toward the P medium base extraction region 17. It turns out that there are quite a lot. Furthermore, since the emitter region 7 and the collector region 8 face the N++-containing layer 2, there is a drawback that a relatively large parasitic capacitance is attached and the AC characteristics are poor.

[Objective of the Invention] The object of the present invention is to form a vertical bipolar transistor without substantially changing the process of forming the vertical bipolar transistor.
An object of the present invention is to provide a semiconductor technology that allows a high-performance lateral transistor to be formed on the same substrate as a vertical bipolar transistor.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Summary of the Invention] Representative inventions disclosed in this application will be summarized as follows.

That is, by forming an emitter region and a collector region having an extraction electrode structure made of a polysilicon layer in the element region formed on the main surface of the semiconductor substrate, the area occupied by the emitter region and the collector region is reduced, and the junction capacitance is increased. In addition, by forming an intrinsic base region in the vicinity of the emitter region in a self-aligned manner using an emitter electrode, it is possible to suppress the spread of the depletion layer from the collector region and increase the speed of the lateral transistor. By making it possible to optimize the impurity concentration distribution in the direction, the base width can be reduced and the lateral fT (L and cutting frequency) can be improved without lowering the withstand voltage.

The present invention will be specifically explained below using the drawings.

[Embodiment] FIGS. 1A to 1F show a first embodiment in which the present invention is applied to the formation of a lateral transistor in a bipolar integrated circuit in the order of manufacturing steps.

In this embodiment, a silicon oxide film is first formed on a semiconductor substrate 1 made of P-type wheel crystal silicon by the same method as the known isoplanar technology, although it is not particularly limited. A hole for a buried diffusion pattern is formed at the position, and an N type impurity such as arsenic or antimony is introduced using this silicon oxide film as a mask, thereby forming an N'''' type buried layer 2 partially.

After removing the silicon oxide film that served as a mask for forming the buried layer, an N-type epitaxial layer 4 is grown on it by vapor phase growth, and a silicon oxide film and a silicon nitride film are formed on the surface of the N-type epitaxial layer 4. do. Thereafter, the silicon oxide film and the silicon nitride film are partially removed by photoetching, and using this as a mask, the main surface of the substrate is slightly scraped, and then thermal oxidation is performed to form a relatively thick oxide film 5 for element isolation. After forming the isolation oxide film, the silicon nitride film that served as a mask was removed to leave the state as shown in FIG. 1(A).

Although not shown, in the part where the PNP vertical transistor is formed, the same element formation region as above (
In addition to 4), a collector pull-up port is formed by selectively introducing an N-type impurity such as phosphorus into a portion of the collector region that will become a pull-up port using a silicon nitride film or the like as a mask.

After the state shown in Figure 1 (A), first the CVD method (chemical
After a silicon nitride film 6 is formed on the entire surface by a vapor deposition method, the silicon nitride film 6 and the oxide film 5a in the portions where the emitter region and collector region are to be formed are removed by photoetching, and the openings 6a are formed. 6b
Using this silicon nitride film 6 as a mask, BF2 ions are implanted into the main surface of the substrate to form a high concentration P medium emitter region 7 and collector region 8.

Then, a non-doped polysilicon layer (polycrystalline silicon) is formed on the entire surface by CVD or the like, and then boron is selectively implanted into a portion corresponding to the outer end of the extraction electrode.

Then, heat treatment is performed to cause the impurity (boron) in emitter region 7 and collector region 8 to rise up into the non-doped polysilicon layer thereon. Then, regardless of the spacing between the openings 6a, 13b, boron can always be diffused up to a certain distance from the inner edges of the openings 6a, 6b.

In this state, when the polysilicon layer is etched using an etching solution such as hydrazine (NH2-NH2), hydrazine is more than 10 times more effective than boron-containing polysilicon. Since etching can be performed at high speed, the openings 6a, 6
The polysilicon in the inner part from a position a certain distance away from the inside of b is removed, and the polysilicon outside the outer end of the above-mentioned lead-out electrode doped with boron in advance is also removed, and the lead-out made of polysilicon is removed. electrode 9a,
9b is formed, resulting in the state shown in FIG. 1(B).

Next, a silicon oxide film 11 is formed entirely on the lead electrodes 9a and 9b by CVD.

Furthermore, a silicon nitride film 1 is formed on it by the same <CVD method.
2 is formed on the entire surface. Then, by photo-etching, the emitter lead electrode 9 is formed as shown in FIG. 1(C).
With respect to the silicon oxide film 11 and silicon nitride film 12 near both ends of a.

An opening 13 for forming a base is formed. Then, a part of the emitter extraction electrode 9a is exposed through this opening 13.

Thereafter, using the silicon nitride film 12 and polysilicon electrode 9a as an ion implantation mask, an N-type impurity, such as phosphorus or arsenic, is introduced into the main surface of the substrate to form an N-type semiconductor region 14 that will become an intrinsic base region. Then, using the silicon nitride film 12 as an oxidation-resistant mask, an oxide film 15 is formed on the surface of the exposed portion of the emitter extraction electrode 9a, resulting in the state shown in FIG. 1(D).

After that, as shown in FIG. 1(E), after removing the silicon nitride film 12, the silicon nitride film 6 inside the opening 13, and the silicon oxide fli5a thereunder, a polysilicon layer is deposited on the entire surface. An N type impurity such as arsenic is implanted into this polysilicon layer and diffused to form an N+ type semiconductor region 17 on the intrinsic base region 14 to reduce contact resistance. Then, by photo-etching,
An unnecessary portion of the polysilicon is removed to form a base silicon electrode 18, resulting in the state shown in FIG. 1(F). As a result, the emitter-side intrinsic base region 14 and the base contact region 1 are self-aligned to the emitter region 7.
7 is now formed.

The entire transistor can be configured compactly.

After the state shown in FIG. 1(F), the polysilicon electrode 9a
, 9b, 18 with PSG film (phosphorus silicate glass film)
After forming an interlayer insulating film on the entire surface, the base,
Form contact holes for the emitter and collector regions. Then, aluminum is deposited on the interlayer insulating film and then photoetched to form an aluminum electrode, and a final passivation film is formed on the aluminum electrode to complete the process.

According to the transistor structure as in the above embodiment.

The current flowing from the emitter region 7 toward the N+ type buried layer 2 below it decreases, and the base current that also flows from the emitter region 7 becomes almost an effective base current. Therefore, wasteful base current is reduced and the direct current amplification factor (hyE) is improved.

Further, the electrodes for the emitter region 7 and the collector region 8 are taken out by an extraction electrode 9a made of polysilicon.
, 9b.

Therefore, the area occupied by the emitter region 7, the collector region 8, and the element forming region containing them becomes smaller, thereby reducing the area between the base and emitter.

The base-collector and base-substrate junction capacitances are significantly reduced, increasing the operating speed of the transistor and improving AC characteristics.

Furthermore, the expansion of the depletion layer extending from the collector region 8 is stopped by the highly doped intrinsic base region 14. Therefore, punch-through is less likely to occur, so even if the emitter-collector distance is reduced, the withstand voltage between the base and collector is less likely to drop. As a result, the base width can be reduced without reducing the withstand voltage, and the lateral impurity concentration distribution is also very easy to optimize, greatly improving the fT (L, new local wave number) of the transistor. be able to.

Furthermore, in recent years, various technologies for forming high-performance vertical transistors called 5STs (super self-alignment transistors) have been proposed for bipolar integrated circuits, and the process for the lateral transistors in the above embodiment is based on such technologies. It has excellent compatibility with the SST structure transistor process.

Therefore, if the above embodiment is applied to a bipolar integrated circuit consisting of NPN vertical transistors with an SST structure, it is possible to use a common process to simultaneously create a high-performance NPN vertical transistor and a PNP lateral transistor with excellent performance as described above. A transistor can be formed.

[Example 2] FIG. 2 shows an example of a relatively high-performance lateral transistor that can be formed by a simpler process than the first example.

That is, in this embodiment, contact holes 6a and 6b are formed in an oxide film 5a and a silicon nitride film 6 on the surface of an element region made of an N-type epitaxial layer 4, and a polysilicon layer doped with P-type impurities is formed on the contact holes 6a and 6b. An emitter lead electrode 9a and a collector lead electrode 9b are formed. Then, a P-type emitter region 7 and a collector region 8 are formed by impurity diffusion from these extraction electrodes 9a and 9b.

In this embodiment, an N medium-sized semiconductor serving as a base pull-up port is placed so as to reach the N+ type buried layer 2 previously formed below the emitter and collector regions 7 and 8, with one isolation oxide film 5 in between. A region 21 is formed, and a base electrode is formed on the surface of this base pull-up port (21). The base pull-up port (21) can be formed at the same time as the N+ type semiconductor region which becomes the collector pull-up port of a vertical transistor (not shown).

In this embodiment as well, the emitter and collector electrodes are taken out using an extraction electrode structure, so the emitter region 7 and the collector region 8 are formed more easily than in the conventional type lateral transistor shown in FIG. The area occupied by the element region (in the figure, the epitaxial layer 4 surrounded by the isolation oxide film 5) can be reduced.

Therefore, the base-emitter, base-collector, and base-substrate junction capacitances are significantly reduced, increasing the operating speed of the transistor and improving AC characteristics.

[Effect (1) Since the lateral transistor was constructed by forming an emitter region and a collector region having an extraction electrode structure made of a polysilicon layer in the element region formed on the main surface of the semiconductor substrate, the emitter region and the collector region were formed. The effect of reducing the area occupied by the collector region and reducing the junction capacitance has the effect of increasing the speed of the lateral transistor and improving AC characteristics.

(2) An emitter region and a collector region having an extraction electrode structure made of a polysilicon layer are formed in the element region formed on the main surface of the semiconductor substrate, and an emitter electrode is used in the vicinity of the emitter region for self-alignment. By forming the intrinsic base region and the base contact region, the expansion of the depletion layer from the collector region can be suppressed, and the lateral impurity concentration distribution can be optimized, thereby reducing the breakdown voltage. There is an effect that the lateral fT (L and new station wave number) can be improved by reducing the base width.

Although the invention made by the present inventor has been specifically explained above based on examples, it goes without saying that the present invention is not limited to the above-mentioned examples, and can be modified in various ways without departing from the gist thereof. Nor. For example, in the above embodiment, as an example of a process for a lateral transistor, a process that is compatible with a process for a vertical NPN transistor has been described, but the present invention is not limited thereto, and various modifications of the process can be easily considered.

Further, in the embodiment, a PNP type lateral transistor has been described, but the present invention can also be applied to an NPN type lateral transistor.

[Field of Application] In the above explanation, the invention made by the present inventor was mainly applied to the field of application which is the background thereof, which is the formation of lateral transistors in bipolar integrated circuits, but the present invention is not limited thereto. It can be used for semiconductor devices in general.

FIG. 2 is a sectional view showing a second embodiment of the lateral transistor according to the present invention in the order of manufacturing steps.

FIG. 3 is a cross-sectional view showing an example of the configuration of a lateral transistor in a conventional bipolar integrated circuit.

1... Semiconductor substrate, 2... N medium-sized buried layer, 5...
...Element isolation region (element isolation oxide film), 5a
...Oxide film, 6,12...Silicon nitride film, 7
...Emitter region, 8...Collector region, 9a
...Emitter lead-out electrode, 9b...Collector lead-out electrode, 11...Silicon oxide film, 13...
Base forming opening, 14... Intrinsic base region.

15... Oxide film, 18... Polysilicon electrode for base.

Figure 1 Figure 1 Part 1 h (F)

Claims (1)

[Claims] 1. A low-concentration device region surrounded by a device isolation region is formed on the main surface of a semiconductor substrate, and a high-concentration semiconductor region that becomes an emitter region and a collector region is formed within this device region. A pair of extraction electrodes are formed at appropriate intervals and extend from a part of the element region to the outside thereof with an insulating film interposed therebetween, and one end of this extraction electrode is in contact with the emitter region and the collector region. 1. A semiconductor device comprising a bipolar transistor that operates in the lateral direction. 2. A base region comprising a semiconductor region of a conductivity type different from that of the emitter and collector regions is formed on the surface of the low concentration element region between the emitter region and the collector region. The semiconductor device according to item 1. 3. A patent characterized in that the emitter extraction electrode and the collector extraction electrode are made of a polysilicon layer, and the base electrode and the emitter extraction electrode are separated by an oxide film formed by oxidizing the surface of the emitter extraction electrode. A semiconductor device according to claim 2.