JPH04328833A - Manufacture of semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To lower the base resistance by lessening the gap between an emitter region and outer base regions of a bipolar transistor. CONSTITUTION:After the formation of an emitter electrode 9a using a cap insulating film 11a formed above an emitter region 10 as a mask, outer base regions 6a are formed in a self-alignment manner with this emitter electrode 9a thereby lessening the gap between the outer base regions 6a and the emitter region 10.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technology for manufacturing semiconductor integrated circuit devices, and more particularly to a technology that is effective when applied to semiconductor integrated circuit devices having bipolar transistors.

0002

[Prior Art] One of the methods for manufacturing bipolar transistors is to form a photoresist pattern on an emitter region formed in a part of the base region, and perform ion implantation using this pattern as a mask to form an external base region. There is.

To manufacture an npn bipolar transistor using this method, first, an n-type buried layer is formed in a semiconductor substrate, an epitaxial layer is formed on the buried layer, and then a field layer is formed on the surface of the epitaxial layer. After selectively forming an insulating film, n-type impurities are selectively ion-implanted into a part of the epitaxial layer using a photoresist as a mask, and the impurities are thermally diffused to form n-type impurities.
form a shaped collector extraction area.

Next, a p-type impurity is selectively ion-implanted into a part of the epitaxial layer using the photoresist as a mask, and the impurity is thermally diffused to form a p-type base region. An n-type impurity is selectively ion-implanted into a part of the base region using a mask, and the impurity is thermally diffused to form an n-type emitter region.

Thereafter, a photoresist pattern is formed on the emitter region, and using this as a mask, p-type impurities are selectively ion-implanted into a part of the base region, and then the impurities are thermally diffused to form p-type impurities. form the external base area of the shape.

[0006]

[Problems to be Solved by the Invention] However, in the above-mentioned conventional technique in which an external base region is formed using a photoresist formed on an emitter region as a mask, the emitter region This has the drawback that the distance between the external base region and the external base region increases, and the base resistance increases.

As a measure to improve the above drawbacks, an emitter electrode made of n-type polycrystalline silicon is formed on the p-type base region, and the n-type impurity in this emitter electrode is diffused into a part of the p-type base region. After forming the emitter region, p-type impurity ions are selectively implanted into a part of the base region using this emitter electrode as a mask, and by thermally diffusing this impurity, the impurity is self-aligned to the emitter electrode. Methods of forming external base regions have also been proposed.

However, in this method, p-type impurities are implanted into the emitter electrode made of n-type polycrystalline silicon when forming the external base region, which deteriorates the shape of the emitter electrode and increases the emitter resistance. However, there are disadvantages such as a decrease in emitter injection efficiency.

The present invention has been made in view of the above-mentioned problems, and its purpose is to reduce the base resistance by shortening the distance between the emitter region and the external base region of a bipolar transistor. Our goal is to provide the technology that makes it possible.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[0011]

[Means for Solving the Problems] Among the inventions disclosed in this application, a brief overview of typical inventions will be as follows.
It is as follows.

The method for manufacturing a bipolar transistor according to the present invention includes a step of etching a part of an insulating film on a base region formed on a semiconductor substrate to form an opening, and a step of etching a part of an insulating film on a base region formed on a semiconductor substrate to form an opening. forming an emitter region by thermally diffusing the impurity in the polycrystalline silicon film into a part of the base region through the opening; and depositing an insulating film on the polycrystalline silicon film. forming a cap insulating film above the emitter region by forming a photoresist pattern on the insulating film and etching the insulating film using the photoresist pattern as a mask; forming an emitter electrode on the emitter region by etching the polycrystalline silicon film using as a mask; ion-implanting impurities into a part of the base region using the emitter electrode and the cap insulating film as a mask; After that, there is a step of thermally diffusing the impurity to form an external base region in a self-aligned manner with respect to the emitter electrode.

[0013]

[Operation] According to the above-described means, after forming the emitter electrode using the cap insulating film formed above the emitter region as a mask, the external base region is formed in self-alignment with respect to the emitter electrode. The distance between the base region and the emitter region can be shortened.

The present invention will be explained below with reference to Examples. In addition, in all the figures for explaining the embodiment, parts having the same functions are denoted by the same reference numerals, and repeated explanation thereof will be omitted.

[0015]

Embodiment A method of manufacturing an npn bipolar transistor according to this embodiment will be explained with reference to FIGS. 1 to 7.

First, as shown in FIG. 1, an n-type impurity (for example, phosphorus) is ion-implanted into a semiconductor substrate 1 made of p-type silicon single crystal, and this impurity is thermally diffused to form an n+-type buried layer 2. After this formation, a silicon epitaxial layer 3 is formed on this buried layer 2. Next, a field insulating film 4 made of silicon oxide is formed on the surface of the epitaxial layer 3 by a selective oxidation method (LOCOS method), and then an n-type film is formed on a part of the epitaxial layer 3 using a photoresist (not shown) as a mask. An impurity (for example, phosphorus) is ion-implanted selectively, and the impurity is thermally diffused to form an n-type collector extraction region 5.

Next, as shown in FIG. 2, a p-type impurity (for example, boron) is selectively ion-implanted into a part of the epitaxial layer 3 using a photoresist (not shown) as a mask, and this impurity is heated. After a p-type base region 6 is formed by diffusion, a portion of the insulating film 7 on the base region 6 is etched to form an opening 8.

Next, as shown in FIG. 3, a polycrystalline silicon film 9 for an emitter electrode is formed on the entire surface of the substrate 1 using the CVD method.
After ion-implanting an n-type impurity (for example, phosphorus) into this polycrystalline silicon film 9, the n-type impurity in the polycrystalline silicon film 9 is transferred to a part of the base region 6 through the opening 8 by thermal diffusion. An n-type emitter region 10 is diffused into the n-type emitter region 10.
form.

Next, as shown in FIG. 4, an insulating film 11 made of silicon oxide is deposited over the entire surface of the substrate 1 using the CVD method.

Next, as shown in FIG. 5, the insulating film 11 is
A photoresist pattern 12 is formed thereon, and the insulating film 11 is etched using this pattern as a mask, thereby forming a cap insulating film 11a for forming an emitter electrode above the emitter region 10.

Next, as shown in FIG. 6, after removing the photoresist pattern 12 on the cap insulating film 11a, the polycrystalline silicon film 9 is etched using the cap insulating film 11a as a mask. An emitter electrode 9a is formed on the emitter region 10.

Next, as shown in FIG. 7, a photoresist pattern 13 is formed in a region other than the base region 6 and emitter region 10, and this photoresist pattern 13,
The emitter electrode 9a and the cap insulating film 1 thereon
After ion-implanting a p-type impurity (for example, boron) into the substrate 1 using 1a as a mask, the impurity is thermally diffused to form an external base region 6a in a self-aligned manner with respect to the emitter electrode 9a.

As described above, in this embodiment, after forming the emitter electrode 9a using the cap insulating film 11a formed above the emitter region 10 as a mask, the external base region is formed in a self-aligned manner with respect to the emitter electrode 9a. Form 6a. As a result, the external base region 6a and the emitter region 1
Since the distance from zero can be shortened, the base resistance can be reduced and a high-speed bipolar transistor can be provided.

Furthermore, in this embodiment, when ion-implanting p-type impurities for forming an external base region into the substrate 1, since the cap insulating film 11a is formed on the emitter electrode 9a, the cap insulating film 11a is formed on the emitter electrode 9a. No p-type impurity is implanted into the emitter electrode 9a.

[0025] Above, the invention made by the present inventor has been specifically explained based on examples, but the present invention is not limited to the above-mentioned examples, and can be modified in various ways without departing from the gist thereof. Needless to say.

In the above embodiments, the emitter electrode is made of a polycrystalline silicon film, but for example, a polycide film made of a polycrystalline silicon film and a high melting point metal film such as tungsten (W), or a polycrystalline silicon film and a tungsten film may be used. It can also be constructed from a polycide film consisting of a high melting point metal silicide film such as silicide (WSi2).

In the above embodiment, the case where the present invention is applied to a method of manufacturing an npn type bipolar transistor has been described, but it can also be applied to a method of manufacturing a pnp type bipolar transistor.

[0028]

[Effects of the Invention] Among the inventions disclosed in this application, the effects obtained by the typical inventions will be briefly explained as follows.
It is as follows.

After forming the emitter electrode using the cap insulating film formed above the emitter region as a mask, the external base region is formed in a self-aligned manner with respect to the emitter electrode, so that the connection between the external base region and the emitter region is The distance can be shortened, thereby reducing the base resistance.

[Brief explanation of drawings]

FIG. 1 is a sectional view of a main part of a semiconductor substrate showing a method of manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention.

FIG. 2 is a sectional view of a main part of a semiconductor substrate showing a method of manufacturing this semiconductor integrated circuit device.

FIG. 3 is a sectional view of a main part of a semiconductor substrate showing a method of manufacturing this semiconductor integrated circuit device.

FIG. 4 is a sectional view of a main part of a semiconductor substrate showing a method of manufacturing this semiconductor integrated circuit device.

FIG. 5 is a sectional view of a main part of a semiconductor substrate showing a method of manufacturing this semiconductor integrated circuit device.

FIG. 6 is a sectional view of a main part of a semiconductor substrate showing a method of manufacturing this semiconductor integrated circuit device.

FIG. 7 is a sectional view of a main part of a semiconductor substrate showing a method of manufacturing this semiconductor integrated circuit device.

[Explanation of symbols]

1 Semiconductor substrate 2 Embedded layer 3 Epitaxial layer 4 Field insulation film 5 Collector extraction area 6 Base area 6a External base area 7 Insulating film 8 Opening hole 9 Polycrystalline silicon film 9a Emitter electrode 10 Emitter area 11 Insulating film 11a Cap insulation film 12 Photoresist pattern 13 Photoresist pattern

Claims (3)

[Claims] 1. A method for manufacturing a semiconductor integrated circuit device having a bipolar transistor, comprising: etching a part of an insulating film on a base region formed on a semiconductor substrate to form an opening; forming an emitter region by ion-implanting impurities into a polycrystalline silicon film deposited on the polycrystalline silicon film, and then thermally diffusing the impurities in the polycrystalline silicon film into a part of the base region through the opening; After depositing an insulating film on the film, forming a photoresist pattern on the insulating film, and etching the insulating film using the photoresist pattern as a mask to form a cap insulating film above the emitter region. forming an emitter electrode on the emitter region by etching the polycrystalline silicon film using the cap insulating film as a mask; etching the base region using the emitter electrode and the cap insulating film as a mask; A method for manufacturing a semiconductor integrated circuit device, comprising the step of ion-implanting an impurity into a portion and then thermally diffusing the impurity to form an external base region in a self-aligned manner with respect to the emitter electrode. 2. After ion-implanting impurities into the polycrystalline silicon film deposited on the semiconductor substrate, a high melting point metal film or a high melting point metal silicide film is deposited on the polycrystalline silicon film to form a polycide structure. 2. The method of manufacturing a semiconductor integrated circuit device according to claim 1, further comprising forming an emitter electrode. 3. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the method is a method of manufacturing an npn bipolar transistor.