JPH0256935A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To maintain the characteristic of elements of a high breakdown strength power and improve the characteristics of a low breakdown strength controlling circuit part in a chip by forming P-type low-concentration isolation layers just on P-type high-concentration isolation layers formed in the N-type substrate of the low breakdown strength controlling circuit part so as to surround said high-concentration isolation layers. CONSTITUTION:Isolation areas 2 for isolation from a P-type high-concentration substrate are formed at the specified positions of an N-type low-resistivity substrate 1 by diffusing boron. P-type low-concentration isolation areas 3 are formed on and around the surfaces of the areas 2 by oxidation and removal of oxide films in a wet atmosphere by using the segregation of boron to the oxide films. N-type high- concentration buried layers 4 are formed by diffusing antimony, an epitaxial layer 5 is formed thereon, isolation areas 6 are formed by diffusing boron to isolate elements in one end the same chip, and collector walls 7 are formed by diffusing phosphorus to reduce the series resistance of the elements. This maintains the characteristic of high breakdown strength power elements and provides the characteristics of the saturation voltage and the parasitic current of a low breakdown strength part equal to that of the controlling circuit part of a normal semiconductor integrated circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit incorporating one power element.

[Conventional technology]

Fig. 3 (A semiconductor integrated circuit in which a conventional power element is included in one element using Al-In will be explained.) First, as shown in Fig. 3 (al), an N-type image resistivity substrate (11 predetermined positions A high-concentration isolation region (2) with the substrate is formed by diffusing boron, and a high-concentration N-type buried layer (4) is formed by diffusing antimony as shown in FIG.

Then, as shown in FIG. 3, an epitaxial layer (5) is formed thereon. Next, Figure 3 (
As shown in dl, boron is diffused to form isolation regions (6) in order to separate the elements within the same space, and phosphorus is diffused to form isolation regions (7) in order to reduce the series resistance of the elements. form.

Then, as shown in FIG. 3, each time boron is implanted, the heath region of the transistor (
8), Emitter region of lateral PNP transistor (8,
1), by forming the collector region (8,2) and diffusing phosphorus to form the emitter region (9,
) Horizontal PNP transistor base contact (9,
1) Form.

Then, as shown in FIG. 3(f), a hole is made in the oxide film θφ for taking out the electrode, and then aluminum wiring 0υ is formed to complete the process.

[Problem to be solved by the invention]

In such a conventional semiconductor integrated circuit incorporating one power element, a highly doped P-type layer is formed on the N-type substrate in the control circuit section to prevent punch-through at low voltage between the N-type epitaxial layer and the N-type substrate. Because it forms a high concentration of N
During the epitaxial layer growth after forming the buried layer, autodoping of the high concentration P layer is significantly caused by the high concentration N.
This has the disadvantage that it overtakes the N-type buried layer and surrounds the highly doped N-type buried layer, significantly worsening the saturation voltage of the transistor in the control circuit section. Another disadvantage is that the collector current flows through the highly concentrated P-shaped osteotomy, resulting in an extremely large amount of parasitic current, which deteriorates the characteristics of the control circuit section of a semiconductor integrated circuit incorporating one power element. Ta.

The purpose of the present invention was to solve the above-mentioned problems, and aims not only to maintain the characteristics of a high-voltage power element but also to improve the characteristics of a low-voltage control circuit section within a chip.

[Means to solve the problem]

The semiconductor integrated circuit device according to the present invention has a P-type high voltage formed on an N-type substrate in the low voltage control circuit section. Agricultural degree! Jff
A P-type low-concentration dispersion layer is formed directly above and surrounding the P-type dispersion layer.

[Effect]

In the control circuit section of a semiconductor integrated circuit that incorporates one power device, a P-type high-concentration isolation layer is absolutely necessary to prevent punch-through at low voltage between the N-type eviaxial layer and the N-type substrate. During epitaxial layer growth after forming a high concentration N type buried layer, the high concentration P type layer overtakes the high concentration N type buried layer due to autodoping and surrounds the high concentration N type buried layer.

In order to prevent autodoping, it is sufficient to simply lower the overall concentration of the P-type bone l11 layer, but this method cannot prevent punch-through with the N-type epitaxial layer at low voltage. Therefore, the P-shaped osteotomy layer near the surface is a low-concentration layer that suppresses the concentration and does not cause avalanche breakdown at low voltages, and the inner layer is a layer with a high concentration that prevents punch-through at low voltages. It is a layer with concentration and diffusion depth. These double P-type osteotomies surround the high-concentration N-type buried layer, worsening the saturation voltage of the transistor in the control circuit, and lowering the voltage between the epitaxial layer and the N-type substrate. There is no punch-through and characteristics equivalent to those of the control circuit section of a normal semiconductor integrated circuit can be obtained.

[Embodiments of the invention]

An embodiment of the present invention will be described with reference to the drawings. 1st
The figure shows a cross-sectional structure of a semiconductor integrated circuit device according to an embodiment of the present invention, and FIG. 2 (al-fg) shows a cross-sectional structure according to its manufacturing flow.

First, as shown in Figure 2 fa) (, N-type image resistivity substrate f
By diffusing boron into a predetermined position of the il, a low concentration P-type isolation region (3) from the plate is formed near the surface by oxidation in an etch atmosphere and removal of the oxide film. Furthermore, as shown in FIG. 2(a), a highly concentrated N-type buried layer (3) is formed by diffusing antimony.

Then, as shown in FIG. 2+dl, an epic primary layer (4) is formed thereon. Then,
As shown in Figure 2 (at), in order to separate the elements within the same chip, boron is diffused to form a ζ isolation region (5), and the elements are connected in series 11 (to reduce resistance, phosphorus is diffused to form a collector wall). (6) is formed.

Then, as shown in FIG. 2 R1, by implanting boron, the base region (8) of the N I) N
), horizontal PNr') emitter region of the transistor (8,
1) Form the collector region (8, 2) and expand the phosphorus 11
By doing this, form the emitter 61 region (9) of the N I-transistor and the base contact (9,1) of the lateral PNP I-transistor.

Then, as shown in Fig. 2fg+, after making a hole for taking out the electrode in the oxide film
and complete it. In the above example, we have described an example in which a bipolar transistor is used in the high voltage part.
Naturally, other high voltage elements, such as 0MO5FE, are used in the high voltage part.
Even if an element such as a CMO5FET is included in the low breakdown voltage section, the same effect can be obtained.

〔Effect of the invention〕

As explained above, according to the present invention, in a circuit incorporating one power element, not only the characteristics of the high voltage power element are maintained, but also the saturation voltage and parasitic current of the low voltage part are reduced compared to ordinary semiconductor integrated circuits. Since it can have the same characteristics as the control circuit section, it is possible to obtain a chip that does not deteriorate the electrical characteristics of the Sennobu as a whole.

[Brief explanation of the drawing]

FIG. 1 shows a cross-sectional view of a semiconductor integrated circuit according to an embodiment of the present invention, and FIG. 2 +a+-(91 is a cross-sectional structure according to its manufacturing flow. This is a cross-sectional structure according to the manufacturing flow of a semiconductor integrated circuit using conventional technology. In the figure, (1) is an N-type image resistivity semiconductor substrate, (2) is a P-type high concentration isolation region, and (3) is a P-type resistivity semiconductor substrate. Image density separation area, (4)
is an N-type heavily doped buried layer region, (5) is an epitaxial layer region, (6) is an upper isolation region, (7) is a collector all region, (8) is a base region of an NPN transistor,
(8,1) is the emitter region of the lateral PNP transistor, (8,2) is the collector region of the lateral PNP transistor, (9) is the emitter region of the NPN transistor, (9,1) is the base contact region of the lateral PNP transistor , (+01 indicates an oxide film, and Qll indicates an aluminum wiring. In addition, the same numbers and symbols indicate the same parts in the figures. Agent Masuo Oiwa Figure 1 Figure 2 Figure 2 (e) Figure 3 Figure (, l) Figure 3? Procedural amendment (voluntary)

Claims (1)

[Claims] a semiconductor substrate having a first conductivity type; a first semiconductor region having a second conductivity type with a high impurity concentration formed in a predetermined portion of the semiconductor substrate; a second semiconductor region having a second conductivity type with a low impurity concentration; a third semiconductor region having a first conductivity type with a high impurity concentration formed in a predetermined portion of the second semiconductor region; the semiconductor substrate; a fourth semiconductor region having a first conductivity type formed so as to embed the first semiconductor region, the second semiconductor region, and the third semiconductor region; 1. A semiconductor integrated circuit device comprising: a semiconductor region, a third semiconductor region, and a fourth semiconductor region.