JP2008218982A - Semiconductor device and manufacturing method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem wherein it is difficult, in conventional semiconductor devices, to reduce the size of an isolation region (ISO) that form region, due to increased lateral diffusion width of a P-type embedded layer constituting the ISO. <P>SOLUTION: In a semiconductor device, two epitaxial layers EPI7 and EPI8 are formed on a P-type substrate 6. In the substrate 6 and the epitaxial layers EPI7 and EPI8, isolation regions ISO1, ISO2, and ISO3 are formed to divide the substrate and the epitaxial layers into multiple islands, and ISO1 is formed by connecting L-ISO9, M-ISO10, and U-ISO11. By arranging M-ISO10 between L-ISO9 and U-ISO11, lateral diffusion width W1 of L-ISO9 is narrowed. According to this structure, the ISO1 forming region is made narrow. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof.

As an example of a conventional semiconductor device, the following structure of an NPN transistor 281 is known. As shown in FIG. 25, an N-type epitaxial layer (hereinafter referred to as EPI) 283 is formed on a P-type semiconductor substrate 282. In the EPI 283, P-type buried diffusion layers (hereinafter referred to as buried layers) 284 and 285 that diffuse in the vertical direction from the surface of the substrate 282 and P-type diffusion layers 286 and 287 that diffuse from the EPI 283 surface are formed. Is done. The EPI 283 includes a plurality of island regions (hereinafter referred to as islands) by isolation regions (hereinafter referred to as ISO) 288 and 289 formed by connecting the buried layers 284 and 285 and the diffusion layers 286 and 287. It is divided into. For example, an NPN transistor 281 is formed in one of the islands. The NPN transistor 281 is mainly formed of an N type buried layer 290 as a collector region, a P type diffusion layer 291 as a base region, and an N type diffusion layer 292 as an emitter region. Further, the buried layers 284 and 285 are diffused by performing a dedicated heat treatment. On the other hand, the diffusion layers 286 and 287 are also diffused by performing a dedicated heat treatment. By this thermal diffusion process, the buried layers 284 and 285 and the diffusion layers 286 and 287 are connected to form ISO 288 and 289 (see, for example, Patent Document 1).
Japanese Patent Laid-Open No. 9-283646 (pages 3-4 and 6, pages 1 and 5-7)

  As described above, in the conventional semiconductor device, the film thickness of the EPI 283 is determined in consideration of the breakdown voltage of the NPN transistor 281. For example, when the power semiconductor element and the control semiconductor element are formed on the same substrate 282, the film thickness of the EPI 283 is determined in accordance with the breakdown voltage characteristics of the power semiconductor element. Then, the buried layers 284 and 285 crawl up from the surface of the substrate 282 to the EPI 283. On the other hand, the P-type diffusion layers 286 and 287 crawl down from the surface of the EPI 283. With this structure, the buried layers 284 and 285 also have their lateral diffusion widths W23 and W24 widened in accordance with the amount of rise. As a result, there is a problem that the formation region of ISO 288 and 289 is difficult to be reduced.

  In the conventional semiconductor device, the EPI 283 is formed on the substrate 282. An NPN transistor 281 is formed in the EPI 283 partitioned by ISO 288 and 289. EPI 283 is an N-type low impurity concentration region. Due to the alignment accuracy, the formation region of the buried layer 284 and the diffusion layer 291 is shifted, the separation distance L9 between the diffusion layers 284 and 291 is shortened, and the region where the depletion layer extends is narrowed. The NPN transistor 281 has a problem that it is easy to short-circuit between the base region and the ISO, and it is difficult to obtain a desired breakdown voltage characteristic. Further, the breakdown voltage characteristics of the NPN transistor 281 are not stable due to the variation in the separation distance L9.

  Further, in the conventional semiconductor device, in order to realize a desired breakdown voltage of the NPN transistor 281, it is necessary to secure a separation distance L 9 between the diffusion layer 291 and the buried layer 284 at a constant distance. Similarly, the separation distance L10 between the diffusion layer 291 and the diffusion layer 286 needs to be secured at a constant distance. However, there is a problem that it is difficult to reduce the device size of the NPN transistor 281 due to the spread of the lateral diffusion widths W23 and W25 of the buried layer 284 and the diffusion layer 286.

  In the conventional method for manufacturing a semiconductor device, the above-described two thermal diffusion steps are performed in order to connect the buried layers 284 and 285 and the diffusion layers 286 and 287. With this manufacturing method, the buried layers 284 and 285 also have their lateral diffusion widths W23 and W24 widened in accordance with the amount of rising. In addition, the N-type buried layer 290 also rises toward the surface side of the EPI 283 by the thermal diffusion process. As a result, there is a problem that it is difficult to reduce the device size of the ISO 288 and 289 formation region and the NPN transistor 281.

  Further, as shown in FIG. 26, a structure in which the NPN transistors 301 and 302 are adjacent to each other through the ISO 303 will be described. A ground voltage (GND) is applied to the collector region of the NPN transistor 301, and a power supply voltage (Vcc) is applied to the collector region of the NPN transistor 302. In this case, in the NPN transistor 302, a reverse bias is applied to the PN junction region between the P-type ISO 303 and the P-type semiconductor substrate 304 and the N-type EPI 305 and the N-type buried layer 306. Then, the depletion layer extends from the PN junction region to the P-type ISO 303 and the P-type substrate 304 side.

  At this time, in ISO 303, when the impurity concentration of the overlapping region of the P-type buried layer 307 and the P-type diffusion layer 308 becomes low, the depletion layer spreads toward the NPN transistor 301 as shown by the dotted line. End up. When the depletion layer extends to the N-type buried layer 309, there is a problem that the collector region between the NPN transistors 301 and 302 is short-circuited and a leak current is generated. On the other hand, in order to prevent this leakage current, it is necessary to diffuse the buried layer 307 and the diffusion layer 308 more widely and increase the impurity concentration of the overlapping region. In this case, there is a problem that the diffusion width W26 of the buried layer 307 and the diffusion width W27 of the diffusion layer 308 are widened and it is difficult to reduce the device size of the NPN transistors 301 and 302.

  In view of the above circumstances, the semiconductor device according to the present invention includes a one-conductivity-type semiconductor substrate, a reverse-conductivity-type first epitaxial layer formed on the semiconductor substrate, A reverse conductivity type second epitaxial layer formed on one epitaxial layer; and a one conductivity type isolation region that divides the first and second epitaxial layers into a plurality of islands; Is a one conductivity type first buried diffusion layer formed over the semiconductor substrate, the first epitaxial layer and the second epitaxial layer, and one conductivity type formed in the second epitaxial layer. The second buried diffusion layer is connected to the first diffusion layer of one conductivity type formed in the second epitaxial layer.

  In the method for manufacturing a semiconductor device of the present invention, a step of preparing a semiconductor substrate of one conductivity type and forming a first epitaxial layer of a reverse conductivity type on the semiconductor substrate, and a step of forming the first epitaxial layer on the semiconductor substrate. A step of forming a second epitaxial layer of opposite conductivity type on the first epitaxial layer after ion-implanting impurities forming the first buried diffusion layer of conductivity type; and After the impurity forming the second buried diffusion layer of one conductivity type is implanted from the surface, the impurity of forming the diffusion layer of one conductivity type is continuously implanted and thermally diffused, whereby the first conductivity type second buried diffusion layer is implanted. And a step of forming an isolation region by connecting the one buried diffusion layer, the one conductivity type second buried diffusion layer, and the one conductivity type diffusion layer.

  In the present invention, a plurality of diffusion layers constituting the isolation region (hereinafter referred to as ISO) are formed in the depth direction, and the amount of rising or falling of each diffusion layer is reduced. This structure narrows the ISO formation region.

  In the present invention, two epitaxial layers (hereinafter referred to as EPI) are formed on the substrate. With this structure, the diffusion width of ISO formed in the EPI of the first layer is narrowed, and the ISO formation region is narrowed.

  In the present invention, an N type buried diffusion layer (hereinafter referred to as a buried layer) and an N type diffusion layer are connected between the base region of the NPN transistor and the ISO. With this structure, the base region and the ISO are not easily short-circuited, and the breakdown voltage characteristics of the NPN transistor are improved.

  In the present invention, an N-type diffusion layer is formed between the base region of the NPN transistor and the ISO. With this structure, the base region and the ISO are not easily short-circuited, and the breakdown voltage characteristics of the NPN transistor are improved.

  In the present invention, the N-type diffusion layer disposed between the base region of the NPN transistor and the ISO has a triple diffusion structure. With this structure, the base region and the ISO are less likely to be short-circuited.

  In the present invention, the ion implantation process of the buried layer and the diffusion layer constituting the ISO is continuously performed from the EPI surface of the second layer. With this manufacturing method, a dedicated thermal diffusion process for diffusing the buried layer can be reduced, and the spread of the ISO formation region can be prevented.

  In the present invention, the ion implantation process of the buried layer and the diffusion layer constituting the ISO is continuously performed from the EPI surface of the second layer. With this manufacturing method, the number of masks can be reduced and the manufacturing cost can be reduced.

  In the present invention, after forming the LOCOS oxide film, the diffusion layer constituting the ISO is formed. With this manufacturing method, crystal defects generated on the surface of the diffusion layer forming region and in the vicinity thereof can be reduced.

  In the present invention, the diffusion layer constituting the ISO and the diffusion layer constituting the back gate region of the MOS transistor are formed in a common process. With this manufacturing method, the thermal diffusion process is reduced and the spread of the ISO formation region can be suppressed.

  The semiconductor device according to the first embodiment of the present invention will be described below with reference to FIG.

  As shown in FIG. 1, isolation regions (hereinafter referred to as ISO) 1 to 3 are formed in a lattice shape on the entire IC, and there are various island regions (hereinafter referred to as islands) surrounded by ISO. A variety of semiconductor elements are formed. As shown, an NPN transistor 4 is formed on one island, and an N-channel MOS transistor 5 is formed on the other island.

  First, as shown in the figure, the ISOs 1 to 3 penetrate through first and second N-type epitaxial layers (hereinafter referred to as EPI) 7 and 8 on a P-type single crystal silicon substrate 6. Divide into multiple islands. ISOs 1-3 are composed of three diffusion layers like a snowman. For example, in ISO 1 to 3, P-type buried diffusion layers (hereinafter referred to as buried layers) 9, 10, 12, 13, 15, 16 and P-type diffusion layers 11, 14, 17 from the bottom. Consists of In the cross section shown in FIG. 1, ISOs 1 to 3 are individually illustrated, but are integrally formed so as to surround the island.

  The first EPI 7 is formed on the substrate 6. A second EPI 8 is formed on EPI 7.

  P type buried layers 9, 12, 15 (hereinafter referred to as L-ISO 9, 12, 15) are formed across the substrate 6, the first layer, and the second layer EPIs 7, 8. This L-ISO is ion-implanted from the surface of the first EPI7.

  P-type buried layers 10, 13, and 16 (hereinafter referred to as M-ISO 10, 13, and 16) are formed in the second EPI 8. The M-ISOs 10, 13, and 16 are connected to the L-ISOs 9, 12, and 15, respectively. This M-ISO is ion-implanted from the surface of the second EPI8.

  P-type diffusion layers 11, 14 and 17 (hereinafter referred to as U-ISO 11, 14 and 17) are formed in the second EPI 8. U-ISO11,14,17 connects with M-ISO10,13,16. This U-ISO is ion-implanted from the surface of the second EPI 8 layer.

  As illustrated, in ISO 1, M-ISO 10 is arranged between L-ISO 9 and U-ISO 11. The M-ISO 10 connects the L-ISO 9 climbing from the first layer EPI 7 and the U-ISO 11 climbing from the surface of the second EPI 8. With this structure, the amount of climbing of the L-ISO 9 is reduced, and the lateral diffusion width W1 of the L-ISO 9 is also greatly reduced. That is, the formation region of ISO1 is determined by the lateral diffusion width W1 of L-ISO9, so that the formation region of ISO1 is significantly reduced.

  Similarly, in ISO 2 and 3, the diffusion widths W 2 and W 3 of L-ISO 12 and 15 are significantly narrowed, and the formation regions of ISO 2 and 3 are also greatly reduced. Also, in ISO 1 to 3, the M-ISOs 10, 13, and 16 are formed, so that the amount of creeping down of the U-ISOs 11, 14, and 17 is reduced, and the lateral diffusion widths W4 to W6 of the U-ISO are reduced. Is reduced.

  Further, two layers of EPIs 7 and 8 are deposited on the substrate 6. The film thickness of the first EPI 7 is, for example, 0.6 μm, and the film thickness of the second EPI 8 is, for example, 1.0 μm. With this structure, the film thickness of the first EPI 7 is reduced. And the amount of climbing of L-ISO9,12,15 is reduced, The spreading | diffusion width W1-W3 to the horizontal direction is also reduced significantly. And the formation area of ISO1-3 is reduced significantly.

  Next, the NPN transistor 4 mainly includes a substrate 6, first and second EPIs 7 and 8, an N-type buried layer 18 as a collector region, and a P-type diffusion layer as a base region. 19, an N type diffusion layer 20 as an emitter region, N type buried layers 21 and 22, and N type diffusion layers 23 and 24.

  The N type buried layers 21 and 22 are formed over the first and second EPIs 7 and 8. The N type buried layer is disposed between the P type diffusion layer 19 and the ISOs 1 and 2.

  The N type diffusion layers 23 and 24 are formed in the second EPI 8. The N type diffusion layer 23 is connected to the N type buried layer 21, and the N type diffusion layer 24 is connected to the N type buried layer 22. The N type diffusion layer is disposed between the P type diffusion layer 19 and the ISOs 1 and 2. Although not shown, for example, the N type diffusion layer is arranged in a ring so as to surround the periphery of the P type diffusion layer 19.

  LOCOS oxide films (hereinafter referred to as LOCOS) 25 to 27 are formed on the EPI 8. In the flat portion of the LOCOS 25 to 27, the film thickness is, for example, about 3000 to 10,000 mm. ISOs 1 and 2 are formed below the LOCOSs 25 and 27.

  An insulating layer 28 is formed on the upper surface of the EPI 8. The insulating layer 28 is formed of an NSG (Nondoped Silicate Glass) film, a BPSG (Boron Phospho Silicate Glass) film, or the like. Then, contact holes 29 to 31 are formed in the insulating layer 28 by dry etching.

  In the contact holes 29 to 31, for example, an aluminum alloy film made of an Al—Si film, an Al—Si—Cu film, an Al—Cu film, or the like is selectively formed, and an emitter electrode 32, a base electrode 33, and a collector electrode 34 are formed. Is formed. At this time, the collector electrode 34 is connected to the N type diffusion layer 24 through the contact hole 31. By using the N type diffusion layer 24 and the N type buried layer 22, the sheet resistance value in the collector region is reduced. The emitter electrode 32, the base electrode 33, and the collector electrode 34 may be formed by embedding a metal plug such as tungsten (W) in the contact holes 29 to 31 and forming an aluminum alloy film thereon.

  Next, the N-channel MOS transistor 5 mainly includes a substrate 6, first and second EPIs 7 and 8, an N-type buried layer 35, and a P-type diffusion layer as a back gate region. 36, 37, N-type diffusion layers 38 and 40 as source regions, N-type diffusion layers 39 and 41 as drain regions, and a gate electrode 42.

  The N type buried layer 35 is formed across the substrate 6 and the first EPI 7.

  The P-type diffusion layer 36 is formed in the first and second EPIs 7 and 8 and is used as a back gate region. A P-type diffusion layer 37 is formed so as to overlap with the P-type diffusion layer 36 and is used as a back gate extraction region.

  N-type diffusion layers 38 and 39 are formed in the P-type diffusion layer 36. The N type diffusion layer 38 is used as a source region. The N type diffusion layer 39 is used as a drain region. An N type diffusion layer 40 is formed in the N type diffusion layer 38, and an N type diffusion layer 41 is formed in the N type diffusion layer 39. With this structure, the drain region has a DDD (Double Diffused Drain) structure. The P type diffusion layer 36 located between the N type diffusion layers 38 and 39 is used as a channel region. A gate oxide film 43 is formed on the upper surface of the EPI 8 used as the channel region.

  The gate electrode 42 is formed on the upper surface of the gate oxide film 43. The gate electrode 42 is formed to have a desired film thickness by using, for example, a polysilicon film and a tungsten silicide film. Although not shown, a silicon oxide film is formed on the upper surface of the tungsten silicide film.

  LOCOS 27, 44 and 45 are formed in the EPI 8.

  An insulating layer 28 is formed on the upper surface of the EPI 8. Then, contact holes 46 to 48 are formed in the insulating layer 28 by dry etching.

  Similar to the above, an aluminum alloy film is selectively formed in the contact holes 46 to 48, and a source electrode 49, a drain electrode 50, and a back gate electrode 51 are formed. The source electrode 49, the drain electrode 50, and the back gate electrode 51 may be formed by embedding a metal plug such as tungsten (W) in the contact holes 46 to 48 and forming an aluminum alloy film thereon.

  Although details will be described later in the method of manufacturing a semiconductor device, a dedicated thermal diffusion process for diffusing each of L-ISO 9, 12, 15, M-ISO 10, 13, 16 and U-ISO 11, 14, 17 is reduced. ing. In particular, by omitting a dedicated thermal diffusion process for diffusing the L-ISOs 9, 12, and 15, the amount of creeping of the N-type buried layers 18 and 35 is reduced, and the film thickness of the EPIs 7 and 8 is reduced. can do.

  In the conventional structure, the film thickness of the EPI 283 (see FIG. 25) was 2.1 μm, for example, but in this embodiment, the combined film thickness of the first and second EPIs 7 and 8 is For example, 1.6 μm. In particular, the distance L1 between the P-type diffusion layer 19 and the L-ISO 9 can be reduced by reducing the film thickness of the first EPI 7 and further reducing the lateral diffusion width W1 of the L-ISO 9. it can. Further, as described above, the distance L2 between the P-type diffusion layer 19 and the U-ISO 11 can be narrowed by narrowing the lateral diffusion width W4 of the U-ISO 11. In the conventional structure, the distance L9 (see FIG. 25) between the P-type diffusion layer 291 (see FIG. 25) and the P-type buried layer 284 (see FIG. 25) is, for example, 1.7 μm. The separation distance L10 (see FIG. 25) between the mold diffusion layer 291 and the P-type diffusion layer 286 (see FIG. 25) was, for example, 2.0 μm. However, in the present embodiment, the separation distance L1 is, for example, 1.32 μm, and the separation distance L2 is, for example, 1.58 μm. As a result, while maintaining the breakdown voltage characteristics of the NPN transistor 4, the space between the base region and ISO is narrowed, and the device size of the NPN transistor 4 is reduced.

  Further, as described above, between the P-type diffusion layer 19 and the P-type ISOs 1 and 2, the connected N-type buried layer 21, the N-type diffusion layer 23, and the connected N-type buried layer. A layer 22 and an N-type diffusion layer 24 are disposed. By arranging the connected N type buried layers 21 and 23 and the connected N type buried layers 22 and 24, the EPI 7 between the P type diffusion layer 19 and the P type ISOs 1 and 2 is provided. , 8 is increased in impurity concentration. With this structure, with respect to the depletion layer spreading from the PN junction region between the P-type diffusion layer 19 and the N-type EPI 8, the depletion layer spreading toward the N-type EPI 8 is difficult to spread. Similarly, with respect to the depletion layer extending from the PN junction region between the P-type ISOs 1 and 2 and the N-type EPIs 7 and 8, the depletion layer extending toward the N-type EPIs 7 and 8 is difficult to spread. Accordingly, the spread of the depletion layer is adjusted by the connected N-type buried layers 21 and 23 and the connected N-type buried layers 22 and 24, so that the base region and the ISO are short-circuited. Thus, the breakdown voltage characteristic of the NPN transistor 4 is improved.

  In the present embodiment, the case where only M-ISOs 10, 13, and 16 are arranged between L-ISOs 9, 12, and 15 and U-ISOs 11, 14, and 17 in ISO 1 to 3, has been described. However, the present invention is not limited to this case. For example, a plurality of P-type buried layers may be disposed between the L-ISO and the U-ISO.

  In the present embodiment, the arrangement regions of the connected N-type buried layers 21 and 23 and the connected N-type buried layers 22 and 24 are variously designed according to the breakdown voltage characteristics of the NPN transistor 4. It can be changed. For example, the connected N-type buried layers 21 and 23 and the connected N-type are provided in a region where a desired withstand voltage characteristic is ensured by the separation distance between the P-type diffusion layer 19 and the P-type ISOs 1 and 2. The buried layers 22 and 24 of the mold are not necessarily arranged. That is, in the region where the separation distance between the P-type diffusion layer 19 and the P-type ISOs 1 and 2 is short, at least the connected N-type buried layers 21 and 23 and the connected N-type buried layer 22, 24 should just be arrange | positioned. In addition, various modifications can be made without departing from the scope of the present invention.

  A semiconductor device according to a second embodiment of the present invention will be described with reference to FIG.

  As shown in FIG. 2, an NPN transistor 64 is formed on one island partitioned by ISO 61 to 63, and an N-channel MOS transistor 65 is formed on another island. Although not shown, P-channel MOS transistors, PNP transistors, and the like are formed on other islands.

  First, as shown in the figure, the ISOs 61 to 63 penetrate through the first and second N-type EPIs 67 and 68 on the P-type single crystal silicon substrate 66 as shown in the figure. Divide into islands. The ISO 61 includes a P-type buried layer 69 (hereinafter referred to as L-ISO 69), a P-type buried layer 70 (hereinafter referred to as M-ISO 70), and a P-type diffusion layer 71 (hereinafter referred to as U-). It is called ISO71.) Similarly, the ISO 62 includes P type buried layers 72 and 73 (hereinafter referred to as L-ISO 72 and M-ISO 73) and a P type diffusion layer 74 (hereinafter referred to as U-ISO 74). The ISO 63 includes P-type buried layers 75 and 76 (hereinafter referred to as L-ISO 75 and M-ISO 76) and a P-type diffusion layer 77 (hereinafter referred to as U-ISO 77).

  A first EPI 67 is formed on the substrate 66. A second EPI 68 is formed on the first EPI 67.

  The L-ISOs 69, 72, and 75 are formed across the substrate 66, the first layer, and the second layer of EPIs 67 and 68.

  The M-ISOs 70, 73, and 76 are formed in the second EPI 68. The M-ISOs 70, 73, and 76 are connected to the L-ISOs 69, 72, and 75.

  The U-ISOs 71, 74, and 77 are formed in the second EPI 68. The U-ISOs 71, 74, and 77 are connected to the M-ISOs 70, 73, and 76, respectively.

  As illustrated, in ISO 61, M-ISO 70 is arranged between L-ISO 69 and U-ISO 71. The M-ISO 70 connects the L-ISO 69 climbing from the EPI 67 and the U-ISO 71 climbing from the EPI 68 surface.

  With this structure, the amount of climbing of the L-ISO 69 is reduced, and the diffusion width W7 in the lateral direction of the L-ISO is also greatly reduced. That is, the ISO 61 formation region is determined by the lateral diffusion width W7 of the L-ISO 69, so that the ISO 61 formation region is significantly reduced. Similarly, also in ISOs 62 and 63, the diffusion widths W8 and W9 of L-ISOs 72 and 75 are significantly narrowed, and the formation regions of ISOs 62 and 63 are also greatly reduced. In addition, the lateral diffusion widths W10 to W12 of the U-ISOs 71, 74, and 77 are also reduced.

  Further, two layers of EPI 67 and 68 are deposited on the substrate 66. The film thickness of the first EPI 67 is, for example, 0.6 μm, and the film thickness of the second EPI 68 is, for example, 1.0 μm. With this structure, the film thickness of the first EPI 67 is reduced. Further, the amount of climbing of the L-ISOs 69, 72, and 75 is reduced, and the lateral diffusion widths W7 to W9 are also greatly reduced. And the formation area of ISO61-63 is reduced significantly.

  Next, the NPN transistor 64 mainly includes a substrate 66, EPIs 67 and 68, an N-type buried layer 78 as a collector region, a P-type diffusion layer 79 as a base region, and an N-type as an emitter region. A type diffusion layer 80 and N type diffusion layers 81-86.

  The N type diffusion layers 81 to 86 are formed in the second EPI 68. The N type diffusion layers 81, 83, and 85 are formed so as to overlap each other, and the N type diffusion layers 82, 84, and 86 are formed so as to overlap each other. The N type diffusion layers 81 to 86 are disposed between the P type diffusion layer 79 and the ISOs 61 and 62. Although not shown, for example, the N type diffusion layer 81 and the N type diffusion layer 82 are arranged in a ring so as to surround the periphery of the P type diffusion layer 79. The N-type diffusion layer 83 and the N-type diffusion layer 84 and the N-type diffusion layer 85 and the N-type diffusion layer 86 are similarly arranged in a ring so as to surround the P-type diffusion layer 79. .

  LOCOSs 87-89 are formed in the EPI 68. P-type ISOs 61 and 62 are formed below the LOCOSs 87 and 89.

  An insulating layer 90 is formed on the upper surface of the EPI 68. The insulating layer 90 is formed by an NSG film, a BPSG film, or the like. Then, contact holes 91 to 93 are formed in the insulating layer 90 by dry etching.

  Similar to the first embodiment, an aluminum alloy film is selectively formed in the contact holes 91 to 93, and an emitter electrode 94, a base electrode 95, and a collector electrode 96 are formed. At this time, the collector electrode 96 is connected to the N type diffusion layer 86 through the contact hole 93. Then, by using the N-type diffusion layers 82, 84, 86, the sheet resistance value in the collector region is reduced.

  Next, the N-channel MOS transistor 65 mainly includes a substrate 66, EPIs 67 and 68, an N-type buried layer 97, P-type diffusion layers 98 and 99 as back gate regions, and a source region. N-type diffusion layers 100 and 102, N-type diffusion layers 101 and 103 as drain regions, and a gate electrode 104.

  The N type buried layer 97 is formed across the substrate 66 and the EPI 67.

  The P-type diffusion layer 98 is formed in the EPIs 67 and 68 and used as a back gate region. A P-type diffusion layer 99 is formed so as to overlap with the P-type diffusion layer 98 and is used as a back gate extraction region.

  N-type diffusion layers 100 and 101 are formed in the P-type diffusion layer 98. The N type diffusion layer 100 is used as a source region. The N type diffusion layer 101 is used as a drain region. An N-type diffusion layer 102 is formed in the N-type diffusion layer 100, and an N-type diffusion layer 103 is formed in the N-type diffusion layer 101. With this structure, the drain region has a DDD structure. The P type diffusion layer 98 located between the N type diffusion layers 100 and 101 is used as a channel region. A gate oxide film 105 is formed on the upper surface of the EPI 68 used as the channel region.

  The gate electrode 104 is formed on the upper surface of the gate oxide film 105. The gate electrode 104 is formed to have a desired film thickness by using, for example, a polysilicon film and a tungsten silicide film. Although not shown, a silicon oxide film is formed on the upper surface of the tungsten silicide film.

  LOCOSs 89, 106, and 107 are formed in the EPI 68.

  An insulating layer 90 is formed on the upper surface of the EPI 68. Then, contact holes 108 to 110 are formed in the insulating layer 90 by dry etching.

  In the contact holes 108 to 110, an aluminum alloy film is selectively formed, and a source electrode 111, a drain electrode 112, and a back gate electrode 113 are formed.

  Although details will be described later in the method of manufacturing a semiconductor device, a dedicated thermal diffusion process for diffusing each of L-ISO 69, 72, 75, M-ISO 70, 73, 76 and U-ISO 71, 74, 77 is reduced. ing. In particular, by omitting a dedicated thermal diffusion process for diffusing L-ISO 69, 72, 75, the amount of creeping up of N type buried layers 78, 97 is reduced, and the film thickness of EPI 67, 68 is reduced. can do.

  In the conventional structure, the film thickness of EPI283 (see FIG. 25) is 2.1 μm, for example, but in this embodiment, the combined film thickness of EPI67 and 68 is 1.6 μm, for example. In particular, the distance L3 between the P-type diffusion layer 79 and the L-ISO 69 can be reduced by reducing the film thickness of the first EPI 67 and further reducing the lateral diffusion width W7 of the L-ISO 69. it can. Further, as described above, by reducing the lateral diffusion width W10 of the U-ISO 71, the separation distance L4 between the P-type diffusion layer 79 and the U-ISO 71 can be reduced.

  In the conventional structure, the distance L9 (see FIG. 25) between the P-type diffusion layer 291 (see FIG. 25) and the P-type buried layer 284 (see FIG. 25) is, for example, 1.7 μm. The separation distance L10 (see FIG. 25) between the mold diffusion layer 291 and the P-type diffusion layer 286 (see FIG. 25) was, for example, 2.0 μm. However, in the present embodiment, the separation distance L3 is, for example, 1.23 μm, and the separation distance L4 is, for example, 1.55 μm. As a result, while maintaining the breakdown voltage characteristics of the NPN transistor 64, the space between the base region and the ISO is narrowed, and the device size of the NPN transistor 64 is reduced.

  Further, as described above, the N type diffusion layers 81 to 86 are arranged between the P type diffusion layer 79 and the P type ISOs 61 and 62. By arranging the N type diffusion layers 81 to 86, the impurity concentrations of the EPIs 67 and 68 between the P type diffusion layer 79 and the P type ISOs 61 and 62 are increased. With this structure, with respect to the depletion layer spreading from the PN junction region between the P-type diffusion layer 79 and the N-type EPI 68, the depletion layer spreading toward the N-type EPI 68 becomes difficult to spread. Similarly, with respect to the depletion layer extending from the PN junction region between the P-type ISOs 61 and 62 and the N-type EPIs 67 and 68, the depletion layer extending toward the N-type EPIs 67 and 68 is difficult to spread. As a result, the spread of the depletion layer is adjusted by the N type diffusion layers 81 to 86, so that it is difficult for the base region and the ISO to be short-circuited, and the breakdown voltage characteristics of the NPN transistor 64 are improved.

  In the present embodiment, in ISO 61-63, the case where only M-ISOs 70, 73, 76 are arranged between L-ISOs 69, 72, 75 and U-ISOs 71, 74, 77 has been described. However, the present invention is not limited to this case. For example, a plurality of P-type buried layers may be disposed between the L-ISO and the U-ISO.

  In the present embodiment, various design changes can be made to the arrangement region of the N type diffusion layers 81 to 86 according to the breakdown voltage characteristics of the NPN transistor 64. For example, the N type diffusion layers 81 to 86 are not necessarily arranged in a region where desired breakdown voltage characteristics are ensured by the separation distance between the P type diffusion layer 79 and the P type ISOs 61 and 62. That is, at least the N type diffusion layers 81 to 86 may be disposed in a region where the separation distance between the P type diffusion layer 79 and the P type ISOs 61 and 62 is short.

  In this embodiment, the case where the N-type diffusion layers 81, 83, and 85 and the N-type diffusion layers 82, 84, and 86 are formed so as to overlap each other is described. However, the present invention is limited to this case. is not. For example, only the N type diffusion layers 81 and 82 may be used. In addition, a double diffusion structure in which the N type diffusion layers 81 and 83 and the N type diffusion layers 82 and 84 overlap each other may be used. Further, it may be a case of a further multiple diffusion structure such as a quadruple diffusion structure. In addition, various modifications can be made without departing from the scope of the present invention.

  Next, a method for manufacturing a semiconductor device according to a third embodiment of the present invention will be described with reference to FIGS. 3 to 9 is the method for manufacturing the semiconductor device shown in FIG. 1, the same reference numerals are used for the same components.

  First, as shown in FIG. 3, a P-type single crystal silicon substrate 6 is prepared. A silicon oxide film 121 is formed on the substrate 6, and the silicon oxide film 121 is selectively removed so that openings are formed on the formation regions of the N type buried layers 122 and 123. Then, using the silicon oxide film 121 as a mask, a liquid source 124 containing an N-type impurity such as antimony (Sb) is applied to the surface of the substrate 6. Thereafter, antimony (Sb) is thermally diffused to form N type buried layers 122 and 123, and then the silicon oxide film 121 and the liquid source 124 are removed.

  Next, as shown in FIG. 4, a first N-type EPI 7 is formed on the substrate 6. At this time, the EPI 7 is formed so that the film thickness is about 0.5 to 0.7 μm. The N type buried layers 122 and 123 (see FIG. 3) are thermally diffused by the heat treatment in the formation process of the EPI 7 to form the N type buried layers 18 and 35.

  Next, a silicon oxide film 125 is formed on the EPI 7, and N-type diffusion layers 126 and 127 are formed using an ion implantation technique. Thereafter, a photoresist 128 is formed on the silicon oxide film 125, and an opening is formed in the photoresist 128 on the region where the P type buried layers 129 to 131 are formed. Thereafter, a P-type impurity such as boron (B +) is ion-implanted from the surface of the EPI 7. Then, the photoresist 128 and the silicon oxide film 125 are removed.

  Next, as shown in FIG. 5, a second N-type EPI 8 is formed on the EPI 7. At this time, the EPI 8 is formed so that the film thickness is about 0.9 to 1.1 μm. The N type buried layers 126 and 127 (see FIG. 4) and the P type buried layers 129, 130, and 131 (see FIG. 4) are thermally diffused by the heat treatment in the formation process of the EPI 8, and the N type buried layers. Buried layers 21 and 22 and L-ISOs 9, 12, and 15 are formed.

  Thereafter, a silicon oxide film 132 is formed on the EPI 8, and a photoresist 133 is formed on the silicon oxide film 132. Then, an opening is formed in the photoresist 133 on the region where the N type diffusion layers 134 and 135 are to be formed. N-type impurities such as phosphorus (P +) are ion-implanted from the surface of the EPI 8.

  Next, as shown in FIG. 6, the photoresist 133 (see FIG. 5) is removed and thermally diffused to form N-type diffusion layers 23 and 24, and then the silicon oxide film 132 (see FIG. 5) is removed. . Then, LOCOS 25 to 27, 44, and 45 are formed in a desired region of EPI8. A silicon oxide film 136 is formed on the upper surface of the EPI 8, and a photoresist 137 is formed on the silicon oxide film 136. Then, an opening is formed in the photoresist 137 on the region where the P type buried layers 138 to 141 are formed. Thereafter, a P-type impurity such as boron (B ++) is ion-implanted from the surface of the EPI 8.

  Next, a second ion implantation is performed using the same photoresist 137 without thermally diffusing the P type buried layers 138 to 141. A P-type impurity such as boron (B +) is ion-implanted from above the photoresist 137. P-type diffusion layers 142 to 145 are formed by this second ion implantation step. That is, in the present embodiment, dedicated thermal diffusion steps for thermally diffusing the P type buried layers 138 to 141 and the P type diffusion layers 142 to 145 are reduced.

  Here, after the LOCOSs 25, 27, 44, 45 are formed, boron (B ++, B +) is ion-implanted from above the LOCOSs 25, 27, 44, 45. With this manufacturing method, crystal defects are generated from the surface of EPI 8 damaged by ion implantation of boron (B ++, B +) having a relatively large molecular level due to the heat at the time of forming LOCOS 25, 27, 44, 45. Can be prevented. That is, by implanting boron ions after forming LOCOS, it is possible to prevent heat from being applied to the damaged region during LOCOS formation.

  Next, as shown in FIG. 7, the photoresist 137 (see FIG. 6) is removed and thermally diffused to form M-ISO 10, 13, 16, U-ISO 11, 14, 17, and a P-type diffusion layer 36. Thereafter, the silicon oxide film 136 (see FIG. 6) is removed. In the following description, the P-type buried layer 140 (see FIG. 6) and the P-type diffusion layer 144 (see FIG. 6) are connected by thermal diffusion to form the P-type diffusion layer 36.

  As described above, the thermal diffusion process is performed after the second ion implantation process is continuously performed without performing the thermal diffusion process after the first ion implantation process. With this manufacturing method, the M-ISO 10, 13, 16, U-ISO 11, 14, 17, and the P-type diffusion layer 36 are formed by a single thermal diffusion process. That is, by omitting the dedicated thermal diffusion step after the first and second ion implantations, the lateral diffusion widths W1, W2, and W3 (see FIG. 1) of the L-ISOs 9, 12, and 15 are suppressed, and the ISO1 The formation region of 2, 3 (see FIG. 1) can also be narrowed.

  Further, in the first ion implantation step, ion implantation is performed with a higher acceleration voltage than in the second ion implantation step. And M-ISO10,13,16 is formed in the vicinity of L-ISO9,12,15. With this manufacturing method, it is possible to reliably connect the M-ISOs 10, 13, 16 and the L-ISOs 9, 12, 15 while reducing the amount of scooping of the L-ISOs 9, 12, 15.

  Furthermore, by making the impurity concentrations of L-ISOs 9, 12, and 15 low, the lateral diffusion widths W1 to W3 of L-ISOs 9, 12, and 15 can be suppressed, and the formation regions of ISOs 1 to 3 can be narrowed. . Similarly, the lateral diffusion widths W4 to W6 (see FIG. 1) of the U-ISOs 11, 14, and 17 can be suppressed by reducing the amount of creeping down of the U-ISOs 11, 14, and 17.

  Thereafter, a gate oxide film 43 is formed on the EPI 8. Then, a gate electrode 42 made of, for example, a polysilicon film or a tungsten silicide film is formed on the gate oxide film 43. Thereafter, a photoresist 146 is formed on the silicon oxide film used as the gate oxide film 43. Then, an opening is formed in the photoresist 146 on the region where the N type diffusion layers 147 and 148 are formed. Then, an N-type impurity such as phosphorus (P +) is ion-implanted from the EPI 8 surface. At this time, by using the LOCOS 27 and 44 and the gate electrode 42 as a mask, the N-type diffusion layers 147 and 148 can be formed with high positional accuracy. Thereafter, the photoresist 146 is removed and thermal diffusion is performed. In this thermal diffusion step, the N type diffusion layers 147 and 148 are thermally diffused to form the N type diffusion layers 38 and 39 (see FIG. 8).

  Next, as shown in FIG. 8, a photoresist 149 is formed on the gate oxide film 43. Then, an opening is formed in the photoresist 149 on the region where the P type diffusion layer 150 is to be formed. P-type impurities such as boron (B) are ion-implanted from the EPI 8 surface. Thereafter, the photoresist 149 is removed and thermal diffusion is performed. In this thermal diffusion step, the P type diffusion layer 150 is thermally diffused to form the P type diffusion layer 19 (see FIG. 9).

  Finally, as shown in FIG. 9, after forming the N type diffusion layers 20, 40, 41, the P type diffusion layer 37 is formed. Thereafter, for example, an NSG film and a BPSG film are deposited on the EPI 8 as the insulating layer 28. Then, contact holes 29 to 31 and 46 to 48 are formed in the insulating layer 28 by dry etching. In the contact holes 29 to 31 and 46 to 48, for example, an aluminum alloy film made of an Al—Si film, an Al—Si—Cu film, an Al—Cu film or the like is selectively formed, and an emitter electrode 32 and a base electrode 33 are formed. The collector electrode 34, the source electrode 49, the drain electrode 50, and the back gate electrode 51 are formed.

  In the present embodiment, a description will be given of a case where two ion implantation steps are continuously performed using the same resist mask from above LOCOS 25 to 27, 44, and 45 when forming the diffusion layer constituting the ISO. However, the present invention is not limited to this case. For example, using the same resist mask from above LOCOS 25-27, 44, 45, three or more ion implantation steps are continuously performed, and between L-ISO 9, 12, 15 and U-ISO 11, 14, 17 A plurality of P-type buried layers may be formed. In addition, various modifications can be made without departing from the scope of the present invention.

  Next, a method for manufacturing a semiconductor device according to the fourth embodiment of the present invention will be described with reference to FIGS. 10 to 17 is the method for manufacturing the semiconductor device shown in FIG. 2, and the same reference numerals are used for the same components.

  First, as shown in FIG. 10, a P-type single crystal silicon substrate 66 is prepared. A silicon oxide film 161 is formed on the substrate 66, and the silicon oxide film 161 is selectively removed so that openings are formed on the formation regions of the N type buried layers 162 and 163. Then, using the silicon oxide film 161 as a mask, a liquid source 164 containing an N-type impurity such as antimony (Sb) is applied to the surface of the substrate 66. Thereafter, antimony (Sb) is thermally diffused to form N type buried layers 162 and 163, and then the silicon oxide film 161 and the liquid source 164 are removed.

  Next, as shown in FIG. 11, a first N-type EPI 67 is formed on the substrate 66. At this time, the EPI 67 is formed so that the film thickness is about 0.5 to 0.7 μm. By the heat treatment in the step of forming the EPI 67, the N type buried layers 162 and 163 (see FIG. 10) are thermally diffused to form N type buried layers 78 and 97.

  Next, a silicon oxide film 165 is formed on the EPI 67, and a photoresist 166 is formed on the silicon oxide film 165. Then, an opening is formed in the photoresist 166 on the region where the P type buried layers 167 to 169 are formed. Thereafter, a P-type impurity such as boron (B ++) is ion-implanted from the surface of the EPI 67. Then, the photoresist 166 and the silicon oxide film 165 are removed.

  Next, as shown in FIG. 12, a second N-type EPI 68 is formed on the EPI 67. At this time, the EPI 68 is formed so that the film thickness is about 0.9 to 1.1 μm. The P-type buried layers 167 to 169 (see FIG. 11) are thermally diffused by heat treatment in the formation process of the EPI 68, and L-ISOs 69, 72, and 75 are formed.

  Thereafter, a silicon oxide film 170 is formed on the EPI 68, and then a photoresist 171 is formed on the silicon oxide film 170. Openings are formed in the photoresist 171 over the region where the N type diffusion layers 172 to 175 are to be formed. First, in order to form the N-type diffusion layers 172 and 173, for example, phosphorus (P +) of an N-type impurity is ion-implanted from the surface of the EPI 68. Next, in order to form the N type diffusion layers 174 and 175, for example, phosphorus (P +) of an N type impurity is ion-implanted continuously from the surface of the EPI 68. Thereafter, the photoresist 171 is removed, and after thermal diffusion, the silicon oxide film 170 is removed. In this thermal diffusion step, the N type diffusion layers 172 to 175 are thermally diffused, and N type diffusion layers 81 to 84 (see FIG. 13) are formed.

  Next, as shown in FIG. 13, LOCOSs 87 to 89, 106, and 107 are formed in desired regions of the EPI 68. A silicon oxide film 176 is formed on the upper surface of the EPI 68, and a photoresist 177 is formed on the silicon oxide film 176. Then, an opening is formed in the photoresist 177 on the region where the P type buried layers 178 to 180 and 181 are formed. Thereafter, a P-type impurity such as boron (B ++) is ion-implanted from the surface of the EPI 68.

  Next, a second ion implantation is performed using the same photoresist 177 without thermally diffusing the P type buried layers 178 to 181. P type impurities such as boron (B +) are ion-implanted from above the photoresist 177. P-type diffusion layers 182 to 185 are formed by the second ion implantation process. Thereafter, the photoresist 177 is removed. In other words, in the present embodiment, a dedicated thermal diffusion process for thermally diffusing the P type buried layers 178 to 181 and the P type diffusion layers 182 to 185 is reduced.

  Here, after the LOCOSs 87, 89, 106, 107 are formed, boron (B ++, B +) is ion-implanted from above the LOCOSs 87, 89, 106, 107. Due to this manufacturing method, crystal defects are generated from the surface of EPI 68 damaged by ion implantation of boron (B ++, B +) having a relatively large molecular level due to the heat at the time of forming LOCOS 87, 89, 106, 107. Can be prevented. That is, by implanting boron ions after forming LOCOS, it is possible to prevent heat from being applied to the damaged region during LOCOS formation.

  Next, as shown in FIG. 14, a photoresist 186 is formed on the silicon oxide film 176. Openings are formed in the photoresist 186 over the region where the N type diffusion layers 187 and 188 are to be formed. Then, an N-type impurity such as phosphorus (P +) is ion-implanted from the surface of the EPI 68. Thereafter, the photoresist 186 is removed, and after thermal diffusion, the silicon oxide film 176 is removed.

  In this thermal diffusion step, the P type buried layers 178 to 181, the P type diffusion layers 182 to 185 and the N type diffusion layers 187 and 188 are thermally diffused, and M-ISOs 70, 73 and 76 (FIG. 15). U-ISO 71, 74, 77 and P-type diffusion layer 98 (see FIG. 15) and N-type diffusion layers 85, 86 (see FIG. 15) are formed. In the following description, the P-type buried layer 180 and the P-type diffusion layer 184 are connected by thermal diffusion to form a P-type diffusion layer 98 (see FIG. 15). Further, although not shown, the N-type diffusion layers 85 and 86 are formed in the same process as the N-type diffusion layer constituting the back gate region of the P-channel MOS transistor. However, the N-type diffusion layers 85 and 86 may be formed or not formed.

  As described above with reference to FIGS. 13 and 14, the second ion implantation step is continuously performed after the first ion implantation step without performing the thermal diffusion step. Further, an ion implantation process for forming N-type diffusion layers 85 and 86 is performed without performing a thermal diffusion process, and then a thermal diffusion process is performed. With this manufacturing method, the M-ISO 70, 73, 76, the U-ISO 71, 74, 77, the P-type diffusion layer 98, and the N-type diffusion layers 85, 86 are formed by a single thermal diffusion process. That is, by omitting the two thermal diffusion steps after the first and second ion implantations, the lateral diffusion widths W7 to W9 (see FIG. 2) of the L-ISOs 69, 72, and 75 are suppressed, and the ISO 61, The formation region of 62, 63 (see FIG. 2) can also be narrowed.

  Further, in the first ion implantation step, ion implantation is performed with a higher acceleration voltage than in the second ion implantation step. And M-ISO70,73,76 is formed in the vicinity of L-ISO69,72,75. Although the amount of scooping up of the L-ISOs 69, 72, 75 is reduced by this manufacturing method, the M-ISOs 70, 73, 76 and the L-ISOs 69, 72, 75 can be reliably connected.

  Further, by reducing the impurity concentration of L-ISO 69, 72, 75, the lateral diffusion widths W7-W9 of L-ISO 69, 72, 75 can be suppressed, and the formation region of ISO 61-63 can be narrowed. . Similarly, the lateral diffusion widths W10 to W12 (see FIG. 2) of the U-ISOs 71, 74, and 77 can be suppressed by reducing the amount of creeping down of the U-ISOs 71, 74, and 77.

  Next, as shown in FIG. 15, a gate oxide film 105 is formed on the EPI 68. Then, a gate electrode 104 in which, for example, a polysilicon film and a tungsten silicide film are stacked is formed on the gate oxide film 105. Thereafter, a photoresist 189 is formed on the gate oxide film 105. Then, an opening is formed in the photoresist 189 on the region where the N type diffusion layers 190 and 191 are to be formed. N-type impurities such as phosphorus (P +) are ion-implanted from the EPI 68 surface. At this time, by using the LOCOSs 89 and 106 and the gate electrode 104 as a mask, the N-type diffusion layers 190 and 191 can be formed with high positional accuracy. Thereafter, the photoresist 189 is removed and thermal diffusion is performed. In this thermal diffusion step, the N type diffusion layers 190 and 191 are thermally diffused to form the N type diffusion layers 100 and 101 (see FIG. 16).

  Next, as shown in FIG. 16, a photoresist 192 is formed on the gate oxide film 105. Then, an opening is formed in the photoresist 192 on the region where the P-type diffusion layer 193 is formed. P-type impurities such as boron (B) are ion-implanted from the EPI 68 surface. Thereafter, the photoresist 192 is removed and thermal diffusion is performed. In this thermal diffusion step, the P type diffusion layer 193 is thermally diffused to form a P type diffusion layer 79 (see FIG. 17).

  Finally, as shown in FIG. 17, after N-type diffusion layers 80, 102, 103 are formed, a P-type diffusion layer 99 is formed. Thereafter, for example, an NSG film and a BPSG film are deposited on the EPI 68 as the insulating layer 90. Then, contact holes 91 to 93 and 108 to 110 are formed in the insulating layer 90 by dry etching. The aluminum alloy film is selectively formed in the contact holes 91 to 93 and 108 to 110, and the emitter electrode 94, the base electrode 95, the collector electrode 96, the source electrode 111, the drain electrode 112, and the back gate electrode 113 are formed. .

  In the present embodiment, a description will be given of a case where two ion implantation steps are successively performed using the same resist mask from above LOCOSs 87 to 89, 106, and 107 when forming a diffusion layer constituting ISO. However, the present invention is not limited to this case. For example, using the same resist mask from above LOCOS 87-89, 106, 107, three or more ion implantation steps are performed continuously, and between L-ISO 69, 72, 75 and U-ISO 71, 74, 77. A plurality of P-type buried layers may be formed. In addition, various modifications can be made without departing from the scope of the present invention.

  Next, a semiconductor device according to a fifth embodiment of the present invention will be described with reference to FIGS. FIG. 18A is a cross-sectional view for describing the semiconductor device of this embodiment. FIG. 18B is a plan view for explaining the NPN transistor shown in FIG. FIG. 19A is a diagram for explaining the impurity concentration and the diffusion depth of the diffusion layer constituting the ISO of the present embodiment. FIG. 19B is a cross-sectional view for explaining the ISO of this embodiment.

  In the present embodiment, the shapes of ISOs 201 to 203 are mainly different from the shapes of ISOs 1 to 3 shown in FIG. The shapes of the NPN transistor 204 and the N-channel MOS transistor 205 formed on the islands partitioned by ISO 201 to 203 are substantially the same as the shapes of the NPN transistor 4 and the N-channel MOS transistor 5 shown in FIG. is there. Therefore, the description of FIG. 1 described above is referred to as appropriate, and the same reference numerals are given to the same components.

  As shown in FIG. 18A, a first N-type EPI 7 is formed on a P-type substrate 6. A second EPI 8 is formed on the EPI 7. The EPIs 7 and 8 are divided into a plurality of islands by ISOs 201, 202, and 203. An NPN transistor 204 is formed in one region of the island, and an N-channel MOS transistor 205 is formed in the other region.

  The ISO 201 includes a P-type buried layer 206 (hereinafter referred to as L-ISO 206), a P-type buried layer 207 (hereinafter referred to as M-ISO 207), and a P-type diffusion layer 208 (hereinafter referred to as U-). It is called ISO208). As indicated by a circle 209, L-ISO 206 and U-ISO 208 partially overlap each other. The M-ISO 207 further overlaps with the overlapping region indicated by the circle 209. The ISO 201 including the M-ISO 207 forms a PN junction region with the N type diffusion layer 23. Similar to the ISO 201 described above, the ISOs 202 and 203 include P-type buried layers 210 and 213 (hereinafter referred to as L-ISO 210 and 213) and P-type buried layers 211 and 214 (hereinafter referred to as M-). And P-type diffusion layers 212 and 215 (hereinafter referred to as U-ISO 212 and 215).

  As shown in FIG. 18B, the region surrounded by the solid lines 216 to 220 corresponds to the U-ISOs 208 and 212, and the region surrounded by the dotted lines 221 and 222 corresponds to the N-type diffusion layers 23 and 24. The region surrounded by the alternate long and short dash line 223 corresponds to the P type diffusion layer 19, and the region surrounded by the solid line 224 corresponds to the N type diffusion layer 20. As shown in the figure, the N type diffusion layers 23 and 24 are arranged in a ring shape inside the ISOs 201 and 202 and form PN junction regions with the ISOs 201 and 202 including the M-ISOs 207 and 211.

  In the cross section of FIG. 18A, the U-ISOs 208 and 212 are illustrated as separate diffusion layers, but in actuality, they are formed as one annular diffusion layer. The same applies to the M-ISOs 207 and 211, the L-ISOs 206 and 210, the N-type buried layers 21 and 22, and the N-type diffusion layers 23 and 24.

  In FIG. 19A, the vertical axis represents the impurity concentration of L-ISO 206, M-ISO 207, and U-ISO 208, and the horizontal axis represents the diffusion depth thereof. A solid line indicates the entire ISO 201, a dotted line indicates the U-ISO 208, a one-dot chain line indicates the M-ISO 207, and a two-dot chain line indicates the L-ISO 206.

As indicated by the dotted line, the U-ISO 208 is formed so that the peak of the impurity concentration is located in a region of about 0.3 μm from the surface of the EPI 8. Further, as indicated by the alternate long and short dash line, the M-ISO 207 is formed so that the impurity concentration peak is located in a region of about 0.5 μm from the surface of the EPI 8. Further, as indicated by the two-dot chain line, the L-ISO 206 is formed so that the peak of the impurity concentration is located in a region of about 1.75 μm from the surface of the EPI 8. As indicated by the solid line, the ISO 201 has a region where the M-ISO 207 and the U-ISO 208 are superposed so that the concentration changes from 0.3 to 0.5 μm in the range of 0.3 to 0.5 μm from the EPI 8 surface. U-ISO 208 and L-ISO 206 overlap with each other in a region of about 1.0 μm from the surface of EPI 8, and the impurity concentration of 1.0 × 10 ¹⁷ / cm ² or more is maintained in this overlapping region.

  With this structure, a depletion layer extending from the PN junction region between the P-type ISO 201 and the P-type substrate 6 and the N-type EPIs 7 and 8 and the N-type buried layer 18 crosses the ISO 201 and other adjacent It can be prevented from spreading to the island. And the leak current between adjacent elements is prevented.

  In FIG. 19B, d1 indicates the depth of the peak position of the impurity concentration of U-ISO 208, d2 indicates the depth of the peak position of the impurity concentration of M-ISO 207, and d3 indicates the total film thickness of EPIs 7 and 8. , D4 represents the depth to the overlapping region of U-ISO 208 and L-ISO 206, and d5 represents the depth of the peak position of the impurity concentration of L-ISO 206. As described above with reference to FIG. 19A, d1 = about 0.3 μm, d2 = about 0.5 μm, d3 = about 0.8 μm, d4 = about 1.0 μm, d5 = 1.75 μm, respectively. Degree.

  As shown in the figure, the peak of the impurity concentration of U-ISO 208 and M-ISO 207 is located on the EPI 8 surface side from the central region d3 of EPI 7 and 8. As a result, in the ISO 201, the M-ISO 207 and U-ISO 208 regions have a higher impurity concentration than the L-ISO 206 region, and the lateral diffusion is easily spread. And since the impurity concentration of EPI8 is lower than the impurity concentration of L-ISO206, the shape of ISO201 becomes a shape where M-ISO207 and U-ISO208 flattened in the horizontal direction are arranged on L-ISO206. Then, U-ISO 208 and M-ISO 207 overlap each other, and ISO 201 and N-type diffusion layer 23 form a PN junction region in a region of about 0.3 to 0.5 μm from the surface of EPI 8. In the region where the P-type impurity has a high concentration, lateral diffusion is also likely to spread, but the N-type diffusion layer 23 suppresses the spread of the diffusion width W13 of the M-ISO 207. The device size of the NPN transistor 204 is reduced by suppressing the lateral diffusion width of the ISO 201. As shown in FIGS. 18A and 18B, the N-type diffusion layers 21 to 24 are arranged in a ring shape inside the ISOs 201 and 202, so that the diffusion spread of the ISOs 201 and 202 can be made all around. Can be suppressed.

  Further, the M-ISO 207 further overlaps with the overlapping area indicated by the circle 209. With this structure, the three diffusion layers 206 to 208 are designed so that the impurity concentration of the overlapping region indicated by a circle 209 is equal to or higher than a desired concentration. For this reason, the amount of climbing of the L-ISO 206 and the amount of climbing of the U-ISO 208 can be reduced. The device size of the NPN transistor 204 is reduced by narrowing the diffusion width W13 of the M-ISO 207 and the diffusion width W14 of the L-ISO 206 and suppressing the lateral diffusion of the ISO 201.

  Also in this embodiment, the separation distance L5 between the P-type diffusion layer 19 and the M-ISO 207 and the separation distance L6 between the P-type diffusion layer 19 and the L-ISO 206 shown in FIG. Can do. With this structure, the breakdown voltage characteristic of the NPN transistor 204 is maintained and the device size of the NPN transistor 204 is reduced, as in the embodiment described with reference to FIG.

  In addition, the structure in which two layers of EPIs 7 and 8 are stacked on the substrate 6 and the ISOs 201 to 203 are formed on the EPIs 7 and 8 has been described. However, the present invention is not limited to this case. For example, three or more layers of EPI may be stacked on the substrate, and the ISO having the above structure may be formed on the plurality of layers of EPI. Even in this case, the impurity concentration can be adjusted while suppressing the lateral diffusion of ISO.

  Moreover, although the structure in which the film thickness of the first EPI 7 is thinner than the film thickness of the second EPI 8 has been described, the present invention is not limited to this case. For example, the first and second EPIs 7 and 8 may have the same thickness, or the first EPI 7 may be thicker than the second EPI 8. That is, the same effect can be obtained by forming the ISO having the above structure with respect to the total film thickness of the EPI laminated on the substrate. At this time, the overlapping region of the U-ISO 208 and the L-ISO 206 (the region surrounded by the circle 209) may be formed in the EPI 7 in the first layer.

  In addition, the structure in which the N type buried layers 21 and 22 and the N type diffusion layers 23 and 24 as the collector region of the NPN transistor 204 are arranged around the P type diffusion layer 19 has been described. It is not limited. For example, in a structure in which a diode is arranged in an island region, for example, an N-type diffusion layer as a cathode region (an N-type buried layer is included in a structure in which an N-type buried layer is formed) is an anode. The same effect as described above can also be obtained in the structure disposed around the P-type diffusion layer as the region. In addition, various modifications can be made without departing from the scope of the present invention.

  Next, a method for manufacturing a semiconductor device according to a sixth embodiment of the present invention will be described with reference to FIGS. As described above, the shapes of the NPN transistor 204 and the N-channel MOS transistor 205 are substantially the same as the shapes of the NPN transistor 4 and the N-channel MOS transistor 5 shown in FIG. Therefore, the description of FIG. 3 and FIGS. 5 to 9 described above is referred to as appropriate, and the same reference numerals are given to the same components.

  First, as shown in FIG. 3, a P-type substrate 6 is prepared, and N-type buried layers 122 and 123 are formed on the substrate 6. For details of the manufacturing method, refer to the description of FIG.

  Next, as shown in FIG. 20, the first N-type EPI 7 is formed on the substrate 6. At this time, the N-type buried layers 122 and 123 (see FIG. 3) are thermally diffused by the heat treatment in the EPI 7 formation process, and the N-type buried layers 18 and 35 are formed.

Next, a silicon oxide film 231 is formed on the EPI 7 and N-type diffusion layers 232 and 233 are formed. Thereafter, a photoresist 234 is formed on the silicon oxide film 231, and an opening is formed in the photoresist 234 on the region where the P type buried layers 235 to 237 are to be formed. Thereafter, a P-type impurity such as boron (B +) is ion-implanted from the surface of the EPI 7 with an acceleration voltage of 80 keV and an introduction amount of 3.0 × 10 ¹³ / cm ² . Then, the photoresist 234 and the silicon oxide film 231 are removed.

  At this time, the thickness t1 of the photoresist 234 is, for example, 1.8 μm, and the line widths W15 to W17 on the formation region of the P type buried layers 235 to 237 are, for example, 1.2 μm. This is because the following problems occur when the thickness of the photoresist is increased and the opening for ion implantation is formed. When opening the photoresist, if the thickness of the photoresist is thick, the etching time becomes long, and the side surface of the photoresist in the opening is likely to droop. That is, the etching time becomes longer as the photoresist is closer to the upper end portion, and the opening area becomes larger as it is closer to the upper end portion of the opening portion. As a result, the film thickness of the dripping region of the photoresist is thinner than the film thickness of the other regions. When impurities are ion-implanted with an acceleration voltage matched to a thick portion of the photoresist, the impurities pass through the photoresist in a region where the photoresist is dripped. Then, impurities are implanted into a region wider than the designed line width and are thermally diffused, which makes fine processing difficult.

  Therefore, as described above, by reducing the film thickness t1 of the photoresist 234, the etching time of the photoresist 234 is shortened, and dripping of the opening is prevented. Then, the fine processing of the wiring widths W15 to W17 of the photoresist 234 becomes possible. Further, the acceleration voltage at the time of ion implantation is lowered in response to the reduction in the film thickness t1 of the photoresist 234. As a result, the peak of the impurity concentration of the P-type buried layers 235 to 237 is close to the EPI 7 surface side, and the P-type buried layers 235 to 237 are likely to rise to the EPI 8. Further, since the heat treatment time for diffusing the P type buried layers 235 to 237 can be shortened, the lateral diffusion width of the P type buried layers 235 to 237 can also be reduced.

  Next, as shown in FIGS. 5 to 6, a second N-type EPI 8 is formed on the EPI 7. After the N-type diffusion layers 23 and 24 are formed on the EPI 8, LOCOS 25 to 27, 44, and 45 are formed. Also in this embodiment, a dedicated thermal diffusion process for thermally diffusing the P type buried layers 235 to 237 (see FIG. 20) is not performed. At this time, the N-type buried layers 232 and 233 (see FIG. 20) are thermally diffused by the heat treatment in the EPI 8 formation process, and the N-type buried layers 21 and 22 are formed. Similarly, the P type buried layers 235 to 237 are thermally diffused to form L-ISOs 206, 210, and 213 (see FIG. 21). For the detailed manufacturing method, refer to the description of FIGS.

Next, as shown in FIG. 21, a silicon oxide film 238 is formed on the upper surface of the EPI 8, and a photoresist 239 is formed on the silicon oxide film 238. Then, an opening is formed in the photoresist 239 on the region where the P type buried layers 240 to 243 are to be formed. Thereafter, a P-type impurity such as boron (B ++) is ion-implanted from the surface of the EPI 8 at an acceleration voltage of 300 keV and an introduction amount of 2.5 × 10 ¹³ / cm ² .

  At this time, the thickness t2 of the photoresist 239 is, for example, 1.8 μm, and the line widths W18 to W20 on the formation region of the P-type buried layers 240 to 243 are, for example, 1.2 μm. As described above, the fine processing of the line widths W18 to W20 can be performed by reducing the thickness t2 of the photoresist 239. Then, by reducing the acceleration voltage at the time of impurity ion implantation, the peak of the impurity concentration of the P-type buried layers 240, 241, and 243 becomes closer to the EPI8 surface side.

Next, a second ion implantation is performed using the same photoresist 239 without thermally diffusing the P type buried layers 240 to 243. P-type impurities such as boron (B +) are ion-implanted from above the photoresist 239 at an acceleration voltage of 190 keV and an introduction amount of 8.0 × 10 ¹² / cm ² . P-type diffusion layers 244 to 247 are formed by the second ion implantation process. Thereafter, the photoresist 239 is removed and thermally diffused to form the M-ISO 207, 211, 214 (see FIG. 22), the P-type diffusion layer 36, and the U-ISO 208, 212, 215 (see FIG. 22). The silicon oxide film 238 is removed.

  That is, after the first ion implantation step, the thermal diffusion step is performed after the second ion implantation step is continuously performed without performing the thermal diffusion step. With this manufacturing method, the M-ISOs 207, 211, and 214, the P-type diffusion layer 36, and the U-ISOs 208, 212, and 215 are formed by a single thermal diffusion process.

  Then, the peak of the impurity concentration of the U-ISOs 208, 212, and 215 becomes closer to the EPI8 surface side by lowering the acceleration voltage when ion-implanting the impurities corresponding to the thickness t2 of the photoresist 239. With this manufacturing method, boron (B ++, B +) having a relatively large molecular level is ion-implanted, but the area where EPI 8 is damaged by boron is reduced. After all the ion implantation steps are completed, annealing is performed in a nitrogen atmosphere in order to recover the damage.

  Next, as shown in FIGS. 7 to 9, a gate oxide film 43 and a gate electrode 42 are formed on the EPI 8. Thereafter, N type diffusion layers 38 to 41 and P type diffusion layers 19 and 37 are formed. For details of the manufacturing method, refer to the description of FIGS.

  Finally, as shown in FIG. 22, for example, an NSG film and a BPSG film are deposited on the EPI 8 as the insulating layer 28. Then, contact holes 29 to 31 and 46 to 48 are formed in the insulating layer 28 by dry etching. Similar to the first embodiment, aluminum alloy films are selectively formed in the contact holes 29 to 31 and 46 to 48, and the emitter electrode 32, the base electrode 33, the collector electrode 34, the source electrode 49, and the drain electrode 50 are formed. Then, the back gate electrode 51 is formed.

In this embodiment, the case where the M-ISO 207, 211, 214 and the U-ISO 208, 212, 215 are formed from the surface of the EPI 8 when forming the ISO has been described. However, the present invention is not limited to this case. . Further, the photoresist 239 may be used as the same mask, and for example, boron (B +) may be ion-implanted with an acceleration voltage of 40 keV and an introduction amount of 4.0 × 10 ¹² / cm ² . In this case, the impurity concentration in the formation region of the U-ISOs 208, 212, and 215 is further increased. In addition, various modifications can be made without departing from the scope of the present invention.

  Next, a semiconductor device according to a seventh embodiment of the present invention will be described with reference to FIGS. FIG. 23A is a cross-sectional view for describing the semiconductor device of this embodiment. FIG. 23B is a plan view for explaining the NPN transistor shown in FIG. FIG. 24A is a cross-sectional view for explaining the ISO of this embodiment. FIG. 24B is a diagram for explaining the ISO indicated by the concentration distribution.

  In the present embodiment, the shapes of ISOs 251 to 253 are mainly different from the shapes of ISOs 61 to 63 shown in FIG. The shapes of the NPN transistor 254 and the N-channel MOS transistor 255 formed on the island partitioned by the ISO are substantially the same as the shapes of the NPN transistor 64 and the N-channel MOS transistor 65 shown in FIG. . Therefore, the description of FIG. 2 described above is referred to as appropriate, and the same reference numerals are given to the same components.

  As shown in FIG. 23A, a first EPI 67 is formed on the substrate 66. A second EPI 68 is formed on the EPI 67. The EPIs 67 and 68 are divided into a plurality of islands according to ISO 251-253. An NPN transistor 254 is formed in one region of the island, and an N-channel MOS transistor 255 is formed in the other region.

  The ISO 251 includes a P-type buried layer 256 (hereinafter referred to as L-ISO 256), a P-type buried layer 257 (hereinafter referred to as M-ISO 257), and a P-type diffusion layer 258 (hereinafter referred to as U-). ISO 258). As indicated by a circle 259, L-ISO 256 and U-ISO 258 partially overlap each other. The M-ISO 257 further overlaps with the overlapping region indicated by the circle 259. The ISO 251 including the M-ISO 257 forms N-type diffusion layers 81 and 83 and a PN junction region. Similar to the ISO 251 described above, the ISOs 252 and 253 are P-type buried layers 260 and 263 (hereinafter referred to as L-ISO 260 and 263) and P-type buried layers 261 and 264 (hereinafter referred to as M-). And P-type diffusion layers 262 and 265 (hereinafter referred to as U-ISO 262 and 265).

  As shown in FIG. 23B, the region surrounded by solid lines 266 to 270 corresponds to U-ISO 258 and 262, and the region surrounded by dotted lines 271 and 272 corresponds to N type diffusion layers 81 to 86, A region surrounded by an alternate long and short dash line 273 corresponds to the P type diffusion layer 79, and a region surrounded by the solid line 274 corresponds to the N type diffusion layer 80. As shown in the figure, the N type diffusion layers 81 to 86 are arranged in a ring shape inside the ISOs 251 and 252 and form PN junction regions with the ISOs 251 and 252 including the M-ISOs 257 and 261.

  In FIG. 24A, d6 indicates the depth of the peak position of the impurity concentration of U-ISO258, d7 indicates the depth of the peak position of the impurity concentration of M-ISO257, and d8 indicates the total film thickness of EPI67 and 68. D9 indicates the depth to the overlapping region of U-ISO258 and L-ISO256, and d10 indicates the depth of the peak position of the impurity concentration of L-ISO256. Note that d6 = about 0.3 μm, d7 = about 0.5 μm, d8 = about 0.8 μm, d9 = about 1.0 μm, and d10 = 1.75 μm.

  As illustrated, the shape of ISO 251 is substantially the same as the shape of ISO 201 shown in FIG. Therefore, the impurity concentration and the diffusion depth of ISO 251 are as shown in FIG. 19A, and the description of FIGS. 19A and 19B is referred to as appropriate.

  The peak of the impurity concentration of U-ISO 258 and M-ISO 257 is located on the EPI 68 surface side with respect to the central region d8 of EPI 67 and 68. U-ISO 258 and M-ISO 257 overlap each other, and ISO 251 and N-type diffusion layers 81 and 83 form a PN junction region in a region of about 0.3 to 0.5 μm from the surface of EPI 68. In the region where the P-type impurity has a high concentration, lateral diffusion is also likely to spread, but the N-type diffusion layers 81 and 83 suppress the spread of the diffusion width W21 of the M-ISO 257. The device size of the NPN transistor 254 is reduced by suppressing the lateral diffusion width of the ISO 251. As shown in FIGS. 23A and 23B, the N-type diffusion layers 81 to 86 are arranged in a ring shape inside the ISOs 251 and 252 so that the diffusion width of the ISOs 251 and 252 is widened. Suppressed all around.

  Further, the M-ISO 257 further overlaps with the overlapping region indicated by the circle 259. With this structure, the three diffusion layers 256 to 258 are designed so that the impurity concentration of the overlapping region indicated by a circle 259 is equal to or higher than a desired concentration. For this reason, the amount of climbing of the L-ISO 256 and the amount of climbing of the U-ISO 258 can be reduced. The device size of the NPN transistor 254 is reduced by narrowing the diffusion width W21 of the M-ISO 257 and the diffusion width W22 of the L-ISO 256 and suppressing the lateral diffusion of the ISO 251.

  As shown in FIG. 24B, a thick line 275 indicates the outer shape of ISO251. An area where the color is displayed darker is a higher density area. Although not shown, the ISO 201 shown in FIG. 19B has a similar outer shape.

  The side where the ISO 251 forms the N-type diffusion layers 81 and 83 and the PN junction region (the right side of the drawing) will be described. In the region from the depth d7 to the depth d9, the three diffusion layers 256 to 258 are overlapped, and the lateral diffusion easily spreads. However, the spread of lateral diffusion in the overlapping region is suppressed by the N-type diffusion layers 81 and 83. On the other hand, in the region deeper than the depth d9, it changes in a gently curved surface in accordance with the impurity concentration of L-ISO256, and the diffusion width becomes wider than the region where the PN junction region is formed. As described above, the spread of the lateral diffusion of L-ISO 256 can be suppressed by shortening the heat treatment time.

  Also in this embodiment, the separation distance L7 between the P-type diffusion layer 79 and the M-ISO 257 and the separation distance L8 between the P-type diffusion layer 79 and the L-ISO 256 shown in FIG. Can do. With this structure, the breakdown voltage characteristic of the NPN transistor 254 is maintained and the device size of the NPN transistor 254 is reduced, as in the embodiment described with reference to FIG.

  Further, the structure in which the two EPIs 67 and 68 are stacked on the substrate 66 and the ISOs 251 to 253 are formed on the EPIs 67 and 68 has been described. However, the present invention is not limited to this case. For example, three or more layers of EPI may be stacked on the substrate, and the ISO having the above structure may be formed on the plurality of layers of EPI. Even in this case, the impurity concentration can be adjusted while suppressing the lateral diffusion of ISO.

  Further, although the structure in which the film thickness of the first EPI 67 is thinner than the film thickness of the second EPI 68 has been described, the present invention is not limited to this case. For example, the first and second EPIs 67 and 68 may have the same thickness, or the first EPI 67 may be thicker than the second EPI 68. That is, the same effect can be obtained by forming the ISO having the above structure with respect to the total film thickness of the EPI laminated on the substrate. At this time, the overlapping region of U-ISO 258 and L-ISO 256 (region surrounded by a circle 259) may be formed in the first EPI 67.

  Further, although the structure in which the N type diffusion layers 81 to 86 as the collector region of the NPN transistor 254 are arranged around the P type diffusion layer 79 has been described, the present invention is not limited to this case. For example, in the structure in which the diode is arranged in the island region, for example, the same effect as described above is also obtained in the structure in which the N-type diffusion layer as the cathode region is arranged around the P-type diffusion layer as the anode region. Can be obtained. In addition, various modifications can be made without departing from the scope of the present invention.

  Lastly, the description of the method for manufacturing the semiconductor device shown in FIG. 23A will be omitted with reference to FIGS. 3 to 17 and FIGS. 20 to 22 described above. As described above, the shapes of ISOs 251 to 253 are substantially the same as the shapes of ISO 201 to 203 shown in FIG. 18A, and the manufacturing method thereof is also the same. The shapes of the NPN transistor 254 and the N-channel MOS transistor 255 are substantially the same as the shapes of the NPN transistor 64 and the N-channel MOS transistor 65 shown in FIG. 2, and the manufacturing method thereof is also the same.

It is sectional drawing explaining the semiconductor device in embodiment of this invention. It is sectional drawing explaining the semiconductor device in embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device in embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device in embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device in embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device in embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device in embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device in embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device in embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device in embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device in embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device in embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device in embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device in embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device in embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device in embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device in embodiment of this invention. 1A is a cross-sectional view and FIG. 2B is a plan view illustrating a semiconductor device according to an embodiment of the present invention. (A) The figure for demonstrating the impurity concentration and diffusion depth of an isolation region in embodiment of this invention, (B) It is sectional drawing explaining an isolation region. It is sectional drawing explaining the manufacturing method of the semiconductor device in embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device in embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device in embodiment of this invention. 1A is a cross-sectional view and FIG. 2B is a plan view illustrating a semiconductor device according to an embodiment of the present invention. (A) Sectional drawing explaining the isolation | separation area | region in embodiment of this invention, (B) It is a figure explaining the isolation | separation area shown by concentration distribution. It is sectional drawing explaining the semiconductor device in conventional embodiment. It is sectional drawing explaining the semiconductor device in conventional embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Separation region 2 Separation region 3 Separation region 4 NPN transistor 5 N channel type MOS transistor 6 P type single crystal silicon substrate 7 N type epitaxial layer 8 N type epitaxial layer 9 P type buried diffusion layer 10 P type Embedded diffusion layer 11 P-type diffusion layer 21 N-type diffusion layer 23 N-type diffusion layer

Claims (15)

A semiconductor substrate of one conductivity type;
A first epitaxial layer of a reverse conductivity type formed on the semiconductor substrate;
A second epitaxial layer of reverse conductivity type formed on the first epitaxial layer;
An isolation region of one conductivity type that divides the first and second epitaxial layers into a plurality of islands;
The isolation region is formed in the first epitaxial diffusion layer of one conductivity type formed across the semiconductor substrate, the first epitaxial layer, and the second epitaxial layer, and the second epitaxial layer. 2. A semiconductor device comprising: a first conductivity type second buried diffusion layer and a first conductivity type first diffusion layer formed in the second epitaxial layer connected to each other. A bipolar transistor is formed in one region of the island,
A reverse conductivity type buried diffusion layer formed across the first and second epitaxial layers between the one conductivity type second diffusion layer used as a base region of the bipolar transistor and the isolation region. 2. The semiconductor device according to claim 1, wherein the semiconductor device is formed by connecting a diffusion layer of a reverse conductivity type formed in the second epitaxial layer.
The reverse conductivity type buried diffusion layer and the reverse conductivity type diffusion layer are disposed so as to surround the one conductivity type second diffusion layer, and the collector electrode of the bipolar transistor is the reverse conductivity type diffusion layer. The semiconductor device according to claim 2, wherein:
The one conductivity type first buried diffusion layer and the one conductivity type first diffusion layer are partially overlapped by the second epitaxial layer,
The peak of the impurity concentration of the first conductivity type first buried diffusion layer is located closer to the substrate than the center of the total film thickness of the first and second epitaxial layers, and the one conductivity type The impurity concentration peak of the second buried diffusion layer and the impurity concentration peak of the first conductivity type first diffusion layer are located on the surface side of the second epitaxial layer from the center. The semiconductor device according to claim 1. The one conductivity type second buried diffusion layer has a peak of impurity concentration on the surface side of the second epitaxial layer with respect to the overlapping region, and the one conductivity type second buried diffusion layer. 5. The layer according to claim 4, wherein the layer is formed so as to overlap the first buried diffusion layer of one conductivity type and the first diffusion layer of one conductivity type so as to include the overlapping region. The semiconductor device described. A bipolar transistor is formed in one region of the island, and a reverse conductivity type diffusion layer is formed between the one conductivity type second diffusion layer as the base region of the bipolar transistor and the isolation region,
6. The semiconductor device according to claim 4, wherein the one conductivity type second buried diffusion layer forms a junction region with the opposite conductivity type diffusion layer. The reverse conductivity type diffusion layer is disposed so as to surround the one conductivity type second diffusion layer, and the junction region is formed across a region where the reverse conductivity type diffusion layer is formed. The semiconductor device according to claim 6. A semiconductor substrate of one conductivity type;
A first epitaxial layer of a reverse conductivity type formed on the semiconductor substrate;
A second epitaxial layer of reverse conductivity type formed on the first epitaxial layer;
An isolation region of one conductivity type that divides the first and second epitaxial layers into a plurality of islands;
The isolation region is formed in the first epitaxial diffusion layer of one conductivity type formed across the semiconductor substrate, the first epitaxial layer, and the second epitaxial layer, and the second epitaxial layer. A first conductivity type second buried diffusion layer and a first conductivity type first diffusion layer formed in the second epitaxial layer are connected to each other;
A bipolar transistor is formed in one region of the island, and a reverse conductivity type diffusion layer is formed between the one conductivity type second diffusion layer used as a base region of the bipolar transistor and the isolation region. A semiconductor device. The reverse conductivity type diffusion layer is disposed so as to surround the one conductivity type second diffusion layer, and a collector electrode of the bipolar transistor is connected to the reverse conductivity type diffusion layer. 8. The semiconductor device according to 8. Preparing a semiconductor substrate of one conductivity type and forming a first epitaxial layer of reverse conductivity type on the semiconductor substrate;
Forming a second epitaxial layer of opposite conductivity type on the first epitaxial layer after ion-implanting an impurity for forming the first buried diffusion layer of one conductivity type into the first epitaxial layer; ,
Implanting an impurity for forming a second buried diffusion layer of one conductivity type from the surface of the second epitaxial layer, and subsequently implanting an impurity for forming a diffusion layer of one conductivity type and thermally diffusing. And a step of connecting the first buried diffusion layer of one conductivity type, the second buried diffusion layer of one conductivity type, and the diffusion layer of one conductivity type to form an isolation region. A method for manufacturing a semiconductor device. 11. The semiconductor device according to claim 10, wherein an impurity forming the second conductive diffusion layer of the one conductivity type and the diffusion layer of the one conductivity type is ion-implanted using the same resist mask. Method. After a LOCOS oxide film is formed on the second epitaxial layer, impurities for forming the one conductivity type second buried diffusion layer and the one conductivity type diffusion layer are ion-implanted from the LOCOS oxide film. 12. The method for manufacturing a semiconductor device according to claim 10, wherein: In the step of ion-implanting impurities forming the one conductivity type second buried diffusion layer and the one conductivity type diffusion layer, the one conductivity type second buried diffusion layer and the one conductivity type diffusion are formed. The impurity is ion-implanted so that the peak of the impurity concentration of the layer is located on the surface side of the second epitaxial layer from the center of the total film thickness of the first and second epitaxial layers. A method for manufacturing a semiconductor device according to claim 10. 14. The manufacturing method of a semiconductor device according to claim 13, wherein impurities forming the second buried diffusion layer of one conductivity type and the diffusion layer of one conductivity type are ion-implanted using the same resist mask. Method. A semiconductor layer; a one-conductivity-type isolation region that divides the semiconductor layer into a plurality of islands; and a reverse-conductivity type diffusion formed in the semiconductor layer and located on an inner periphery of the isolation region in the one region of the island And having a layer
The isolation region forms a junction region with the reverse conductivity type diffusion layer, and a diffusion width of the isolation region of the region forming the junction region is located in a deeper part of the semiconductor layer than the junction region A semiconductor device characterized by being narrower than the diffusion width of the region.