JPS59124153A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To improve withstanding voltage and to prevent yielding of parasitic elements, by forming an element separating layer, which reaches a p<+> layer from an n layer in a p<+>n-n<+>n constitution, providing the p<+> layer as a channel stopper, providing an n<+> layer for reducing collector resistance, and providing a bipolar element in the n layer. CONSTITUTION:On a p<+> type Si substrate 31, a p layer 32, an n<+> layer 33, and n layer 34 are sequentially laminated. Etching is performed, and grooves reaching the p<+> substrate 31 are formed and filled up with poly Si 35. Then, an n<+> layer 36 is selectively formed by ion implantation. Thereafter, p layers 37-39 and an n layer 40 are formed. Finally, the surface is coated by SiO2 42, and an Al electrode 41 is provided. Thus the device is completed. In thid constitution, channel prevention is performed by the substrate 31. The p<+> substrate and the n<+> layer 33 are separated by the p layer 32 in the vertical direction. Therefore, withstanding voltage is not deteriorated. Since the n<+> layer 33 is uniform, hFE of parasitic p-n-p caused by the layers 37-34-33-32 is 0.1 or less due to the high concentration of the n base 33, and no actual obstacle is yielded. A mask process can be also reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor integrated circuit device in which elements are isolated by an insulating film.

Conventional configurations and their problems Conventionally, in bipolar integrated circuits, the isolation between junctions is p
N-junction isolation technology was used. On the other hand, the so-called LOC
O3 (Local Qxidation of Si 1
There was also an oxide film separation method called 1con), but L
The OCOS method has the disadvantage that a crow's beak-shaped oxide film called a bird's beak spreads laterally, thereby narrowing the actual area of the active region. Therefore, insulating film separation methods that do not cause birthbeaks have recently been developed, and the area required for separation has been substantially reduced. This naturally results in the active regions becoming very close9.
The n-type inversion of the substrate surface immediately below the separation causes deterioration of inter-element breakdown voltage and generation of leakage current.

For this reason, it is common practice to selectively diffuse p-type impurities at a high concentration directly beneath the isolation oxide film to prevent n-type inversion. However, since this high concentration p-type diffusion layer is in close proximity to the n-type buried diffusion layer, new problems arise such as suppression deterioration due to contact between the high concentration regions, and as a result, It is necessary to maintain a certain distance between the active regions, which is disadvantageous in achieving high density, which is one of the original objectives. This will be explained in detail below.

FIG. 1 shows a standard conventional manufacturing process.

(Spring 1 is a p-type substrate, which has a specific resistance of ~Ω·m and a thickness of ~100 μm.

(Uniform 2 is an n-type high-concentration region, usually made of As (arsenic), and has a very low layer resistance of several Ω/ohm to several 10 ohm/ohm, and is used as a buried layer to compensate for the collector resistance of a backpolar transistor. Diffused for reduction.

(Q3 is a highly doped p-type layer and is a channel that prevents the formation of an n-type inversion layer during the isolation between elements mentioned above.

Selectively diffused to prevent outbreaks.

(Ill 4 deposits an n-type epitaxial growth layer on the substrate 1. The specific resistance is about 0.3 to 2 Ω-m, and the film thickness is about 1 to 3 μm.

(The reference numeral 5 is an insulating film made of, for example, a silicon oxide film, a combination of polycrystalline silicon and silicon oxide film, etc.), and is created as isolation between elements.

(F) 6 is a collector wall diffusion layer, which is an n-type high concentration layer, and is generated by diffusion in order to lower the collector resistance.

(G) P-type boron is diffused into the growth layer, resulting in NPN
The base of the transistor, the emitter and collector 8 of a horizontal pnp transistor are formed. The layer resistance of this impurity layer is 200 to 300 Ω/hole.

(H) 9 is an n-type impurity diffusion layer made of phosphorus or arsenic, and serves as an emitter of an npn) run sister.

(I) To perform Al wiring, NPN and pn
p The transistor is completed. Note that it is a 10iA7 metal film.

The above-mentioned problems with conventional transistors will be explained in detail.

(1) The region 2 that will become the buried layer is placed close to the insulating film 5, but if it is not close, the base 7-growth layer 4
PNP transistors are produced by combining 10 on one substrate, which acts as a parasitic PNP and causes problems such as latch-up. This is because if they are brought close together, the hFE of the parasitic pnp transistor becomes extremely small due to the region 2 in which the base of the parasitic pnp layer is highly doped n-type, and there is no concern about latch-up or the like.

On the other hand, since the insulating film 5 is narrow, the p-type layer 3 for preventing a channel provided under the insulating film 5 has to be made even narrower.
There is a risk of contact with area 2 and deterioration of withstand voltage. Furthermore, if the insulating film 5 is made wider, the element area becomes larger.

(Considering the precision of mask alignment, the distance between region 2 and p-type layer 3 should normally be 2 μm or more, otherwise it would be a problem in terms of pressure resistance. However, since these manufacturing processes are in the first half of the process, temperature treatment is required later. This tends to spread in the lateral direction, which results in further expansion of the device area, making it impossible to achieve high density.

In the example shown in FIG. 1, the region 2 is wider than the base 7, so it is possible to reduce the region 2 to just below the base 7, which alleviates the above problem to some extent. This is a serious problem for walled base structures.

FIG. 2 shows a conventional example in which a vertical PNP is mixed with an NPN. In (A), 11 is a p-type substrate with a specific resistance of several Ω-cyn.
, 12 is a heavily doped n-type buried layer, 13 is a channel prevention portion and is a p-type high-density layer, and 14 is a p-type heavily doped layer, which is formed by diffusion inside the buried layer 12. (B) 15 is an n-type epitaxial layer with a specific resistance of 0.5 to 2 Ω-m.

Reference numeral 16 denotes a collector all diffusion portion of the collector electrode lead-out portion of the npn transistor, into which a high concentration of n-type impurity is diffused. Reference numeral 17 is an insulating film of an isolation portion for elemental isolation. 18 is a layer connected to the high concentration p-type high concentration layer 14 by diffusion from above by ion implantation, etc., and serves as a layer resistance.1.
This layer is about 5 to 3 Ω/hole and serves as a collector for a vertical PNP. This is the base layer of the vertical PNP, and is formed by ion implantation with phosphorus or the like at a resistance of several hundred Ω/hole. Reference numerals 20, 21 and 22 denote p-type diffusion layers which serve as an npn base, a pnp emitter and a collector, respectively, and are formed by boron diffusion or the like and have a layer resistance of about 150 to 300 Ω/hole. Reference numerals 23 and 24 denote the emitter of the npn transistor and the base diffusion layer of the pnp transistor, which are formed by phosphorus or arsenic diffusion, respectively. The layer resistance is ~Ω/mouth and the thickness is. , about 2-0.4 μm. Reference numeral 25 denotes an electrode made of Al.

In this way, the npn and pnp are integrally formed, but here too, the problem caused by the proximity of the n-type buried layer 12 and the channel prevention layer 13 is the same as that shown in FIG. .

Now, considering that the process yield in the IC manufacturing process is determined by the number of masks in the process and how strict the mask alignment accuracy is, let's consider the conventional example shown in Figure 1. In the basic process, the first
It will look like a table.

Table 1 (margin below) As described above, in the conventional example, eight masks are required, and precision in mask alignment is required in the channel prevention diffusion process and the insulating film formation process.

Purpose of the Invention The present invention prevents breakdown voltage deterioration due to the proximity of the channel prevention diffusion part and the buried layer, which is a problem in realizing a high-density, high-performance bipolar device, and the generation of parasitic transistors caused by avoiding this. Moreover, it is an object of the present invention to provide a semiconductor integrated circuit device that can reduce the number of masks required for the process and minimize the mask alignment process that requires precision.

Structure of the Invention The present invention comprises a highly doped first layer of one conductivity type, a lightly doped second layer formed on this layer, and a highly doped second conductive layer formed on the second layer. a third ↓ layer of the type, a low concentration fourth layer of the other conductivity type formed on the third layer, and an inter-element isolation film reaching the first layer from the surface of the fourth layer. the first layer acts as a channel stopper between transistor elements, the third layer acts as a buried layer for reducing collector resistance,
The semiconductor integrated circuit device is characterized in that a predetermined bipolar element is formed in the fourth layer.

DESCRIPTION OF EMBODIMENTS An embodiment of the present invention will be described below with reference to FIG. 3 according to the drawings.

(A) 31 was a high concentration p-type substrate with a resistance of 0.2 Ω or less. The thickness is approximately 300 μm. 32 is a low concentration p-type layer epitaxially grown on the high concentration p-type substrate 31, and has a specific resistance of about 1 Ω-m and a film thickness of about 1 μm. For the formation, we adopted the reduced pressure epitaxial method that can be formed at low temperatures, but if we use the MBE method (molecular beam epitaxial method),
Furthermore, films with less odope can be grown at lower temperatures. 33
is an n-type diffusion layer formed entirely on the p-type layer 32 by ion implantation or the like, and has a thickness of about 0.5 μm.

The p-type layer 32 is formed by short-time annealing such as annealing while maintaining the p-type layer 32. 34 is a low concentration n-type layer 1. , o~
Epitaxial growth is performed over the entire surface to a thickness of about 1.5 μm. The specific resistance is around 0.5Ω, and the formation method uses a reduced pressure epitaxial method. Using the substrate formed in this way,
Perform selective device formation.

(B) Reference numeral 36 denotes an insulating film, which is formed by growing an oxide film or by burying an insulating film after a silicon opening, similar to the method described in the conventional example. Another advantage is that methods such as embedding polycrystalline silicon can be performed without changing the impurity concentration distribution of the silicon substrate. The depth of the insulating film 35 is 2.
The diameter is around 5 μm, and its tip reaches the high concentration p-type substrate 31.

(C) 3e is collector wall diffusion, in which n-type high concentration impurities are formed using ion implantation.

(D) 37 to 39 are p-type impurity diffusion layers formed using boron ion implantation, and are respectively an npn base and a p-type impurity diffusion layer.
Form a pnp emitter and collector.

(E) By ion implantation of n-type impurities, the layer resistance is several Ω.
/ By injecting aiming at the mouth, the emitter of npn 4
0 is formed.

(F) 41 is an electrode formed by vapor deposition of A7.

Note that 42 is an oxide film.

As is clear from the above, the substrate 31 plays the role of the channel prevention part necessary for isolation between elements, and the high concentration p-type substrate 31 and the high concentration n-type diffusion layer 33 are Since they are separated in the vertical direction by the p-type layer 32, there is no fear of breakdown voltage deterioration. Furthermore, since the highly concentrated diffusion layer 33 is ion-implanted into the entire surface of the silicon substrate, it is formed by the n-type collector part formed by the p-type base 37 and the diffusion layer 33, and the p-type part of the p-type layer 32. Since the base region of the parasitic PNP, that is, the diffusion layer 33, has a high concentration, hFE of the parasitic PNP is extremely small, 0.1 or less, and does not pose a practical problem.

As described above, according to this embodiment, the conventional problem when the channel prevention part, which is a highly doped p-type region, and the buried part, which is a highly doped n-type region, are adjacent to each other can be resolved vertically. This problem was solved by a structure that reduces the parasitic pnp effect and prevents breakdown voltage deterioration, making it possible to increase density. Further, problems arise in the number of masks required for manufacturing and in mask alignment. Regarding accuracy, as shown in Table 2,
Compared to the conventional example shown in Table 1, the number of masks can be reduced from 8 to 6. The difficult mask alignment process can be reduced from 3 to 1 process.

Margin below Table 2 FIG. 4 shows an embodiment in which a vertical PNP is integrated.

(A) 51 is a p-type high concentration substrate, and 62 is a p-type low concentration epitaxial layer. 53 is an n-type high concentration diffusion layer, 64
is a p-type high concentration diffusion layer selectively formed on the diffusion layer 53. Substrate 51. Epitaxial layer 52. Diffusion layer 53
is formed on the entire surface without mask alignment.

(B) 55 is an n-type epitaxial layer with a specific resistance of 0.5 to
1.5Ω-mi, and the film thickness is 1.0 to 2.0 μm.

Reference numeral 56 denotes an insulating film, which is formed by burying polycrystalline silicon or the like. Reference numeral 57 denotes a highly doped n-type layer serving as a collector all portion, which is formed to improve the resistance of the collector electrode. A p-type layer 58 serves as the collector of the pnp transistor, and is formed by ion implantation. Reference numeral 59 denotes an n-type layer, which is formed within the p-type layer 58 and serves as a pnp base. 6
0, 61, and 62 become the npn base and pnp emitter and collector contact portions, respectively, into which p-type boron is implanted. 63 and 64 become the emitter of the npn transistor and the base contact of the pnp transistor, respectively, into which arsenic or the like is ion-implanted. 65 is an Al wiring as an electrode. As shown in the embodiment shown in FIG. 4, a vertical pup formed integrally also has a structure that does not have the non-selectivity of the three layers p+, p, and h+, similar to the embodiment shown in FIG. Similarly, the process steps begin with a similar substrate.

In the example shown in FIG. 4, as in the first embodiment, the number of masks required in the mask alignment process is reduced by two, and the electrical characteristic effects are also the same as in the first embodiment.

FIG. 5 shows a third embodiment of the present invention. In FIG. 5, 7o is a highly doped p-type substrate with a low doped n-type substrate on top of it.
A high concentration n-type layer 72 and a low concentration n-type layer 73 are stacked on top of the mold layer 71, and these layers are formed non-selectively and uniformly over the entire silicon wafer. There is. This structure is a silicon substrate corresponding to the silicon substrate shown in FIG. 3 (spring) described earlier, and the steps shown in FIG. The difference from the example is that the low concentration layer 71 in FIG. 5 is of n-type.

In particular, the role of this layer 71 is to prevent the p-type substrate 70 and the n-type high concentration n-type layer 72 from coming into contact with each other, and to serve as a region where the depletion layer of the pn junction spreads to provide a breakdown voltage. There is essentially no difference whether it is p-type or n-type. Therefore, whether to make N71 an n-type or a p-type can be determined based on ease of epitaxial formation, etc.

Effects of the Invention The present invention has the following features. In other words, (1) By vertically separating the breakdown voltage deterioration that conventionally occurred due to the close proximity of the channel prevention layer and the buried layer, the breakdown voltage deterioration can be prevented without increasing the area, and the concentration can be reduced to the same level as before. This makes it possible to increase the height even further, improving device characteristics.

(2) Parasitic effects caused by not providing a high concentration n-type region over the entire lower part of the device, such as parasitic pnp hFE
significantly decreased.

(3) The number of masks in the process has been increased by 2 compared to the conventional method.
Reduced number of copies.

(→ We have significantly reduced the number of parts in the process where the precision of mask alignment is critical.

(Tsuji) Because a high-resistance board is used, it is possible to lower thermal resistance and facilitate heat dissipation.

The effects described above have made it possible to significantly improve the production process, resulting in great industrial benefits.

[Brief explanation of drawings]

Figure 1 (8 to σ) is a process diagram of integrating a conventional n'pn) transistor and a horizontal pnp) transistor;
Figures (P-) and (B) are cross-sectional views of a process in which a conventional npn transistor and a vertical pnp transistor are integrated; Figure 4) is a process flow diagram of integrating horizontal PNP and NPN) transistors, and ■) is a process cross-sectional diagram of integrating vertical PNP and NPN) transistors according to the second embodiment of the present invention. The figure is a cross-sectional view of the structure of a substrate according to the third embodiment of the present invention. 31.51.70 mark: high concentration n-type, diffusion layer, 34°55.73...low concentration N-type layer, 71/old...Low concentration n-type layer. Name of agent: Patent attorney Toshio Nakao Haga 1 person No. 1
Figure 1 Figure 1? Figure 2 Figure 3 Figure 3

Claims (1)

[Claims] A first layer of one conductivity type with a high concentration, a second layer of one conductivity type with a low concentration formed on this first layer, and a second layer of one conductivity type with a low concentration formed on this first layer; A third layer of the other conductivity type with a high concentration is formed, a fourth layer of the other conductivity type with a low concentration is formed on the third layer, and the first layer is formed from the surface of the fourth layer. What is claimed is: 1. A semiconductor integrated circuit device comprising: an inter-element isolation oxide film reaching the layer, and a predetermined bipolar element is formed in the fourth layer separated by the inter-element isolation film.