JPS6031107B2 - Semiconductor integrated circuit device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated circuit device including a reverse direction transistor, and more particularly to a bibolar integrated circuit of conventional structure and a reverse direction transistor or an integrated injection logic circuit (
ln is a great lnfction mountain gic, hereinafter abbreviated as PL.

) coexist on one semiconductor chip. Reverse direction transistors have come to be frequently used as multi-collector transistors for interfaces between PL and conventional circuits.

12L is a bipolar logic device which is a combination of an injector for injecting minority carriers and a switching transistor, and has the advantage of being highly densely integrated and providing a low power consumption control circuit.

Since this 12L also includes a reverse direction (operation) transistor, we will take as an example the case where the 12L and a conventionally structured integrated circuit (hereinafter simply referred to as IC) coexist on one semiconductor chip. explain. Conventionally, various circuit networks using 12L have been constructed, but in any of the circuit networks, input/output circuits are coupled, and other circuits (these circuits are configured as ICs).

) is required in combination with In that case, it is desirable that the entire device be constructed simultaneously on one semiconductor chip through an IC manufacturing process. Moreover, the logic component of the PL has a structure that reduces the power delay product and improves performance.
It is increasingly necessary for other circuit components to have a structure that has a low collector saturation voltage, excellent high frequency characteristics, and high breakdown voltage. The inventors of the present application have previously proposed a semiconductor integrated circuit device and its manufacturing method that can satisfy all of the above demands (Japanese Patent Application No. 7636/1983:
No.-6487, special face No. 49-135444: Japanese Unexamined Patent Publication No. 5
1-61786).

Its typical structure (enlarged cross-section of the main part) is as shown in Figure 1, in which an N as a representative IC is placed on one semiconductor substrate 1.
PN transistors 2 and 12L3 coexist. The structure, operation, and features will be briefly explained below. To simplify the explanation, the conductivity of the semiconductor of each component will be defined and the explanation will be made assuming that a P-type substrate is used as the substrate 1. However, when an N-type substrate is used, the conductivity of each component ( It goes without saying that all you have to do is replace P and N). In FIG. 1, 4 and 4' are N-type low-resistance buried layers, 5 is an N-type epitaxial growth layer, and 6, 6', and 6'' are formed to separate the regions constituting the IC and 12L. (or an insulator) separation layer.Place P at the desired position in each separated region.
Layers 7, 7', 7'' and N+ layers 8, 8', 8'', 8 are provided. 9 is an insulating film, and 10 to 16 are electrodes.

Here, a characteristic point different from the configuration of the conventional device is that the separated region constituting the PL is located above the N0 type low-resistance buried layer 4' (below the P layers 7' and 7''). A low resistance N-type region 17 is provided in a portion.

The NPN transistor 2 configured in a region surrounded by separation layers 6 and 6' has an emitter electrode 10, a base electrode 11,
12 is a collector electrode, and 4 is a normal bipolar NPN transistor which operates as a buried layer for lowering the collector resistance.

In the PL 3 configured in the area surrounded by the separation layers 6' and 6'', 13 applies an injection current with an injection electrode and injects holes from the P layer 7' to the P layer 7'' via the N layer 5 to generate a P layer. The potential of the layer 7'' is increased, thereby the N layer 5 (emitter electrode 16)-P layer 7
″(base electrode 15)-N ten layers 8″(collector electrode 14
) turns on the vertical reverse-acting NPN transistor.
It works like that. The low resistance N-type region 17 increases the hole injection efficiency from the P layer 7' in the PL,
Also, it was provided to improve the current amplification factor by increasing the impurity concentration of the emitter of the reverse operation NPN transistor (for details, see the above-mentioned Tokuiso Sho 49-7636y: Samurai Seki Sho 51-6487). , has greatly contributed to improving the performance of PL.

On the other hand, this low-resistance N-type region 17 maintains a breakdown voltage for an IC configured as a region insulated by a separation layer.
This is an unnecessary thing that obstructs the formation of a high-output operation circuit or the like. The present invention further improves the structure of the low-resistance N-type region and provides a new and simplified structure of a semiconductor integrated circuit device in which an IC and 12L as shown in FIG. 1 coexist on one semiconductor chip. This is what we provide. EMBODIMENT OF THE INVENTION The semiconductor integrated circuit device of the present invention will be explained in detail below using examples.
Embodiment 1 FIGS. 2a to 2f are diagrams illustrating the semiconductor integrated circuit device of the present invention in the order of the manufacturing process, and show the main process steps in order.

Note that f is a completed drawing and corresponds to FIG.
Further, in the figures, the same reference numerals as in FIG. 1 indicate the same or equivalent parts, and the explanation will be omitted. First stage process [see Figure 2a]: First, a P-type semiconductor substrate 1 with a thickness of 100 to 600 m is formed using a thermal forming method or CVD (Chemistry method).
A thin poppy dioxide layer, a bare silicon layer, a thin silicon layer,
An insulating mask having desired characteristics such as an aluminum oxide layer is deposited, and an N+ buried layer 4 is formed at a desired location on the surface of the semiconductor substrate by diffusion of an impurity of antimony or arsenic.
Form to a depth of ~10 meters.

Second stage process [see Figure 2b]: 12 on the above structure
Phosphorus, which is an N-type impurity with a higher diffusion rate than antimony or arsenic, is deposited on the portion where L is to be formed for a desired period of time through an insulating mask, and then buried and diffused at a temperature of about 900 to 1300 qo to increase the sheet resistance ps. 10 to 2,000 m/m and a diffusion depth of 1 to 1 m to form an N0 buried layer 42'.

Third stage process [see FIG. 2c]: After removing the insulating mask, an N-type epitaxial growth layer 5 of 0.1 to 100 m is formed to a thickness of 2 to 1 m. During this formation, impurities in the N+ buried layers 4, 42' diffuse into the epitaxially grown layer by about 0.5 to 2.0 m. Note that the buried layer 42'
is designated 4' in the following description and drawings. Fourth stage process [see Fig. 2 d]: An insulating film is deposited at a desired location of the N-type epitaxial growth layer 5 as a mask, and boron, which is a P-type impurity, is diffused at approximately 900 to 1300 qo. Form r-type separation layers 6, 6', 6''.

The separation layer is formed by etching a hole to a depth of about half the thickness of the N-type epitaxial layer 5 using the above-mentioned mask, and oxidizing it using an appropriate method to form an insulator. ○xi onboard ionof
It may also be performed using Silicon technology.

Next, apply 900~1300 to the desired location through an insulator mask.
00, the P-type impurity boron is diffused to form the P layer 7,
7' and 7'' are formed to a thickness of 0.6 to 4.0 m.

Fifth stage process [see Figure 2 e]: Using the insulating film 9 as a mask, N-type impurity diffusion is performed again to form N10 layers 8, 8', 8''.
, 8''' to a thickness of 0.3 to 3 m.

In the above fourth and fifth steps, the N+ buried layers 4, 4'(42') provided in advance are diffused (rising upward), and the portions forming the FL (separation layers 6', 6 ''), the diffusion rate of phosphorus is high, so the buried layer 4' is formed thicker than the buried layer 4, and the P layer 7
It comes into contact with the bottom surface of ',7''.

On the other hand, in the part where the IC is formed (the area surrounded by the separation layers 6 and 6'), the N buried layer 4 is formed only of antimony or arsenic, so the diffusion rate is slow and it hardly spreads, so the P layer 7 is A wide gap from the bottom is maintained. 6th
Step process [see Fig. 2 f]: Electrodes 10 to 1 are inserted through an insulating film 9 with a thickness of 0.5 to 10 m with holes drilled at desired locations.
6 etc. by evaporation of aluminum to 0.5~3. Form to a nominal thickness of m.

Note that connection electrodes such as the N0 buried layer and the P+ type isolation layer and wiring interconnecting the IC and the PL are omitted to avoid complication of the drawing. Through the steps described above, the IC and 12L with improved performance are formed coexisting on one semiconductor chip. Note that when this semiconductor integrated circuit device is completed, 1
In the part where 2L is formed, the N0 buried layer 4'(41',42'
) and the bottom surfaces of the P layers 7', 7'' are most desirable in terms of PL performance.
The selection of the type and concentration of impurities 1' and 42' is important, and is determined by taking into consideration the heat treatment process to be performed in the subsequent process (such as in the diffusion stage of the P ten layer), etc. The other embodiments will be explained in sequence below, but the flow of the manufacturing process is almost the same as the first embodiment above, except for the first and second steps mentioned above, and the different steps are shown in FIG. 2. Only parts will be explained.

In this case, it is assumed that 42' in b and c of the same figure represents a layer having a different type or concentration of impurities from 4. Example 2 IC on the surface of P-type semiconductor substrate 1 using an insulator mask
Diffusion impurities such as phosphorus, antimony, and arsenic are selectively deposited in the areas where the particles are formed.

Then, using an insulating mask again, the diffusion impurity is deposited for a predetermined time on a portion of the surface of the semiconductor substrate where 13L is to be formed, at a higher concentration than that of the IC portion. By forming the N+ buried layers 4 and 42' with different impurity concentrations in advance in this way, the rise of the N+ buried layer 4' in the 12L formation portion at the time of device completion can be reduced by I.
It can be made larger than the N+ buried layer 4 in the C forming portion. All the steps from the third stage onwards are the same as in the first embodiment.

Example 3 Embedded diffusion impurities such as antimony, arsenic, and phosphorus are deposited on the surface of the P-type semiconductor substrate 1 where an IC is to be formed using an insulating mask, and then stretched and diffused for a desired time. The concentration of the buried layer 4 is lowered.

Next, using the insulating mask again, a buried diffusion impurity having the same concentration as above is deposited and diffused in the portion on the surface of the P-type semiconductor substrate 1 where the FL is to be formed. In this way, N
+ The buried layers 4 and 42' can be formed with different impurity concentrations in advance, so that the rise in the subsequent steps can be differentiated. All the steps from the third stage onwards are the same as in the first embodiment.

Embodiment 4 FIG. 3 shows a cross section of a semiconductor integrated circuit device in which the IC shown in FIG. 1 and 12L coexist on one semiconductor chip, with a partial structure changed.

The structural difference is that the N0 layer 18 is provided at a desired location on or surrounding the N0 buried layer 4 or 4'. This is called an N+ collar, and has the effect of preventing the generation of parasitic transistors, reducing the emitter resistance of the vertical transistor, and preventing the current amplification factor 8 of 12L from decreasing. Furthermore, the NPN transistor in the IC has the effect of reducing the collector resistance. The current amplification factor 6 will be highest if this N+ collar is made at a depth that is in contact with the N+ buried layer, but if the epitaxial layer 5 is thick, making it deeper increases the width and takes up more area, so it is not practical and generally not suitable. It can be stopped at a certain depth.
A method of manufacturing a semiconductor integrated circuit device having this structure will be described below.

Any of the embodiments described above may be used up to the third stage process, and the P+ type separation layers 6, 6', 6'' of the fourth stage process may be used.
After formation, a deep N
+ layer 18 is provided. Thereafter, P-type impurity diffusion is performed in the same manner as in the previous embodiment to form P layers 7, 7', 7''.
All the steps from the fifth stage onwards are performed in the same manner as in the first embodiment, and the semiconductor integrated circuit device is completed. By the way, in each of the embodiments described above, when the semiconductor integrated circuit device is completed, N
It is necessary to adjust so that the buried layers 4, 4' and the P layers 7', 7'' are in contact with each other. There are three methods for this. The first method is to The sheet resistance of the buried diffusion layer provided in advance is controlled by changing the deposition time or temperature of the N-type impurity in the step process, and the rise amount of the N+ buried layer in the subsequent process is set to a desired value.

In the second method, the thickness of the epitaxially grown layer 5 in the third step is controlled so that the depth of the P layers 7', 7'' is just N0 when the formation of the PL is completed. (42')
Make sure that it is in contact with the rise of your armpits.

The third method is to change the diffusion (or oxidation) time during the formation of the P+ type (or insulator) isolation layer in the fourth step.

In this method, the temperature is kept constant at, for example, 1200 oo and the time is controlled, and since the finished depth of the separation layer is not much of an issue, there is an advantage that the amount of swelling can be varied over a wide range. By the manufacturing method explained above, it is possible to manufacture a semiconductor integrated circuit device in which IC and 12L coexist on one semiconductor chip, and when the device is completed, the N+ buried layer 4'(42') where 13L is formed can be made. It can be brought close to the bottom surfaces of the P layers 7', 7''.

As mentioned above, it is desirable for these two layers to be in close contact with each other, but impurity diffusion control is quite delicate, and the diffusion (upward rise) of the N buried layer becomes too large and the P layer In reality, there may be cases where the diffusion exceeds the bottom surface to some extent, or cases where the diffusion is so small that it does not come into contact with the bottom surface of the P layer, but the decline in the performance improvement effect of 12L is not so rapid, and the amount of rise described above due to process variations is likely to occur. A variation of only a certain degree can be put to practical use. Next, the effects of the present invention will be explained.

In the semiconductor integrated circuit devices of Examples 1 to 5, the N+ buried layer 4' in the 12L portion is close to the bottom surfaces of the P layers 7' and 7''. With this structure, the P layer 7'' serves as the base of the vertical transistor, The N+ buried layer 4' becomes the emitter of the vertical transistor. Therefore, the impurity concentration of the emitter 4' can be higher than or about the same as the impurity concentration of the base 7'' of the vertical transistor.For this reason, holes injected from the base 7'' to the emitter 4' Since the base current decreases, there is an effect of increasing hF8 of the vertical transistor. Next, for the same reason, the number of holes flowing from injector 7' to 4' decreases, and 7'→5→
7'', which increases the proportion of flowing holes, which has the effect of improving injection efficiency.

In addition, in Example 4, since there is the N10 layer 18, 7'→5
This also has the effect of preventing the generation of parasitic PNP transistors that tend to occur between →6' and the like, and of reducing the emitter resistance of vertical transistors. The present invention has the above-mentioned characteristics and effects, but this is not limited to the conduction type of the embodiment.
It is equally applicable to PNP structures. That is, if P and N, P+ and N+, and holes and electrons in this specification are replaced, the same holds true in that case as well. As described above, according to the present invention, most of the processes are no different from conventional manufacturing processes, and it is possible to easily produce ICs and PLs with excellent characteristics by combining widely used techniques. A multifunctional large-scale integrated circuit device can be obtained by making it possible to coexist a reverse direction transistor on a single semiconductor chip.

In addition, the increase in the number of manufacturing steps is small, the decrease in yield is hardly a problem, and the industrial benefits are extremely large.

[Brief explanation of drawings]

1 and 3 are enlarged cross-sectional views of main parts illustrating the structure of the semiconductor integrated circuit device of the present invention, and FIGS. 2 a to 2 f are flowcharts of the main manufacturing process of the semiconductor integrated circuit device of the present invention. FIG. 1... Semiconductor substrate, 2... IC (NP
N transistor), 3...12L, 4, 4'(42')
...N+ buried layer, 5...Epitaxial growth layer, 6, 6', 6"...P ten type (insulator) separation layer, 7, 7', 7". ...P layer, 8, 8', 8'',
8 River N+ layer, 9... Insulating film, 10 to 16...
・Electrode, 17...Low resistance N-type region, 18...N+ layer (
N+color). Sha "Figure" 3 figures ☆ 2 figures

Claims (1)

[Claims] 1 A second semiconductor substrate of a conductivity type opposite to that of the substrate is placed on a first conductivity type semiconductor substrate.
A conductive type semiconductor layer is provided, a first conductive type impurity-introduced region or an insulator region is provided that separates the second conductive type semiconductor layer into a plurality of island regions, and a first conductive type semiconductor layer is provided. The island region is provided with a reverse direction transistor or an integrated injection logic circuit, and the second island region is provided with a bipolar transistor. In a semiconductor integrated circuit device in which a buried layer of a second conductivity type is provided in a boundary region with a second conductivity type semiconductor layer, the buried layer provided in the first island region The second conductive type semiconductor layer has an impurity concentration distribution that decreases toward the inside of the second conductive type semiconductor layer, and extends deeper into the second conductive type semiconductor layer than the buried layer provided in the second island region. A semiconductor integrated circuit device, characterized in that the semiconductor integrated circuit device is provided in contact with a base region of a transistor provided in a first island region.