JPS5950108B2 - transistor - Google Patents

Description

[Detailed description of the invention] The present invention relates to the structure of a transistor.

Recently, an integrated circuit called I″L (hereinafter referred to as IC)
has become a hot topic.

The reason for this is that it can be made only with the already established bipolar technology, and due to the special characteristics of the chip structure, it can be made very small, therefore it can be made at low cost, and there is a wide degree of freedom in functional design. Because there is. However, upon closer examination, it is indeed possible to realize an IC called I″L using conventional manufacturing methods and conventional structures, but it is possible to achieve the desired characteristics while also being compact. However, it is extremely insufficient to achieve the goal of low cost.Therefore, optimal manufacturing methods, impurity distribution, and structure within the chip are required for this I″L as well.First, Before explaining the present invention, the prior art will be described. Fig. 1 shows a part of a circuit called I''L, in which a PNP transistor TR is a constant current source (or load), and an NPN transistor TR is a constant current source (or load). Transistor TR.

is an inverter. Note that 1 to 3 are terminals, and G is a ground terminal. FIG. 2 is a sectional view of a chip structure obtained by realizing the circuit of FIG. 1 by a conventionally known method, and this chip structure is realized as follows.

That is, a thin layer 12 of the same conductivity type is provided on an N'' type substrate 11 using an epitaxial method, and two P layers separated from each other are formed on the surface region of this thin layer 12 by a normal impurity diffusion method.
Type regions 13 and 14 are formed at the same time, and an N-type region 15 is provided in one P-type region 14 by a double diffusion method.

Then, the PNP transistor T uses the P type region 13 as an emitter, the thin layer 12 as a base, and the other P type region 14 as a collector.
The RI is composed of an N-type substrate 11 and an N-type thin layer 12.
is the emitter, the P-type region 14 is the base, and the N-type region 15 is
An NPN transistor TR2 is configured as a collector.
It is obvious that with such a configuration, the I″L chip can be realized in a very small size.

NPN transistor TR as an inverter. Since e also has an amplification effect, it is desirable that the current amplification factor is large. However, the NPN transistor T in Figure 2
Since R2 is formed by double diffusion from the surface of the thin plate, the area Be of the emitter-base junction 16 is necessarily larger than the area θSc of the base-collector junction 17. Therefore, if a large current amplification factor e is desired, a large current amplification factor hfe cannot be obtained, which is extremely undesirable. The object of the present invention is to solve these problems and provide a transistor which can obtain desired characteristics, particularly a desired large current amplification factor, and which can be made small and inexpensive.

In the present invention, a collector region formed by impurity diffusion is arranged near the surface of a semiconductor thin plate, and a base is also formed by impurity diffusion below the collector region, that is, in a deeper part of the thin plate than the collector region. In a transistor in which emitters are arranged across regions, the emitters corresponding to the central portion of the collector region are arranged so that the effective area of the emitter junction is sufficiently smaller than the collector junction area in order to increase the current amplification factor Hfe. The present invention provides a transistor characterized in that the impurity concentration of the region is lower than the impurity concentration of the surrounding emitter region.

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 3 shows an embodiment of a chip structure according to the invention which implements the circuit of FIG. 1, and this chip structure can be realized by a combination of conventional techniques.

For example, N-type impurities are diffused into a part of the surface of the N substrate 11 to form what is commonly called a buried layer 19, and then the entire surface of the substrate is covered with N-type impurities.
The mold thin layer 12 is formed by an epitaxial method. The rest is to form P-type regions 13 and 14 simultaneously by the usual method, that is, by the usual impurity diffusion method as described above, and then to form N into one P-type region 14 by the double diffusion method. A mold region 15 is formed. In this way, PNP transistor TR. , and NPN transistor TR, as described above. It is configured as follows. In Fig. 3, the emitter of PNP transistor TR and the emitter of NPN transistor TR2 are shown.
The base and collector of . The purpose is to make the impurity concentration in the emitter region non-uniform so that the device does not operate uniformly.

That is, the impurity concentration of the emitter region 18 directly below the center of the base-collector junction 17 of the NPN transistor TR2 is low, and the impurity concentration of the emitter region 18 of the peripheral portion thereof is low. The impurity concentration in the emitter region 19 is intended to be high, so if we do this, if we apply a forward voltage to the emitter region and the base region, electron injection will first occur from the emitter region 18 due to the difference in rising voltage. , almost never occurs from region 19. Originally, this I″L is characterized by low current operation, so a small injection current from around the center is sufficient. With the configuration shown in Figure 3, the injection starts. Since the corresponding collector area is much wider than the emitter area, all the injected carriers are collected at the collector, just like in a normal transistor, so large current amplification factors H and e can be obtained. It is clear that the present invention is not limited to this embodiment, and various applications and modifications can be considered.

For example, in FIG. 3 of this embodiment, the conductivity type as shown is described, but the present invention is not limited to this.
Of course, it is possible to make arbitrary changes according to design requirements. That is, the P and N types may be reversed, or the substrate may be of P type instead of N' type. Further, it is also effective in the present invention to provide an N' region 20 as shown in FIG. 3 to provide the same effect as the region 19. By using the transistor according to the present invention as described above, desired characteristics, particularly a large current amplification factor, can be obtained, and the transistor can be made smaller and less expensive.

[Brief explanation of drawings]

Figure 1 is a diagram showing one unit circuit of I''L, Figure 2 is a cross-sectional view of a chip structure that realizes the circuit in Figure 1 using a conventional structure,
FIG. 3 is a cross-sectional view of a chip structure according to the present invention. DESCRIPTION OF SYMBOLS 11...N''' substrate, 12...N-type thin layer, 14...P-type region, 15...N-type region, 16... ...Emitsuta base joint, 17.
...Base-collector junction, 18...Emitter region, 19...Rikomu layer, 20...
・N area.

Claims (1)

[Claims] 1. In a transistor in which a base region is formed within an emitter region, the emitter region is provided with at least two region portions having different impurity concentrations, and at least a portion of the base-collector junction is formed on the region portion with a low impurity concentration. A transistor characterized by being located.