JPS6133261B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention is based on IIL (Integrated Injection Logic)
Regarding the improvement of a semiconductor device that integrates a conventional bipolar transistor and a conventional bipolar transistor in the same process, the current amplification factor of one transistor (vertical transistor) of the IIL is increased, and the withstand voltage of a normal bipolar transistor is improved, and in addition, different withstand voltages are improved. The purpose of this is to obtain a bipolar transistor. IIL is attracting attention as a bipolar LSI,
It is often used integrated with a normal bipolar transistor. At that time, the digital section
In IIL, the analog section consists of conventional bipolar transistors. The integrated structure is then formed using a conventional standard process as shown in Figure 1. In Figure 1, 1 is the emitter of the npn transistor, 2 is the base, 3 is the collector, and 4 is the IIL
The emitter (injector) of the pnp transistor, 5 the base of the pnp transistor (the emitter of the npn transistor, which is a vertical transistor), and 6 the collector of the pnp transistor (the same npn
(base of the transistor), 7 and 8 become the collector of the same npn transistor. 10 is a p-type silicon substrate, 11 is a buried layer, 12 is an isolation diffusion region, 1
3 is a collector contact. The first problem when integrating an IIL with a normal bipolar transistor is that the current amplification factor of the IIL's npn transistor is small. This is because conventional bipolar transistors are manufactured using the same process, so the structure is such that breakdown voltage, etc., does not deteriorate. And such a configuration is often not an optimal structure for IIL. for example,
In order to increase the current amplification factor of IIL npn transistors, methods such as narrowing the base width and lowering the base impurity concentration are used. Although such a method improves the current amplification factor of the IIL npn transistor, at the same time the current amplification factor of the conventional bipolar transistor increases, which causes a problem in that the withstand voltage between the collector and emitter of the transistor decreases. Therefore, if the base region is configured so as not to degrade the withstand voltage between the emitter and collector, the current amplification factor of the IIL will decrease, which will pose a problem in operation. As described above, the breakdown voltage of a normal bipolar transistor and the improvement of the current amplification factor of an IIL are contradictory points in integration, and a configuration that solves this problem is needed. In view of the above-mentioned problems, the present invention provides a method for integrating high-voltage bipolar transistors, ordinary graft-based bipolar transistors, and IIL elements into a single unit. The present invention provides an integrated circuit structure and a method for manufacturing the same that can satisfy both the current amplification factor of a transistor and the current amplification factor of a vertical transistor of an IIL element. In other words, the present invention increases the base width in high-voltage transistors, increases the impurity concentration in the diffusion depth of only the active base region in ordinary graft-based bipolar transistors, and improves IIL.
The vertical transistor is characterized by a narrow active base region width and a low impurity concentration. Hereinafter, a detailed explanation will be given based on the embodiment shown in FIGS. 2A to 2E. (A) A p-type silicon single crystal substrate 21 is coated with As or
Selectively high concentration n-type buried layer 22 using Sb
After forming, an n-type single crystal layer 23 having a specific resistance of 0.5 to 2 Ωcm is grown. (B) N-type single crystal layer 2 using impurities such as boron
3, a p-type isolation layer 24 is formed so as to reach the p-type substrate 21, and n-type island regions 23a, 23b,
23c is formed. Next, a high concentration n ⁺ layer 25 is selectively formed so as to reach the n ⁺ buried layer 22 . This n ⁺ layer 25 is the collector all (n ⁺
Color). (C) Highly doped p ⁺ region 2 to form the bases of bipolar transistors Tr ₁ and Tr ₂ and the emitter and collector of the pnp transistor of IIL.
6, 27, and 28 (28a, 28b) are formed simultaneously. The p ⁺ regions 26 and 27 are the bases of the npn bipolar transistors Tr ₁ and Tr ₂ , and the p ⁺ region 28
a becomes the emitter of the IILpnp transistor, and p ⁺ region 28b becomes the collector. (D) In order to form shallow active base regions of low concentration transistors Tr ₂ and IIL, low concentration p regions 29 and 30 are formed using boron or the like to be shallower than high concentration p ⁺ regions 27 and 28; Figure 3 A and B are
The base and emitter portions of Tr ₁ and Tr ₂ are shown, and C represents the base and collector portion of the I ² L vertical npn transistor. At this time, the semiconductor device whose base is formed by the highly doped p ⁺ region 26 is referred to as a transistor Tr ₁ , and the semiconductor device whose base is formed by the highly doped p ⁺ region 27 and the p region 29 is a transistor.
Set as Tr ₂ . Here, p ⁺ region 27 is a transistor
In the graft base region of Tr ₁ , p region 29 is the active base region. P region 30 becomes the active base region of the vertical npn transistor of IIL. Next, bipolar npn transistors Tr ₁ , Tr ₂
The emitters 31 and 32 of the IILnpn transistor and the collector 33 of the IILnpn transistor are formed at the same time. Here, the emitter 32 has a high concentration of p ⁺ at the periphery of the bottom surface.
so that it touches region 27, that is, p ⁺ region 27
The collector 33 of the IIL is formed so that the peripheral part of the bottom surface is in contact with the p region 30 and
It is formed so as not to straddle the p ⁺ region 28. Here, the emitters 31, 32 and the collector 33 can use n-type phosphorus, arsenic, antimony, etc. as impurities, but especially when phosphorus is used,
The p-region 30 is pushed out, and as shown in FIG. 3C, due to the push-out effect, the width of the base at the periphery of the bottom surface of the IIL collector 33, that is, the portion a in FIG. 3C is narrowed, and the current amplification factor is improved. On the other hand, in the normal graft-based bipolar transistor Tr ₂ , as shown in FIG. 3B,
The emitter 32 is formed so as to span the p ⁺ region 27, and the peripheral part of the bottom surface is a high concentration and deep p ⁺ layer 2.
7, so the base width does not become narrower at the periphery. Therefore, the withstand voltage of the emitter 32 and collector 23 of the transistor Tr ₂ can be maintained to some extent. In addition, the transistor Tr ₁ has a base region having a deep base layer 26 with a high concentration as shown in FIG. 3A.
Since the current amplification factor is small,
The withstand voltage between the collector 23 and the emitter 31 can be made sufficiently large. For example, high concentrations of p ⁺
50 to 80 Ω/□ for regions 26, 27, and 28, diffusion depth 1.2 to 1.5 μm, and 200 Ω/ for p regions 29 and 30.
□, depth 0.8 to 1.0 μm, n ⁺ region 31, 32, 3
3 is formed at 10 to 15Ω/□ and 0.8μm in depth,
The relationship between breakdown voltage and current amplification factor is shown in the table below.

[Table] As described above, by combining a highly doped p ⁺ layer and a p layer, three types of transistors with different breakdown voltages and current amplification factors can be formed at the same time. Further, although phosphorus is highly effective as an impurity in the n ⁺ layer, other impurities such as arsenic, antimony, etc. can also be used to increase the effect. In that case, as shown in FIG. 3C', since the extrusion effect is small, the width of the base at the periphery of the IIL collector is approximately the same as that at the center. (E) As shown in Figure 2, the surface is coated with an insulator such as SiO ₂ 3
4, a contact window is opened, and wiring is formed using a metal such as Al. 3 each
5 is the emitter of transistor Tr ₁ , 36 is the base, 37 is the collector, 38 is the emitter of transistor Tr ₂ , and 39 is the transistor.
The base of Tr ₂ , 40, is the same collector, and 41
is the collector of the IIL vertical npn transistor, 4
2 is the base of the IIL vertical npn transistor, 4
3 is the emitter of the IIL vertical npn transistor,
44 is an IIL injector. The integrated structure according to the present invention has the following effects. Since the IIL npn transistor is in contact with a shallow p-layer over the periphery of the bottom of the collector, the injection efficiency between the emitter and the base is improved and the current amplification factor can be increased. In particular, when phosphorus is used as an n-type impurity in the collector, the extrusion effect narrows the base width at the periphery of the collector, increasing the injection efficiency, which has a significant effect on increasing the current amplification factor. On the other hand, two types of ordinary bipolar transistors having different characteristics can be constructed. Since the base region of this one transistor (Tr ₁ described above) is formed of a deep P ⁺ layer with high concentration, the base width is wide and the current amplification factor can be reduced.
A product with high withstand voltage between the collector and emitter can be obtained. In addition, the other transistor Tr ₂ has the peripheral part of the bottom of the emitter in contact with a deep, highly doped P ⁺ layer, so
The base width of this portion becomes wider and the injection efficiency decreases. In particular, by creating a structure in which the bottom surface of the emitter has a large area in contact with the highly concentrated p ⁺ layer, it is possible to further reduce the injection efficiency between the emitter and the base, thereby lowering the current amplification factor. In other words, by adjusting the amount of overlap between the p ⁺ layer and the emitter, the transistor Tr ₁ and
It is possible to form a device with a breakdown voltage and current amplification factor intermediate to those of IILnpn transistors, and these values can be obtained arbitrarily. As described above, according to the present invention, three types of transistors with different characteristics can be formed by combining a highly doped and deep p ⁺ layer and a lightly doped and shallow p layer, and there is no need to increase any process. This makes it possible to simultaneously form bipolar transistors with high breakdown voltage and different characteristics, and IIL vertical transistors with high current amplification factors, without any problems, which has a great effect on the design of integrated circuits. In particular, it has a great effect on the integration of digital integrated circuits using IIL and analog integrated circuits using ordinary bipolar transistors.

[Brief explanation of the drawing]

Figure 1 shows a conventional bipolar transistor and IIL
FIGS. 2A to 2E are cross-sectional views of the manufacturing process of a semiconductor integrated circuit according to an embodiment of the present invention, and FIGS.
FIG. 3 is a partial cross-sectional view of the semiconductor integrated circuit in the step of FIG. 21...p-type silicon single crystal substrate, 23a, 2
3b, 23c...n-shaped island region, 26, 27, 28
b...p ⁺ type high concentration base region, 29, 36...
p-type low concentration base region, 31, 32... n-type emitter region, 33... n-type collector region.

Claims (1)

[Scope of Claims] 1. In a semiconductor integrated circuit including at least an IIL element and first and second bipolar transistors, a peripheral part of the bottom surface of the emitter of the second bipolar transistor is connected to a collector of a vertical transistor of the IIL element. The bottom surface of the emitter of the first bipolar transistor is in contact with the base region, which has a higher concentration and is deeper than the peripheral part of the bottom surface.
A semiconductor device characterized in that the semiconductor device is in contact with a base region having a higher concentration and deeper than the concentration of the base region in contact with the bottom surface of the collector of a vertical transistor of an IIL element. 2. selectively introducing impurities of the other conductivity type into the first, second, and third island regions of one conductivity type, and forming a first high concentration base region within the first island region;
Within the second and third island regions, the second
simultaneously forming second and third high concentration base regions surrounding a part of the third island region;
First and second low concentration base regions having a lower concentration and shallower depth than the second and third high concentration base regions are simultaneously formed in the second and third island regions surrounded by the high concentration base regions of a first high concentration base region of one conductivity type in the first high concentration base region in the first island region;
simultaneously forming a second emitter region spanning from the first low concentration base region to a second high concentration base region, and a collector region within the second low concentration base region; A method for manufacturing a semiconductor device, comprising: 3. The method of manufacturing a semiconductor device according to claim 2, wherein phosphorus is used as an impurity when forming the first and second emitter regions and the collector region.