JPS61207066A - Bi-polar transistor - Google Patents
Bi-polar transistorInfo
- Publication number
- JPS61207066A JPS61207066A JP60048554A JP4855485A JPS61207066A JP S61207066 A JPS61207066 A JP S61207066A JP 60048554 A JP60048554 A JP 60048554A JP 4855485 A JP4855485 A JP 4855485A JP S61207066 A JPS61207066 A JP S61207066A
- Authority
- JP
- Japan
- Prior art keywords
- region
- base
- base region
- value
- hfe
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 6
- 239000000758 substrate Substances 0.000 claims description 5
- 239000012535 impurity Substances 0.000 abstract description 12
- 230000006798 recombination Effects 0.000 abstract description 4
- 238000005215 recombination Methods 0.000 abstract description 4
- 239000000969 carrier Substances 0.000 abstract description 3
- 230000008033 biological extinction Effects 0.000 abstract 1
- 238000009792 diffusion process Methods 0.000 description 4
- 238000002955 isolation Methods 0.000 description 4
- 230000007423 decrease Effects 0.000 description 2
- 230000008034 disappearance Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 239000002243 precursor Substances 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1004—Base region of bipolar transistors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Bipolar Transistors (AREA)
- Bipolar Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
０）産業上の利用分野
本発明は半導体集積回路（ＩＣ）に組込まれるバイポー
ラトランジスタのｈｔｍ値コントロールに関する。DETAILED DESCRIPTION OF THE INVENTION 0) Industrial Application Field The present invention relates to HTM value control of bipolar transistors incorporated in semiconductor integrated circuits (ICs).
（ロ）従来の技術
従来のバイポーラトランジスタとしては、例えば特開昭
５９−２３４３号公報に開示されている。(B) Prior Art A conventional bipolar transistor is disclosed in, for example, Japanese Patent Laid-Open No. 59-2343.
第３図はこのようなバイポーラトランジスタを示し、（
１１はＰ型半導体基板、（２）はＮ 型埋込層、（３）
はＮ−型エピタキシャル層、（４）はＰ 型分離領域、
（５）は分離領域（４）により島状に分離された複数の
島領域である。そして島領域（５）表面にＰ型不純物を
拡散して第１のベース領域（６）を形成し、後にＮ型不
純物を拡散してエミッタ領域（７）及びコレクタコンタ
クト領域（８）を形成し、ＮＰＮ型トランジスタを構成
する。この詩仙の島領域（５）においても前述した拡散
工程で同時にＮＰＮ型トランジスタが形成されている。Figure 3 shows such a bipolar transistor, (
11 is a P-type semiconductor substrate, (2) is an N-type buried layer, (3)
is an N-type epitaxial layer, (4) is a P-type isolation region,
(5) is a plurality of island regions separated into island shapes by the separation region (4). P-type impurities are then diffused into the surface of the island region (5) to form a first base region (6), and later N-type impurities are diffused to form an emitter region (7) and a collector contact region (8). , constitutes an NPN type transistor. In this Shisen Island region (5), an NPN transistor is also formed at the same time by the above-described diffusion process.
貼止した如く構成したトランジスタのｈ□値は、第１の
ベース領域（６）及びエミッタ領域（７）の不純物濃度
とベース幅（第３図Ｎ中Ｋ“Ｂ”で示す）により決定す
る。従って各々の島領域（５）Ｋ同時に形成する限り、
従来のトランジスタは何れもほぼ均一なｈ□値になる。The h□ value of the transistor configured as if pasted is determined by the impurity concentration of the first base region (6) and the emitter region (7) and the base width (indicated by K"B" in FIG. 3N). Therefore, as long as each island region (5)K is formed simultaneously,
All conventional transistors have approximately uniform h□ values.
（ハ）発明が解決しようとする問題点
しかしながら、ユーザーの散水や回路構成上の必要性か
ら同一チップ上に複数の異るｈＰｌ値をもつトランジス
タを形成したい場合、従来のトランジスタではそれぞれ
のｈ□値ごとに拡散工程を追加しなければならず、同時
には形成できないという欠点があった。(c) Problems to be Solved by the Invention However, when it is desired to form transistors with a plurality of different hPl values on the same chip due to the user's needs for water dispensing or circuit configuration, conventional transistors have different hPl values. There was a drawback that a diffusion process had to be added for each value, and that they could not be formed at the same time.
（ロ）問題点を解決するための手段
本発明は貼止した欠点に鑑みてなされ、同一チップ上に
様々なｈ□値をもつトランジスタを同時に形成すること
を目的とし、エミッタ領域（支）に一部重管する第２の
ベース領域（２３）を形成し、第２のベース領域（ハ）
とエミッタ領域（イ）との重畳面積の変化でｈ□値をコ
ントロールすることを特徴とする。(b) Means for Solving the Problems The present invention was made in view of the drawbacks of pasting, and aims to simultaneously form transistors with various h□ values on the same chip. A second base region (23) is formed which is partially overlapped, and a second base region (c) is formed.
The feature is that the h□ value is controlled by changing the overlapping area of the emitter region (a) and the emitter region (a).
（ホ）作用
本発明によれば、第２のベース領域（ハ）によりエミッ
タ領域−直下の不純物濃度が増し、ベースでの注入担体
の消滅による再結合電流が増加するのでｈ□値は小とな
る。その値は第１のベース領域０８１により決まるｈｙ
ｍ値に対し、第２のベース領域（ハ）によりどの程度再
結合電流が増加するかで決まる。(e) Effect According to the present invention, the second base region (c) increases the impurity concentration immediately below the emitter region, and the recombination current due to the disappearance of implanted carriers at the base increases, so the h value is small. Become. Its value is determined by the first base area 081
It is determined by how much the recombination current increases due to the second base region (c) with respect to the m value.
（へ）実施例 以下本発明の実施例を図面を参照しながら説明する。(f) Example Embodiments of the present invention will be described below with reference to the drawings.
第１図は本発明によるバイポーラトランジスタの彌寺寺
侠施例を示し、αυはＰ型半導体基板、（＋２１はＮ＋
型埋込層、α阻まＮ型エピタキシャル層、（１４１はＰ
＋型分離領域、α９αｅは分離領域α４）により島状に
分離された複数の島領域、（Ｌ前駆まＰ型第１のベース
領域、Ｑ９（イ）はＮ 型エミッタ領域、（２１）■は
Ｎ＋型コレクタコンタクト領域、（ハ）はＰ 型彫２の
ベース領域、（２供家酸化膜、Ｃ１５１０６１・・・・
・・■は夫々の領域上に設けられた電極である。FIG. 1 shows an example of a bipolar transistor according to the present invention, where αυ is a P-type semiconductor substrate, (+21 is an N+
type buried layer, α blocked N type epitaxial layer, (141 is P
+-type isolation region, α9αe is a plurality of island regions separated into islands by isolation region α4), (L precursor or P-type first base region, Q9(a) is an N-type emitter region, (21)■ is N+ type collector contact region, (C) is the base region of P mold engraving 2, (2-type oxide film, C151061...
... ■ is an electrode provided on each region.
而して、島領域（１５１には同一チップ上で最大のｈ□
値をもつＮＰＮＷ）ランジスタが形成され、島領域α６
１には第２のベース領域（ハ）を設けることにより小さ
いＬＦＩ値をもつＮＰＮ型トランジスタが形成されてい
る。Therefore, the island area (151 has the largest h□ on the same chip)
NPNW) transistor with value α6 is formed, and island region α6
By providing a second base region (c) in 1, an NPN type transistor having a small LFI value is formed.
本発明の最も特徴とする点は、エミッタ領域−に一部１
畳した第２のベース領域（ハ）を設けた点にある。The most characteristic feature of the present invention is that a portion of the emitter region
The point is that a folded second base area (c) is provided.
この構造によれば、第１と第２のベース領域ａＱ（ハ）
が１畳することにより不純物濃度が増し、ベースでの注
入担体の消滅による再結合電流が増加するのでｈｌｌ値
は小さくなる。この時の値は第２のベース領域（ハ）の
不純物濃度及びエミッタ領域（イ）と第２のベース領域
との重畳面積により増減するが、これを夫々の島領域ａ
ｅに同時に形成すれば不純物濃度は一定なのでｈ□値を
コントロールするＫは前記重畳面積による。前記重畳面
積が大となれば第２のベース領域（ハ）がｈｔｍ値に与
える影醤が大となるのでｈ□値は小となる。According to this structure, the first and second base regions aQ(c)
Since the impurity concentration increases and the recombination current due to the disappearance of implanted carriers at the base increases, the hll value decreases. The value at this time increases or decreases depending on the impurity concentration of the second base region (c) and the overlapping area of the emitter region (a) and the second base region, but this value is
Since the impurity concentration is constant if they are formed simultaneously on e, K, which controls the h□ value, depends on the overlapping area. If the overlapping area becomes large, the influence that the second base region (c) gives to the htm value becomes large, and therefore the h□ value becomes small.
従って本発明によれば、ｈ□値の最も高いトランジスタ
を第１のベース領域α＆のみの構造とし、ｈＦＩ値が小
さくなるに従って前記重畳面積を大とすれは夫々の島領
域α９αｅに様々なり、ヨ値をもつトランジスタを同時
に形成することができる。Therefore, according to the present invention, the transistor with the highest h□ value has a structure with only the first base region α&, and as the hFI value becomes smaller, the overlapping area becomes larger, and the area becomes different in each island region α9αe. transistors with different values can be formed simultaneously.
以下本発明による第１の実施例の製造方法を第２図（イ
）〜に）を参照しながら説明する。The manufacturing method of the first embodiment according to the present invention will be described below with reference to FIGS.
先ず第２図（イ）に示す如く、Ｐ型半導体基板ＵυにＮ
＋型埋込層α２をドープした後エピタキシャル成長法を
用いてエピタキシャル層１３１を形成し、Ｐ＋型分離領
域（１４）を形成することにより複数の島領域αｏｔｉ
＋を形成する。First, as shown in Figure 2 (a), N is applied to the P-type semiconductor substrate Uυ.
After doping the + type buried layer α2, an epitaxial layer 131 is formed using an epitaxial growth method, and a plurality of island regions αoti are formed by forming a P + type isolation region (14).
Form +.
次に第２図（ロ）に示す如く、選択拡散法を用いてＰ型
不純物、例えばボロンを拡散し、第１のベース領域（１
７）（１〜を形成する。Next, as shown in FIG.
7) (form 1~).
次に第２図（ハ）に示す如（、再びＰ型不純物を拡散し
て所望の島領域Ｑ６１に第２のベース領域（ハ）を第１
のベース領域（１１９より浅く形成する。この時の拡散
窓の大きさは後に形成するエミッタ領域−との重畳面積
で所望のｈｕｍ値が得られるようにする。Next, as shown in FIG. 2(c), the P-type impurity is diffused again to form the second base region (c) in the desired island region Q61.
The base region (119) is formed shallower than the base region (119).The size of the diffusion window at this time is determined so that a desired hum value can be obtained based on the area of overlap with the emitter region to be formed later.
次に第２囚に）に示す如く、Ｎ型不純物、例えばリンを
拡散し、Ｎ 型エミッタ領域Ｑ９翰、コレクタコンタク
ト領域Ｑυのを形成し、酸化膜伽）にコンタクトホール
なあけた後に周知の蒸着技術にて電極部材、例えばアル
ミを蒸着し、所望形状にエツチングすることにより各領
域上に電極（ハ）伽１・・・・・・側を設ける。Next, as shown in Figure 2), an N-type impurity, such as phosphorus, is diffused, an N-type emitter region Q9 and a collector contact region Qυ are formed, and a contact hole is made in the oxide film. An electrode member, such as aluminum, is deposited using a vapor deposition technique and etched into a desired shape, thereby providing electrodes (c) on each region.
同図では島領域−に同一チップ上で最も高いｈ□値をも
つトランジスタが形成され、島領域側にはそれより小さ
いｈ□値をもつトランジスタが形成されている。In the figure, a transistor with the highest h□ value on the same chip is formed in the island region, and a transistor with a smaller h□ value is formed on the island region side.
（ト）発明の詳細
な説明した如く、本発明によれば１回の拡散工程を追加
するだけで同一チップ上に様々なｈｒｍ値をもつトラン
ジスタを同時に形成することができるので、ユーザーの
要求に即対応でき、回路説計がより容易になる。(g) As described in detail, according to the present invention, transistors with various hrm values can be simultaneously formed on the same chip by adding one diffusion process, so that it can meet user requirements. It can be applied immediately and circuit estimation becomes easier.
第１図ビ）（ロ）はそれぞれ本発明の詳細な説明するた
めの断面図、平面図、第２図（イ）〜に）は本発明によ
る実施例の製造方法を説明するための断面図、第３図は
従来のバイポーラトランジスタを示す断面図である。
主な図番の説明
αυは半導体基板、α５１（１６１は島領域、αηａ阻
ま第１のベース領域、（ハ）は第２のベース領域、α９
＠はエミッタ領域、の）はベース幅である。
出願人 三洋電機株式会社 外１名
代理人 弁理士 佐 野 静 失
策１図（岨
第２図（イ）
第２図（田
１ら １７
第 ２ 図 （ハ）１１Figure 1 B) and (B) are sectional views and plan views for explaining the present invention in detail, respectively, and Figures 2 (A) to 2) are sectional views for explaining the manufacturing method of the embodiment according to the present invention. , FIG. 3 is a cross-sectional view showing a conventional bipolar transistor. Explanation of main figure numbers αυ is the semiconductor substrate, α51 (161 is the island region, αηa is blocked by the first base region, (C) is the second base region, α9
@ is the emitter region, and ) is the base width. Applicant Sanyo Electric Co., Ltd. and one other representative Patent attorney Shizuka Sano Mistakes Figure 1 (Figure 2 (A)) Figure 2 (Ten et al. 17 Figure 2 (C) 11
Claims (1)
タキシャル層と該エピタキシャル層を島状に分離した島
領域と該島領域表面に二重に形成した一導電型の第１の
ベース領域と逆導電型のエミッタ領域とを備えたバイポ
ーラトランジスタにおいて、前記エミッタ領域と一部重
畳し且つ前記第１のベース領域より浅い第２のベース領
域を備え、該第２のベース領域と前記エミッタ領域との
重畳面積を変化させることによりｈ＿■＿■値をコント
ロールしたことを特徴とするバイポーラトランジスタ。(1) An epitaxial layer of the opposite conductivity type formed on a semiconductor substrate of one conductivity type, an island region in which the epitaxial layer is separated into islands, and a first base region of one conductivity type formed double on the surface of the island region. and an emitter region of opposite conductivity type, including a second base region that partially overlaps the emitter region and is shallower than the first base region, the second base region and the emitter region A bipolar transistor characterized in that the h_■_■ value is controlled by changing the overlapping area with the bipolar transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60048554A JPS61207066A (en) | 1985-03-12 | 1985-03-12 | Bi-polar transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60048554A JPS61207066A (en) | 1985-03-12 | 1985-03-12 | Bi-polar transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61207066A true JPS61207066A (en) | 1986-09-13 |
Family
ID=12806591
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60048554A Pending JPS61207066A (en) | 1985-03-12 | 1985-03-12 | Bi-polar transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61207066A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1998010469A1 (en) * | 1996-09-06 | 1998-03-12 | Mitsubishi Denki Kabushiki Kaisha | Transistor and method of manufacturing the same |
| US6878998B1 (en) * | 2000-04-13 | 2005-04-12 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device with region that changes depth across the direction of current flow |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5534462A (en) * | 1978-08-31 | 1980-03-11 | Matsushita Electric Ind Co Ltd | Method and apparatus for semiconductor |
-
1985
- 1985-03-12 JP JP60048554A patent/JPS61207066A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5534462A (en) * | 1978-08-31 | 1980-03-11 | Matsushita Electric Ind Co Ltd | Method and apparatus for semiconductor |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1998010469A1 (en) * | 1996-09-06 | 1998-03-12 | Mitsubishi Denki Kabushiki Kaisha | Transistor and method of manufacturing the same |
| US6878998B1 (en) * | 2000-04-13 | 2005-04-12 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device with region that changes depth across the direction of current flow |
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