JPS63293974A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To obtain a bipolar pnp transistor, which controls the depth of a p-type well and can control hFE excellently without diffusion for the p-well, by previously cutting a trench to one part of the surface of an n-type semiconductor layer to which a p-type diffusion layer for element isolation is formed. CONSTITUTION:An epitaxial-grown n<-> type Si layer 2 is shaped onto a substrate 1. A p<+> type (a buried layer) 4 formed by implanting and diffusing B ions onto the p<-> type substrate 1 is buried as a buried layer by shaping the n<-> type Si layer 2 onto the p<+> type (the buried layer) 4. A trench 10 shaped by etching one part of the surface of the n<-> layer is formed, and p-type diffusion is conducted along the trench 10, thus shaping an element isolation p<+> layer 12. Consequently, the depth d1 of the element isolation region p layer 12 and the depth d2 of a p-well layer on the buried layer can be brought to d1approx.=d2 by forming a stepped section by the trench 10, thus allowing the simultaneous diffusion of the p layer 14. Accordingly, the depth d2 of the p-well layer 14 can easily be selected in optimum depth, thus improving the controllability of the hFE of a bipolar element.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to semiconductor devices, particularly triple diffused mxcm vertical pnp
) regarding transistor technology.

[Prior art]

The mainstream of vertical transistors is npn) transistors, but it is difficult with current technology to make linear pnp transistors, which are used complementary thereto, to match the characteristics of npn) transistors.

The present inventor studied the case of making a bipolar (vertical type) pnp transistor.6 The following are not publicly known techniques, but are techniques studied by the present inventor, and the outline thereof is as follows. That is, as shown in FIG. 8, an n-type buried layer 3 and a P-type Si substrate 1 are formed between a P-type Si substrate 1 and an n FI S 1 layer 2 epitaxially grown thereon.
The type buried layer 4 is buried and used as a collector, and the n-type layer 4 is buried.
Based on layer 2, on the surface of which is a normal bipolar NPN
) This structure uses the P type layer 5 as an emitter, which utilizes transistor pace diffusion.

In addition, as shown in FIG. 9, a P-type well N46 is formed in contact with the P-type buried layer 4, and an n-type well N7 is formed in this P-type well 6 to serve as a base. A triple diffusion type PNP transistor has been proposed in which a P-type diffusion layer 5 is further formed in the transistor 7 to serve as an emitter (Tokuko Sho-) (Matsushita patent).

In this case, WII can be controlled by using n-wells.

[Problem that the invention seeks to solve]

In the pnp structure using epitaxial n4 at the pace n, there is a problem that the base width WB is determined by P diffusion (rising) from the P buried layer, making hrg control difficult.

When using an n-well in the above-mentioned pace, in addition to the former process, two diffusion processes are required to form a p-well and an n-well, making the process complicated.

The present invention has been made in order to eliminate the above-mentioned problems, and its purpose is to provide a bipolar pnp (pnp) transistor that can improve hrg control without performing diffusion for the p-well.

[Means for addressing problems]

A brief summary of typical inventions disclosed in this book is as follows.

That is, an n-type semiconductor layer is epitaxially grown on one main surface of a P-type semiconductor substrate through a partially high-concentration P-type buried layer, and a layer for device isolation is grown from a part of the surface of this n-type semiconductor layer. At the same time, a P-type diffusion layer is formed to be connected to the P-type substrate, and at the same time, the P-type separation diffusion is performed from another part of the surface of the n-type semiconductor layer to form a P-type well for the bipolar region. By forming a groove in a part of the surface of the n-type semiconductor layer that forms the P-type diffusion layer for element isolation, the P-type diffusion layer is formed so as to reach the type buried layer.
It controls the depth of the mold well.

[For production]

According to the above means, the number of P diffusion steps can be reduced, and the P type well for the bipolar region can be properly controlled by the depth of the groove of the P type diffusion layer for element isolation.
It becomes easy to improve the hFIc of a bipolar pnp (pnp) transistor, and the above object can be achieved.

[Embodiment 1] Figure 1 shows an embodiment of the present invention, and is a schematic cross-sectional view of a bipolar pnp transistor using trench and pn junction isolation (Eitzle-Sheen) technology.

1 is a P-type S1 substrate (substrate), and 2 is an n-type Sl substrate epitaxially grown on the substrate 1. 4
is a P-type (buried layer) obtained by ion implanting and diffusing B (poron) on a P-type plate 1, and is buried as a buried layer by forming an n-ya S1 layer 2 thereon. 10 is n-″ra
This is a groove whose surface is partially etched, and by performing P-type diffusion along this groove 10, an element isolation P layer 12 is formed.

Reference numeral 14 denotes a P-type well formed on the n-layer surface of the portion where no groove is formed. This P-well 14 is an element isolation P/
It is formed by simultaneous diffusion with i&1i12. 7 is an n-type well and serves as a space region for a bipolar (pnp) transistor. 5 is a P type diffusion layer which also serves as an emitter region. 1
Reference numeral 7.18 is a collector extraction portion formed using separation P layer diffusion and emitter P diffusion.

The effects obtained from the above examples are as follows.

(1) The P well 14 for element isolation and the P well 14 for bipolar elements are formed in one diffusion process, which simplifies the process.

(2) By forming a step using 1610, the depth d of the element isolation region PA12 and the depth d of the P well layer on the buried layer can be set to d, = d, and the P layer 14 simultaneous diffusion is possible. This makes it easy to select the optimum depth d of the P-well layer 14, and the hFE controllability of the bipolar device is improved.

[Embodiment 2] FIGS. 2 to 5 are process cross-sectional views of a method for manufacturing a bipolar PNP transistor according to another embodiment of the present invention.

The steps will be explained below in order.

(11P-type S1 substrate (substrate) 1 is implanted with B ions and a P buried layer 4 is formed by diffusion, and then an epitaxial nmSi layer 2 is grown.

5to by surface oxidation and photoetching of n-type 5tR4
A z mask 8 is formed (FIG. 2).

(2) B (boron) ions are implanted and diffused using the Si0g mask 8 to form a P layer (PI) for element isolation.
SO) 12 and a P-well 14 for the Pivot 2 element are formed at the same time (FIG. 3).

(3) By photoresist mask processing, an n-well 7 for a space region of the bipolar element is formed on a part of the surface of the p-well (FIG. 4).

(4) After forming the emitter P layer 5 and the collector extraction part P layer 18 by photoresist mask processing and forming the base extraction part n''/115, contact photoetching is performed.
A11J that over-contacts the pace emitter and collector regions by I vapor deposition, patterning, and etching.
An L pole 9 is provided. In this way bipolar pnp
) Create a transistor (5th rS!U).

According to the above embodiment, P diffusion for element isolation and P quel diffusion for bipolar elements can be performed in the same process, thereby reducing the number of process steps, reducing cost, and facilitating control of impurity concentration.

[Embodiment 3] FIG. 6 shows an embodiment of the present invention, in which a vertical pnp using shallow groove and pnn junction isolation technology is shown.
) is a schematic cross-sectional view of a transistor.

1 is a P-type St substrate (substrate), and 2 is an n-8i layer epitaxially grown on the substrate. 3 is an N++ buried layer in which SB or the like ion-implanted into the substrate surface is diffused, and 4 is a P type buried layer in which B is also diffused, which are the same as in the conventional example. The thickness of the epitaxial n-St Nj is, for example, 2 μm.

Reference numeral 11 denotes a deep layer for isolation (depth ds!: 1 μm) in which a groove is etched on the surface of the epitaxial n layer, and a P-type diffusion isolation blind layer 12 is formed between this deep groove and the substrate.

13 is a shallow groove (depth 0.3 μm) for forming an emitter.
This shallow layer 13 is formed on the surface of the epitaxial layer above the P-type implant 4.

14 is a shallow groove 1 using the above-mentioned isolation type P type diffusion.
P-type diffusion 1m formed in 3, P in Figure 4 above.
This corresponds to the mold well 6.

The condition is that the depth aprso of the isolation P-type diffusion layer is dpt sow dcp-dB 1+α between the epitaxial layer thickness clip and the deep groove depth dat. Although the concentration of the P-type layer is not necessarily optimal, it can be solved by controlling the shallow n-depth dtm of the epitaxial layer by silicon etching.

7 is an n layer formed on the surface of the P type layer 14 by n type diffusion.
- type well layer.

Reference numeral 5 denotes a P-type diffusion layer formed on a part of the surface of the n-type well, which becomes the emitter of the pnp transistor. This P-type diffusion layer 5 can be formed by utilizing the space diffusion (BR diffusion) of a vertical npn transistor. .

15 is the surface of the n- type well f) n+ formed on the other part
It becomes the pace extraction part of the type scattered layer PNP) transistor.

16 is a deep groove for taking out the collector, and this deep groove is an extension of the isolation depth #$11 to the upper part of the buried layer. 6 17 is a deep groove between this deep groove 16 and the P type buried layer 4. P formed using einlacetic carbon diffusion
It is a type layer.

Reference numeral 18 denotes a P type diffusion layer formed on the surface of the P type layer 170 using the I3R diffusion, and serves as a collector extraction portion of the pnp transistor.

The effects obtained from the above embodiments are as follows.

(1) The impurity ia degree profile of the isolation P-type diffusion layer is suitable for the part corresponding to the vertical pnp transistor σ) P-type well, so that the isolation P-type diffusion island and the P-type well can be A single diffusion layer serves both purposes, reducing the number of diffusion steps.

(2) Since the pace width (WB) is determined by the n-type well 7 and the P & diffusion layer 5, P and B from the buried layer
It can be controlled without considering the "rising" diffusion of (boron), and the hr is as good as the P-type well method.
g controllability is obtained.

(3) By utilizing such grooves and isolation diffusion, the collector lead-out portion can be formed in the deep groove portion as a vertical pnp transistor, and the collector resistance Rcs can be lowered.

[Example 4] A deep trench and a shallow trench are formed in one semiconductor substrate, and the height from the substrate and the buried layer is used to advantageously perform isolation depression diffusion layer and collector extraction diffusion. A technique for forming an integrated logic element (integrated logic element) is described in Japanese Patent Laid-Open No. 58-79752 filed by the present applicant.

FIG. 7 shows an example in which the first embodiment shown in FIG. 6 is applied to an IC for a VTR, in which vertical pnp) transistors Qst, vertical npn) transistors Q, and IILQs are formed on one semiconductor substrate. FIG. 3 is a longitudinal cross-sectional view of a formed element.

As shown in the figure, the deep #11 of the Q1 cycle and the isolation P type diffusion 12 can use the deep grooves of Q, , Q and the inlay vr:/PFk diffusion as they are.

The shallow trench 13 in Ql can utilize the shallow @13 for the active region in Qs.

The P-type layer (fel) 14 in the shallow groove of Ql and the P-type layer 17 in the collector lead-out portion utilize the isolation 17 structure.

In the n-well 7 in the shallow groove of Q, n-diffusion for increasing the amplification factor Bi of the active region of Q can be used as is.

Ql emitter P type diffusion and collector extraction + P type diffusion can utilize Q, pace P type diffusion.

The pace extraction n+ type diffusion of Ql can utilize the emitter n+ type diffusion of Q.

The effects obtained from the above-mentioned embodiments are particularly applicable to the process using the conventional method of forming a diffusion layer in the groove.
vertical npn on one substrate without adding additional processes.
) A transistor and a vertical pnp transistor can be formed, for example, a complementary transistor with good hFE controllability can be realized.

Although the invention made by the present inventor has been specifically explained based on the examples, the present invention is not limited to the above-mentioned examples, and can be modified within a range without departing from the gist thereof.

The present invention can be applied to general ICs in which deep grooves and shallow grooves are formed on the surface of a substrate and a diffusion layer is provided in the grooves.

In addition to the above, the present invention also provides isolation 17 by P-type diffusion.
It is possible to apply the structure to a bipolar IC.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

That is, an IC having a bipolar pnp (pnp) transistor with excellent electrical characteristics can be provided without increasing the number of steps.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of a bipolar pnp (pnp) transistor showing one embodiment of the present invention. FIGS. 2 to 5 are cross-sectional views of a semiconductor device manufacturing process showing other embodiments of the present invention. FIG. 6 shows another embodiment of the invention (bipolar pnp)
FIG. 3 is a cross-sectional view of a transistor. FIG. 7 is a partial sectional view of a semiconductor integrated circuit device showing an applied embodiment of the present invention. Are Figures 8 and 9 Paibo? FIG. 3 is a cross-sectional view showing a conventional example of a pnp) transistor. DESCRIPTION OF SYMBOLS 1... P-type Si substrate, 2... 81 epitaxial layers, 3... N++ buried layer, 4... P-type buried layer, 5...
... Emitter P-type diffusion layer, 6... P-type well, 7.
... n-type well (pace), 8...810. , mask, 9... A111L pole, 10... groove, 11... e# for isolation long, groove, 12... isolation ten P type diffusion layer, 13... shallow groove, 14...P full layer (well), 15...Pace extraction n+ type scattered layer 16...Deep sea for collector, 17...Collector sales P type N, 18...Collector extraction P-type diffusion layer. 11' Agent Patent Attorney Uo Ogawa; No. 1
Figure 4 - P+ Buried Shoulder Figure 2 Figure 3 Figure 4 Figure 5FjA Figure 6 Figure 8 Figure 9

Claims (1)

[Claims] 1. A high-concentration P-type buried layer is buried between a P-type semiconductor substrate and an n-type semiconductor layer epitaxially grown thereon, and P is buried from a part of the surface of the n-type semiconductor layer. A semiconductor device in which a P-type separation layer connected to a type substrate is provided, a P-type well is formed extending from the other surface of the n-type semiconductor to the P-type buried layer, and an element is formed in this well. A semiconductor device characterized in that the depth of the P-type isolation layer and the depth of the P-type well are controlled by forming a step on the surface of the n-type semiconductor layer. 2. In the semiconductor device according to claim 1, the depth of the P-type isolation layer is made smaller than the depth of the P-type well by providing the step. 3. Epitaxially growing an n-type semiconductor layer on one main surface of the P-type semiconductor substrate through a heavily doped P-type buried layer;
At the same time, a P-type diffusion layer for element isolation is formed on a part of the surface of this n-type semiconductor layer so as to be connected to the substrate.
A method of manufacturing a semiconductor device, characterized in that a P-type well for a bipolar region is formed from another part of the surface of a type semiconductor layer by utilizing the P-type isolation diffusion. 4. In the method for manufacturing a semiconductor device according to claim 3, a groove is formed in the surface of the n-type semiconductor where a P-type diffusion layer for element isolation is formed, thereby forming a P-type diffusion layer in that portion. It is formed to be shallower than the depth of the P-type diffusion layer of the P-type well.