JPH02148737A - Vertical bipolar transistor - Google Patents

Abstract

PURPOSE:To reduce the element area and make a smaller transistor by making a collector electrode taking-out groove in a specific position an epitaxial layer. CONSTITUTION:An N-type epitaxial layer 4 formed on a P-type semiconductor substrate 1 and a p-type buried diffusion region 3, formed near the interface of the substrate 1 and the layer 4, electrically separated from the substrate 1 with an N-type buried diffusion region 2' and acting as a collector, are installed. An electrode is taken out of the region 3 through a collector electrode taking-out groove 7 made in a specific position in the layer 4 so as to reach the region 3 and insulated from the layer 4. Therefore, a depletion layer does not extend from the groove 7 by voltage applied between an emitter and a collector, the interval between the groove 7 and the P type diffusion layer 9 can be shortened, and a smaller transistor can be manufactured.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention is applicable to vertical bipolar transistors, and particularly to vertical PNP transistors with a floating collector in which the collector is separated from a P-type substrate to an electric electrode. (Hereinafter referred to as CFV-PNP transistor.)
Regarding.

〔overview〕

For example, in a CVF-PNP (CVF-PNP) transistor in which the collector is electrically isolated from a P-type semiconductor substrate, the collector electrode can be taken out from the P-type buried expansion region that becomes the collector at a predetermined location in the epitaxial layer where the transistor is formed. By reaching the P-type buried diffusion region at the position of the collector electrode through a collector electrode extraction groove provided insulating from the epitaxial layer with an insulating film, the transistor can be made smaller. This is what I did.

[Conventional technology]

FIG. 4 is a vertical cross-sectional view showing a main part of an example of a conventional CFV-PNP transistor, mainly showing the impurity region. As shown in Fig. 4, conventionally, CFV-PN
P) In order to electrically connect with the P-type buried diffusion region 3 which becomes the collector of the transistor, an N-type buried diffusion region 2 and a P-type buried diffusion region 3 are formed on the surface of the P-type semiconductor substrate 1. , furthermore, an N-type epitaxial layer 4 is formed on the P-type semiconductor substrate 1.
After growing, P-type high concentration impurities are diffused from the surface of the N-type epitaxial layer 40 so as to reach a predetermined region on the P-type buried diffusion region 3 to form a P-type cavity concentration region 12.

[Problem that the invention seeks to solve]

The conventional CFV-PNP) transistor described above has an N-type epitaxial layer 4 as a base and a P-type semiconductor substrate 1.
The electrical isolation must be electrically isolated from P
This is done using a type buried diffusion region 3 and a P type cavity concentration region 12 formed by diffusion from a predetermined region on the surface of the N type epitaxial layer 4. Further, this P-type cavity concentration region 12 also served as a collector electrode extraction.

Therefore, when the voltage applied between the collector and emitter of the CFV-PNP) transistor increases, a depletion layer extends from this P-type cavity concentration region 12 into the N-type epitaxial layer 4, and the CFV-PNP) transistor A problem arises that causes punch-through.

Therefore, the distance between the P-type diffusion layer 9, which is the emitter of the CFV-PNP transistor, and the P-type cavity concentration region 12 is
Since the voltage applied to the FV-PNP transistor must be increased as the voltage increases, it has the drawback of hindering miniaturization of the transistor.

An object of the present invention is to provide a vertical bipolar transistor that can be miniaturized by eliminating the above-mentioned drawbacks.

[Means for solving problems]

The present invention includes a semiconductor substrate of one conductivity type, an epitaxial layer of an opposite conductivity type provided on the semiconductor substrate, and a layer electrically isolated from the semiconductor substrate near the interface between the semiconductor substrate and the epitaxial layer. In a vertical bipolar transistor provided with a buried diffusion region of one conductivity type and serving as a collector, the epitaxial layer has a conductive layer that reaches the buried diffusion region of one conductivity type at a predetermined position of the epitaxial layer and is connected to the epitaxial layer. The device is characterized by having a collector electrode extraction groove insulated by an insulating film.

[Effect]

In the present invention, for example, in a CFV-PNP (CFV-PNP) transistor, an electrode can be taken out from a P-type buried diffusion region which becomes a collector by placing the electrode in a predetermined position of an N-type epitaxial layer in the epitaxial layer so as to reach the P-type buried diffusion region. This is done through a collector electrode extraction groove provided insulated by an insulating film.

Therefore, the extension of the depletion layer from the collector electrode lead-out groove due to the applied emitter-collector voltage is eliminated, and the distance between the collector electrode lead-out groove and the emitter of the transistor, for example, a P-type diffusion layer, is determined without considering the extension of the depletion layer. This allows the transistor to be made smaller.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a longitudinal sectional view showing the main parts of the first embodiment of the present invention.
The parts formed by the metallization process after the process of forming an interlayer film and the process of forming a contact are omitted.

The present embodiment includes a P-type semiconductor substrate 1, an N-type epitaxial layer 4 provided on the P-type semiconductor substrate 1, and a P-type semiconductor substrate 1 in the vicinity of the interface between the P-type semiconductor substrate 1 and the epitaxial layer 4. 1 and a P-type buried diffusion region 3 which is provided as a collector and is electrically separated from the P-type buried diffusion region 2 by an N-type buried diffusion region 2. A collector electrode extraction groove 7 is provided which reaches the buried diffusion region 3 and is insulated from the epitaxial layer 4 by an oxide film 5.
A polycrystalline silicon layer 8 serving as a collector electrode is provided via this collector electrode extraction groove 7.

A feature of the present invention is that a collector electrode extraction groove 7 is provided in FIG.

Next, regarding the manufacturing method of the second embodiment, FIGS.
This will be explained using a vertical cross-sectional view of the main steps shown in (d).

First, as shown in FIG. 2(a), on the P-type semiconductor substrate 1,
After forming the N-type buried diffusion region 2 and the P-type buried diffusion region 3, an N-type epitaxial layer 4 with an impurity concentration of 6 XIO"cm' is grown to a thickness of 10 μm, and an oxide film 5 is formed on the N-type epitaxial layer 4. A total of 700 layers are formed by thermal oxidation, and an oxidation-resistant film, such as a nitride film 6, is vapor-phase grown to 100 OA.

Next, as shown in FIG. 2(b), a collector electrode extraction groove 7 reaching the P-type buried diffusion region 3 is formed in the N-type epitaxial layer 4 using existing photoresist technology and etching technology. . Etching was performed using a parallel plate type etching device.

The nitride film 6, oxide film 5, and N-type epitaxial layer 4 are selectively removed by 9 μm to 10 μm by anisotropic etching using a similar gas. The width of this collector electrode extraction groove 70 is 4μI! 1 to 5 μm is preferable.

Next, a thermal oxide film 5 is formed by 500 to 1000 people on the side surface of the collector electrode extraction groove 7 formed above. The thickness of the oxide film is determined by the withstand voltage applied to the CFV-PNP transistor, and a stacked structure with a nitride film is also possible.

Next, as shown in FIG. 2C, the oxide film 5 formed at the bottom of the collector electrode extraction groove 7 is removed by anisotropic etching using a CF4 gas. Although the nitride film 6 is also etched here, by forming the film thicker than the oxide film 5, only the oxide film 5 formed at the bottom of the collector electrode extraction groove 7 is etched away. Next, boron is implanted into the bottom of the collector electrode extraction groove 7 by ion implantation.

Energy is 5Qkev, dose is IXIO”
cm-2 or more is preferable. Also, as annealing, N2
A temperature of 1000° C. for 20 minutes in an atmosphere is used. Next, after removing the nitride film 6 by etching with hot phosphoric acid, a polycrystalline silicon layer 8 is grown to a thickness of 15 μm over the entire surface of the substrate. After forming the polycrystalline silicon layer 8, boron diffusion is performed at 950°C, and further 11
Pressing is performed at 00°C for 20 minutes in a nitrogen atmosphere.

Next, as shown in FIG. 2(6), a polycrystalline silicon layer 8
The entire surface is anisotropically etched with a CF4 gas to remove polycrystalline silicon layer 8 until 1 to 2 μm of polycrystalline silicon layer 8 remains on oxide film 5. Next, the polycrystalline silicon layer 8 is selectively removed using existing photoresist and etching techniques, and the CF
V-PNP) Collector electrode extraction groove 7 of transistor
form. Thereafter, as shown in FIG. 1, a P-type diffusion layer 9 and an N-type diffusion layer 10 are formed using existing photoresist technology and etching technology. The P-type diffusion layer 9 is formed by boron ion implantation at an energy of 50 kev and a dose of 1×10 14 cm −2 . Also, the N-type diffusion layer 10
is formed by phosphorus diffusion at 950° C. using the oxide film 5 as a mask material.

After that, CFV/PNP was manufactured using existing metallization technology.
Take out the emitter, collector and base of the transistor.

FIG. 3 is a longitudinal sectional view showing the main parts of a second embodiment of the present invention. The second embodiment is the same as the first embodiment shown in FIG. 1 except that a base phosphorus diffusion region 11 is added.

A feature of the present invention is that, as shown in FIG. 3, a collector electrode extraction groove 7 is provided.

Next, the manufacturing method will be explained using FIGS. 2(a) to 2(6). In FIG. 2(a), after growing the N-type epitaxial layer 4, phosphorus is ion-implanted into the region where the CFV-PNP) transistor located on the P-type buried diffusion region 3 is to be formed, thereby forming the base phosphorus diffusion region 11. Form. Energy is 1QQkev Dose amount is 1×1014cm
-2 is the optimal tear.

Thereafter, the steps after the step of forming the oxide film 5 shown in the first embodiment are the same.

In the second embodiment, by forming the base phosphorus diffusion region 11, the thickness of the epitaxial growth layer 4 can be reduced.
When applying 0 Volt and without the base phosphorus diffusion region 11, the thickness of the epitaxial growth layer 4 is required to be 13 μm or more, but the structure of the second embodiment has the advantage that the thickness can be reduced to 8 μm. .

Although the above explanation deals with PNP) transistors, it also applies to NPN) transistors.

〔Effect of the invention〕

As explained above, the present invention provides, for example, CFV-PN
P) A collector electrode is taken out from the P-type buried diffusion region 3, which becomes the collector of the transistor, by etching away a predetermined region of the N-type epitaxial growth so as to reach the P-type buried diffusion region 3. This is done using a boron-doped polycrystalline silicon layer buried in the trench 7, and this boron-doped polycrystalline silicon layer 8 and CFV-PNP
) Since it is separated from the N-type epitaxial layer 4 which is the base of the transistor by an insulating film formed by the oxide film 5, it is separated from the N-type epitaxial layer 4 which is the base of the transistor.
The distance between the type diffusion layer 10 and the collector electrode extraction groove 7 of the CFV-PNP transistor can be narrowed.
This has the effect of reducing the element area.

For example, CFV-PNP) transistor l:40Vol
When applying t, the conventional technology requires a distance of 20 μm between the emitter and the collector electrode lead-out portion, but according to the present invention, the distance can be reduced to 5 μm, and the device area can be reduced to A.
You can do the following, and the effect is great.

[Brief explanation of the drawing]

FIG. 1 is a longitudinal sectional view showing the main parts of a first embodiment of the present invention. FIGS. 2(a) to 2(6) are longitudinal cross-sectional views of the main manufacturing steps. FIG. 3 is a longitudinal sectional view showing the main parts of a second embodiment of the present invention. FIG. 4 is a longitudinal sectional view showing the main parts of a conventional example. 1... P-type semiconductor substrate, 2... N-type buried diffusion region,
3... P type buried diffusion region, 4... N type epitaxial layer, 5... Oxide film, 6... Nitride film, 7a... Collector electrode extraction groove, 8... Polycrystalline silicon layer, 9.
... P type diffusion layer, 10... N type diffusion layer, 11... Baseline diffusion region, 12... P type fovea concentration region. 2 P type 14 bodies substrate: N type ygL included wide forging tilting: P type embedded wide movable base N type epitaxy V le foot: posterior film 7: Corefta @ -0 Ominade; nose 8 2 polycrystalline silicon・Wi 9: Acid layer 10 on P type: N type 2, Kotou ■ P guard 44 & substrate N type embedded F, comparative area P type I-Kitsune Tori monk formation N type engineer bit N shal C1 ;;-I72 membrane 7: Kore 7 Riq Higashi directori Mi Riman 8: Polycrystalline silicon I) Con 1 9: P type name 1 10: N type 2 defeat layer 11: N-nu, Lin M , to the G investment, the shoulder of the I9!1 3 Figure 1: P-type conductor 1 plate 2: N-type i-komi fox-cho area 3: P-type embedded rose 4: N-type shrimp 7 tsubo Somali layer 9: P type 13 Hot heat 10: N type 2 mosquitoes 1 12: P type Hatakenoya deposit Conventional example 0 construction irises 4 Figure

Claims (1)

[Claims] 1. A semiconductor substrate of one conductivity type, an epitaxial layer of an opposite conductivity type provided on the semiconductor substrate, and an electrical connection from the semiconductor substrate to the vicinity of the interface between the semiconductor substrate and the epitaxial layer. In a vertical bipolar transistor having a buried diffusion region of one conductivity type which is provided separately from a transistor and serves as a collector, the buried diffusion region of one conductivity type is reached at a predetermined position of the epitaxial layer and A vertical bipolar transistor characterized in that a collector electrode extraction groove is provided which is insulated from the epitaxial layer by an insulating film.