JP2009027050A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device, capable of suppressing the potential variations of adjacent vertical diodes when a forward current is applied on vertical diodes, securing stable circuit operation, and reducing the occupied area of an isolation layers among the vertical diodes, with respect to the element area. <P>SOLUTION: A trench groove 20 is formed on a p-type semiconductor layer 1 sandwiched in between an n-type diffusion layer 3 and an n-type diffusion layer 4. An n-type isolation layer 5 is formed at the bottom part of the trench groove 20. P-type isolation layers 6 are formed in the p-type semiconductor layer 1 on both the sides of the trench groove 20. A conductor 16 is filled inside the trench groove 20, a metal electrode 10 is formed on an upper end part of the conductor 16, and the metal electrode 10 is connected to the ground GND. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device in which a plurality of semiconductor elements are integrated on the same semiconductor substrate to form a circuit, and a surge protection element is formed.

In a semiconductor device in which a plurality of power semiconductor elements, a drive circuit, and a surge protection element are formed on the same semiconductor substrate, the power is generated by applying an external surge voltage or noise voltage and a surge voltage generated by the operation of the power semiconductor element itself. A semiconductor element, a control circuit, etc. may malfunction.
In order to prevent this, an isolation structure such as a dielectric isolation structure or a junction isolation using a high concentration buried epitaxial layer and a high concentration isolation diffusion layer has been applied. Also in semiconductor devices for automobiles, the area of power semiconductor elements and control circuits is reduced by advancing miniaturization and integration of elements and integration of functions using the dielectric isolation and junction isolation techniques.
However, semiconductor devices for automobiles have particularly strict requirements for ESD (Electric Static Discharge) resistance, surge resistance, and noise resistance, so that surge protection elements do not affect the surrounding semiconductor elements and control circuits. The protection element and the semiconductor element and control circuit formed around the protection element must be electrically separated.
For this purpose, it is common practice to form a horizontal surge protection element in the isolated region using dielectric isolation or junction isolation for the surge protection element, but the horizontal surge protection element is occupied. The area increases and the chip area increases.

For this reason, there are many examples in which the surge protection element is not formed on the same semiconductor substrate, the chip area is reduced, and a diode, a resistor, a capacitor, or the like is individually attached as the surge protection element to achieve high surge resistance.
Further, a vertical diode as a surge protection element is formed on the same semiconductor substrate to reduce the area. In this case, since the current density can be increased as compared with the horizontal surge protection element, a high surge voltage can be absorbed even in a small area, and the surge protection effect is great.
When a vertical diode is used for input protection of an integrated circuit (IC) such as a control circuit, the cathode electrode of the vertical diode, which is a surge protection element, is formed on the surface side of the semiconductor substrate, and this is also used as an input terminal. Often, the input terminal is connected to the high potential side of Vcc through a pull-up resistor.
The input terminal is also connected to a power semiconductor element and a control circuit to be protected. When the input terminal is pulled up, the pn junction of the vertical diode, which is a surge protection element, is always applied with a reverse bias, so that no forward current flows through the vertical diode in normal operation.
However, when a large negative surge voltage that causes the pn junction to be forward biased is applied to the input terminal, a very large current flows through the vertical diode. Part of this large current is caused by the parasitic npn transistor comprising the n-type diffusion layer (cathode region) of the vertical diode adjacent to the vertical diode to which the surge voltage is applied and the p-type semiconductor substrate. Since it acts as a base current, this parasitic npn transistor operates.

Due to the operation of the parasitic npn transistor, the current flowing in the adjacent vertical diode flows from Vcc through the pull-up resistor, so that the potential of the cathode electrode of the adjacent vertical diode, that is, the adjacent input terminal is lowered by the voltage drop of the pull-up resistor. The operation of the control circuit connected to this becomes unstable.
As a means for suppressing such potential fluctuations of adjacent input terminals, first and second conductivity type separation layers are formed on the surface layer of the p-type semiconductor substrate sandwiched between the vertical diodes. Patent Document 1 discloses a method of drawing out current flowing into an adjacent vertical diode in the second conductivity type separation layer when a forward current flows through the vertical diode by connecting these separation layers to the ground. (FIG. 11).
In addition, a floating electrode is formed on the surface of the first conductive type and second conductive type separation layer between the vertical diodes, and a current drawn to the second conductive type separation layer is connected to the ground through the floating electrode. Patent Document 2 discloses a method of flowing in the flow (FIG. 12).
JP 2005-327964 A JP 2005-317630 A

The method disclosed in Patent Documents 1 and 2 is to draw out a sneak current to an adjacent vertical diode when a forward current flows through the vertical diode through an n-type separation layer 5 formed between the diodes. By drawing out the sneak current through the isolation layer 5, the operation of the parasitic npn transistor formed between the adjacent vertical diodes is prevented, and the potential fluctuation of the adjacent input terminal is suppressed.
However, in this method, the current drawing effect greatly depends on the depth of the n-type isolation layer 5. When the n-type isolation layer 5 is formed deeply, the current extraction effect is increased and the sneak current to the adjacent vertical diode is reduced, so that the potential fluctuation of the adjacent input terminal is suppressed.
However, since the formation of the deep n-type isolation layer 5 also increases lateral diffusion, the width of the n-type isolation layer increases, and as a result, the p-type isolation layer 6 located between adjacent vertical diodes. It is necessary to increase the width of the separation layer including the n-type separation layer 5 and the n-type separation layer 5. As the number of input terminals increases, the area occupied by the separation layer increases, and the area occupied by the separation layer with respect to the chip area increases.
The object of the present invention is to solve the above-mentioned problem, and even when a negative excessive surge voltage is applied to the input terminal and a forward current flows through the vertical diode of the surge protection element, the potential of the adjacent input terminal An object of the present invention is to provide a semiconductor device that can suppress fluctuations, ensure a stable operation of a control circuit, and reduce the occupation area of a separation layer between vertical diodes with respect to a chip area.

  It is another object of the present invention to provide a semiconductor device with a high ESD tolerance that does not break down the element even when a large positive voltage such as ESD is applied.

To achieve the above object, in a semiconductor device having a semiconductor element formed in a semiconductor layer, a control circuit that controls the semiconductor element, and a plurality of vertical pn junction diodes that are surge protection elements,
A plurality of second conductivity type first diffusion layers (cathode layers) formed apart from the surface layer of the first conductivity type semiconductor layer and the adjacent first diffusion layers; A trench groove formed in the semiconductor layer apart from one diffusion layer, and a first conductivity formed in a surface layer of the semiconductor layer between the trench groove and the first diffusion layer in contact with a sidewall of the trench groove A second diffusion layer (separation layer) of the mold, a third diffusion layer (separation layer) of the second conductivity type formed at the bottom of the trench groove, and a conductor filling the trench groove; A first metal electrode formed on the first diffusion layer; a second metal electrode formed on the conductor and on the second diffusion layer; and a back electrode formed on the back side of the semiconductor layer; Semiconductor device in which the vertical pn junction diode is configured by the semiconductor layer and the first diffusion layer There are, a structure in which the second metal electrode is connected to the ground.
Further, in a semiconductor device having a semiconductor element formed in a semiconductor layer, a control circuit that controls the semiconductor element, and a plurality of vertical pn junction diodes that are surge protection elements,
A plurality of second conductivity type first diffusion layers (cathode layers) formed apart from the surface layer of the first conductivity type semiconductor layer and the adjacent first diffusion layers; A trench groove formed in the semiconductor layer apart from one diffusion layer, and a first conductivity formed in a surface layer of the semiconductor layer between the trench groove and the first diffusion layer in contact with a sidewall of the trench groove A second diffusion layer (separation layer) of the mold, a third diffusion layer (separation layer) of the second conductivity type formed at the bottom of the trench groove, and a conductor filling the trench groove; A first metal electrode formed on the first diffusion layer; a second metal electrode formed on the conductor and on the second diffusion layer; and a back electrode formed on the back side of the semiconductor layer; Semiconductor device in which the vertical pn junction diode is configured by the semiconductor layer and the first diffusion layer There are, a configuration wherein the second metal electrode is a floating electrode.

The tip of the bottom of the third diffusion layer may be deeper than the diffusion depth of the second diffusion layer.
Further, a semiconductor substrate having a first conductivity type higher than the impurity concentration of the first semiconductor layer is disposed between the back surface side of the semiconductor layer and the back electrode, in contact with each of them.
The second semiconductor layer and the third semiconductor layer are in contact with the semiconductor substrate.
The second diffusion layer is composed of two or more layers having different diffusion depths.
The second diffusion layer having the deepest diffusion depth may be in contact with the semiconductor substrate.

According to the present invention, even when an excessive negative surge voltage is applied to the vertical protection diode used for surge protection of the control circuit and an excessive forward current flows, the adjacent vertical protection diode is protected. Stable operation of the control circuit can be ensured by suppressing the operation of the parasitic npn transistor formed between the diode and stabilizing the potential of the adjacent input terminal.
Moreover, the area occupied by the isolation layer between the protective diodes can be reduced by combining the trench groove and the isolation layer.
Also, by forming the first conductivity type (p-type) separation layer with a shallow diffusion layer and a deep layer, it is possible to suppress potential fluctuations of adjacent input terminals when a negative surge voltage is applied. In addition, the positive surge resistance can be improved.

  Embodiments of the invention will be described in the following examples. The same parts as those described in the drawings of the prior art are denoted by the same reference numerals. In addition, here, the first conductivity type is p-type and the second conductivity type is n-type, but it is also possible to reverse them.

FIG. 1 is a cross-sectional view of a main part of a semiconductor device according to a first embodiment of the present invention. An n-type diffusion layer 3 is formed on the surface layer of the p-type semiconductor layer 1, a metal electrode 8 is formed on the surface, and a back electrode 11 that is a common electrode is formed on the back surface. A vertical diode for surge protection is formed by pn junction diodes of the n-type diffusion layer 3 (cathode region) and the p-type semiconductor layer 1 (anode region).
Further, an n-type diffusion layer 4 is formed adjacent to the n-type diffusion layer 3 apart from the n-type diffusion layer 3, a metal electrode 9 is formed on the surface, and a vertical diode as a surge protection element is adjacent to the n-type diffusion layer 3. Form. A trench groove 20 is formed in the p semiconductor layer 1 between the two vertical diodes. The n-type isolation layer 5 is formed at the bottom of the trench groove 20, and the p-type isolation layer 6 is formed on the surface layer of the p-type semiconductor layer 1 on both sides of the trench groove 20.
The insulating film 15 is formed on the side wall of the trench groove 20, the inside of the trench groove 20 is filled with the conductor 16, and the metal electrode 10 is formed on the upper end thereof. The metal electrode 10 is electrically connected to the n-type separation layer 5 and further connected to the p-type separation layer 6. The metal electrode 10 is connected to the ground GND.
Note that the insulating film 15 on the side wall of the trench groove 20 is not necessarily formed. The metal electrode 8 and the metal electrode 9 are input terminals IN formed by bonding pads, and input signals of independent control circuits are inputted to the respective input terminals IN. In the figure, the metal electrodes 8 and 9 and the input terminal IN are drawn individually for convenience.

Further, a control circuit or a power semiconductor element formed on the same semiconductor substrate is connected to the metal electrode 8 and the metal electrode 9 by a metal wiring, and at that time, it is also connected to the high potential side terminal Vcc through a pull-up resistor or the like. Further, the back electrode 11 and the metal electrode 10 are connected to GND.
A positive voltage is normally applied from the Vcc through the pull-up resistor 12 to the metal electrode 8 which is the cathode electrode of the vertical diode, and the vertical diode is in a reverse bias state and no forward current flows.
However, when a negative voltage is applied due to a surge or the like, the vertical diode is in a forward bias state and a forward current flows. At this time, most of the electrons injected from the n-type diffusion layer 3 into the p-type semiconductor layer 1 are recombined in the p-type substrate 1, but some of the electrons spread in the lateral direction and enter the adjacent n-type separation layer 5. As a result, a parasitic npn transistor including the n-type diffusion layer 3 / p-type semiconductor layer 1 / n-type isolation layer 5 operates, and electrons flowing in the n-type isolation layer 5 pass through the electrode 16 formed in the trench groove. And flows to the surface metal electrode 10.
More specifically, when some of the electrons spread and flow in the p-type semiconductor layer 1, holes also spread and flow in the p-type semiconductor layer 1 so as to neutralize the electrons. This hole flow becomes the base current of the parasitic npn transistor, and a large current flows from the collector (n-type isolation layer 5) of the parasitic npn transistor through the base (p-type semiconductor layer 1) to the emitter (n-type diffusion layer 4). .

In this way, when a negative surge voltage is applied to the vertical diode, the parasitic npn transistor composed of the n-type diffusion layer 3 / p-type semiconductor layer 1 / n-type separation layer 5 operates, so that the two vertical diodes are connected. The operation of the parasitic npn transistor formed of n-type diffusion layer 3 / p-type semiconductor layer 1 / n-type diffusion layer 4 can be suppressed. By suppressing the operation of the parasitic npn transistor, the potential fluctuation of the metal electrode 9 (adjacent input terminal IN) formed in the n-type diffusion layer 4 is suppressed, and the operation of the control circuit connected thereto is stabilized. Can do.
The n-type isolation layer 5 is preferably formed deep in consideration of the electron extraction efficiency. By forming it at the bottom of the trench groove 20, the n-type isolation layer 5 is formed at a deep position in the p-type semiconductor layer 1 with a minimum width. 5 can be formed, the area occupied by the separation layer between the vertical diodes (a region obtained by combining the surface width of the p-type separation layer 6 and the width of the opening of the trench 20) can be made smaller than that of the conventional structure. .

FIG. 2 is a fragmentary cross-sectional view of a semiconductor device according to a second embodiment of the present invention. The difference from the first embodiment is that the p-type semiconductor layer 1 is formed on a high-concentration p-type semiconductor substrate 2. Usually, the p-type semiconductor layer 1 is an epitaxial growth layer formed on the p-type semiconductor substrate 2.
In this case, the same effect as that of the first embodiment can be obtained with respect to the potential fluctuation of the adjacent input terminal IN. Further, the area occupied by the separation layer between the vertical diodes (a region obtained by combining the width of the surface of the p-type separation layer 6 and the width of the opening of the trench 20) is the same as in the first embodiment. Further, in this case, the operating resistance of the vertical diode can be made smaller than that of the vertical diode of the first embodiment, and the surge current when a positive surge voltage is applied can be increased, so that the positive surge resistance is improved. be able to.

FIG. 3 is a cross-sectional view of a principal part of the semiconductor device according to the third embodiment of the present invention. The difference from the first and second embodiments is that the metal electrode 10 formed on the surface of the separation region is a floating metal electrode that is not connected to any electrode on the surface.
Even in such a case, the parasitic npn transistor composed of the n-type diffusion layer 3 / p-type semiconductor layer 1 / n-type isolation layer 5 is operated to change the potential of the adjacent n-type diffusion layer 4 (metal electrode 9). Is the same as in the second embodiment in that stable circuit operation can be secured. However, since the wiring for connecting the metal electrode 10 to the ground becomes unnecessary, the chip can be reduced by reducing the wiring area as compared with the second embodiment.
In FIG. 3, the electrons extracted to the n-type separation layer 5 pass through the conductor 16 and are carrier-converted by the metal electrode 10, and from the back electrode 11 to the p-type semiconductor substrate 2, the p-type semiconductor layer 1, and the p diffusion layer 6. Recombines with holes flowing through the surface to the metal electrode 10 on the surface.

FIG. 4 is a cross-sectional view of a main part of a semiconductor device according to a fourth embodiment of the present invention. This structure is almost the same as that of the third embodiment. However, in the third embodiment, the p-type isolation layer 6 is formed on both sides after the trench groove 20 is formed, or two p-type isolation layers 6 are formed apart and then the trench groove 20 is formed therebetween. On the other hand, in this embodiment, after one p-type isolation layer 6 is formed, a trench groove 20 is formed so as to divide the p-type isolation layer 6 in the center of the p-type isolation layer 6. In the case of the present embodiment, the area of the location where the trench groove 20 is formed can be used as a mask opening when forming the p-type isolation layer 6, and therefore the width of the p-type isolation layer 6 located on both sides of the trench groove 20. Can be made smaller than in the third embodiment. As a result, the chip can be reduced.
Further, the same effect as that of the third embodiment can be obtained with respect to the potential fluctuation of the adjacent input terminal IN. The same effect can be obtained when the metal electrode 10 is connected to the ground GND.
FIG. 5 is a process diagram showing a method of manufacturing the semiconductor device of FIG. 4, and FIG. 5A to FIG.
A p-type semiconductor layer 1 is formed by epitaxial growth or the like on a p-type semiconductor substrate 2 having a high impurity concentration, and n-type diffusion layers 3 and 4 in contact with the p-type semiconductor substrate 2 are formed on the p-type semiconductor layer 1. A p-type separation layer 6 is formed on the surface layer of the p-type semiconductor layer 1 sandwiched between the diffusion layers 3 and 4 (FIG. 1A).

Next, a trench groove 20 that penetrates the p-type isolation layer 6 from the surface of the p-type isolation layer 6 and reaches the p-type semiconductor layer 1 is formed, and an n-type isolation layer 5 is formed at the bottom of the trench groove 20 (see FIG. (B)).
Next, an insulating film 14 (selective oxide film) is formed on a part of the n-type semiconductor layers 3 and 4, a part of the p-type isolation layer 6, and the p-type semiconductor layer 1 sandwiched between these layers, An insulating film 15 is formed on the side wall of the trench groove 20, and a conductor 16 electrically connected to the n-type isolation layer 5 is filled in the trench groove 20 ((c) in the figure).
Next, the metal electrode 10 connected to the conductor 16 and the p-type separation layer 6 is formed.

FIG. 6 is a cross-sectional view of the principal part of the semiconductor device according to the fifth embodiment of the present invention. The difference from the fourth embodiment is that the diffusion depth of the n-type isolation layer 5 is increased and the n-type isolation layer 5 is in contact with the high-concentration p-type semiconductor substrate 2. In this case, since the n-type isolation layer 5 is deeper than in the fourth embodiment, the operation of the parasitic npn transistor formed by the n-type diffusion layer 3 / p-type semiconductor layer 1 / n-type diffusion layer 4 is the fourth embodiment. It can be suppressed more than the case of.
Although not shown, the same effect can be obtained by connecting the metal electrode 10 to the ground GND.

FIG. 7 is a fragmentary cross-sectional view of the semiconductor device according to the sixth embodiment of the present invention. The difference from the fourth embodiment is that the n-type isolation layer 5 and the p-type isolation layer 6 are in contact with the high-concentration p-type semiconductor substrate 2. With this structure, the function of the parasitic npn transistor formed by the n-type diffusion layer 3 / p-type isolation layer 5 / n-type isolation layer 5 is weakened by the interposition of the p-type isolation layer 6, and the potential of the adjacent input terminal IN is reduced. Although the fluctuation is larger than that of the fourth embodiment, the potential fluctuation is smaller than that of the conventional structure. Further, the same effect can be obtained even when the metal electrode 10 is connected to the ground GND.
In forming the p-type diffusion layer 7, as in the n-type diffusion layer 5, a trench groove having the same shape as the trench groove 20 is formed in the semiconductor layer 1 at a distance from the trench groove 20. After forming the insulating film on the side wall, a p-type diffusion layer may be formed at the bottom of the trench groove. In this case, the trench is filled with a conductor and electrically connected to the conductor 16.
In the first to sixth embodiments, it has been described how to suppress the potential fluctuation of the adjacent input terminal IN when a large negative voltage is applied due to a surge or the like. When a large positive voltage such as ESD is applied, if the function of the parasitic npn transistor composed of the n-type diffusion layer 3, the p-type semiconductor layer 1, and the n-type isolation layer 5 is large, the ESD tolerance is reduced. . For this reason, the ESD tolerance of the sixth embodiment is larger than that of the first to fifth embodiments.

  Next, a structure capable of suppressing the potential fluctuation of the adjacent input terminal IN when a negative surge voltage is applied and improving the ESD tolerance when a large positive voltage due to ESD is applied will be described.

8 to 10 are main part configuration diagrams of a semiconductor device according to a seventh embodiment of the present invention. FIG. 8 is a plan view, FIG. 9 is a cross-sectional view taken along line AA in FIG. It is sectional drawing cut | disconnected by the BB line of FIG. A significant difference from the first to sixth embodiments is that shallow p-type isolation layers 6 and deep p-type isolation layers 7 are alternately formed between vertical diodes.
By forming the p-type isolation layers 6 and 7 having different depths between the vertical diodes, potential fluctuations of adjacent input terminals can be suppressed, and the ESD tolerance can be improved.
Even when a large positive voltage due to ESD or the like is applied to the vertical diode and electrons are injected from the n-type isolation layer 5 by the avalanche current, the p-type isolation is formed at the location where the p-type isolation layer 7 having a deep diffusion depth is formed. Electron injection from the n-type isolation layer 5 to the p-type semiconductor layer 1 is suppressed by the potential barrier of the layer 7.
Therefore, the function of the parasitic npn transistor composed of the n-type isolation layer 5 / p-type semiconductor layer 1 / n-type diffusion layer 3 is suppressed, and the ESD tolerance can be improved as compared with the first to fifth embodiments. .
On the other hand, when a negative surge voltage is input, a parasitic npn composed of the n-type diffusion layer 3 / p-type semiconductor layer 1 / n-type separation layer 5 at the portion where the p-type separation layer 6 having a shallow diffusion depth is formed. Since the transistor works and electrons can be extracted from the n-type diffusion layer 5, the voltage fluctuation of the adjacent input terminal IN can be suppressed to the same extent as in the first to fifth embodiments.

Sectional drawing of the principal part of the semiconductor device of 1st Example of this invention. Sectional drawing of the principal part of the semiconductor device of 2nd Example of this invention Sectional drawing of the principal part of the semiconductor device of 1st Example of this invention. Sectional drawing of the principal part of the semiconductor device of 4th Example of this invention FIGS. 5A to 5D are process diagrams illustrating a method for manufacturing the semiconductor device of FIG. 4, and FIGS. Sectional drawing of the principal part of the semiconductor device of 5th Example of this invention. Sectional drawing of the principal part of the semiconductor device of 6th Example of this invention The principal part top view of the semiconductor device of 7th Example of this invention Sectional view cut along line AA in FIG. Sectional view cut along line BB in FIG. The figure in the case where the metal electrode 10 is connected to the ground in the cross-sectional view of the main part of the conventional semiconductor device The figure when metal electrode 10 turns into a floating electrode in the principal part sectional view of the conventional semiconductor device.

Explanation of symbols

1 p-type semiconductor layer 2 p-type semiconductor substrate 3, 4 n-type diffusion layer 5 n-type separation layer 6 p-type separation layer 7 p-type separation layer (diffusion depth is deep)
8, 9, 10 Metal electrode 11 Back electrode 12 Pull-up resistor 14, 15, Insulating film 16 Conductor 20 Trench groove Vcc Power supply high potential side terminal / Voltage IN Input terminal GND Ground

Claims (7)

In a semiconductor device having a semiconductor element formed in a semiconductor layer, a control circuit that controls the semiconductor element, and a plurality of vertical pn junction diodes that are surge protection elements,
The plurality of second conductivity type first diffusion layers formed apart from the surface layer of the first conductivity type semiconductor layer and the adjacent first diffusion layers are separated from the first diffusion layer. A trench groove formed in the semiconductor layer, and a second diffusion layer of a first conductivity type formed on a surface layer of the semiconductor layer between the trench groove and the first diffusion layer in contact with a sidewall of the trench groove A third diffusion layer of the second conductivity type formed at the bottom of the trench groove, a conductor filling the trench groove, a first metal electrode formed on the first diffusion layer, and the conductive layer A second metal electrode formed on the body and on the second diffusion layer; and a back electrode formed on a back surface side of the semiconductor layer, wherein the vertical pn junction is formed by the semiconductor layer and the first diffusion layer. A semiconductor device constituting a diode, wherein the second metal electrode is connected to a ground. The semiconductor device according to. In a semiconductor device having a semiconductor element formed in a semiconductor layer, a control circuit that controls the semiconductor element, and a plurality of vertical pn junction diodes that are surge protection elements,
The plurality of second conductivity type first diffusion layers formed apart from the surface layer of the first conductivity type semiconductor layer and the adjacent first diffusion layers are separated from the first diffusion layer. A trench groove formed in the semiconductor layer, and a second diffusion layer of a first conductivity type formed on a surface layer of the semiconductor layer between the trench groove and the first diffusion layer in contact with a sidewall of the trench groove A third diffusion layer of the second conductivity type formed at the bottom of the trench groove, a conductor filling the trench groove, a first metal electrode formed on the first diffusion layer, and the conductive layer A second metal electrode formed on the body and on the second diffusion layer; and a back electrode formed on a back surface side of the semiconductor layer, wherein the vertical pn junction is formed by the semiconductor layer and the first diffusion layer. A semiconductor device constituting a diode, wherein the second metal electrode is a floating electrode. That the semiconductor device. The semiconductor device according to claim 1, wherein a tip of the bottom of the third diffusion layer is deeper than a diffusion depth of the second diffusion layer. 3. The semiconductor substrate according to claim 1, wherein a first conductivity type semiconductor substrate having a higher impurity concentration than that of the first semiconductor layer is disposed between the back surface side of the semiconductor layer and the back electrode. Semiconductor device. The semiconductor device according to claim 4, wherein the second semiconductor layer and the third semiconductor layer are in contact with the semiconductor substrate. The semiconductor device according to any one of claims 1 to 5, wherein the second diffusion layer includes two or more layers having different diffusion depths. The semiconductor device according to claim 6, wherein the second diffusion layer having the deepest diffusion depth is in contact with the semiconductor substrate.

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