JPH0130308B2 - - Google Patents
Info
- Publication number
- JPH0130308B2 JPH0130308B2 JP56033419A JP3341981A JPH0130308B2 JP H0130308 B2 JPH0130308 B2 JP H0130308B2 JP 56033419 A JP56033419 A JP 56033419A JP 3341981 A JP3341981 A JP 3341981A JP H0130308 B2 JPH0130308 B2 JP H0130308B2
- Authority
- JP
- Japan
- Prior art keywords
- collector
- region
- transistor
- base
- impurity concentration
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 claims description 22
- 239000012535 impurity Substances 0.000 claims description 19
- 239000002131 composite material Substances 0.000 claims description 8
- 238000010586 diagram Methods 0.000 description 6
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Bipolar Transistors (AREA)
- Element Separation (AREA)
- Bipolar Integrated Circuits (AREA)
Description
【発明の詳細な説明】
本発明はコレクタが低濃度の不純物で形成され
た複合半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a composite semiconductor device in which a collector is formed of impurities at a low concentration.
従来、特にPNP極性をもつトランジスタは、
コレクタが低濃度のＰ形不純物にて形成されてい
る。第１図はPNP形トランジスタの酸化膜と界
面との関係を示す図であり、低濃度のＰ形不純物
で形成されたコレクタ領域１上の酸化膜２の汚染
物質などの正電荷により、等価的にコレクタ領域
１の酸化膜２との界面近傍部３がＮ形に反転する
ことは周知の通りである。この界面近傍部３の反
転層により、たとえばコレクタ領域１とベース領
域４との間に逆バイアス電圧を印加すると、多大
の漏洩電流が流れるので、この対策が種々提案さ
れている。 Conventionally, transistors with PNP polarity, in particular,
The collector is formed of a low concentration P type impurity. Figure 1 is a diagram showing the relationship between the oxide film and the interface of a PNP transistor. It is well known that the portion 3 of the collector region 1 near the interface with the oxide film 2 is inverted to N-type. Due to this inversion layer in the vicinity of the interface 3, when a reverse bias voltage is applied between the collector region 1 and the base region 4, a large amount of leakage current flows, so various countermeasures have been proposed.
ところで、コレクタが低濃度の不純物で形成さ
れた複合半導体装置には、たとえば、ダーリント
ン接続の半導体素子がある。このダーリントン接
続の半導体素子は通常、第２図に示すような等価
回路構成になつている。すなわち、PNP形トラ
ンジスタ２１のエミツタとPNP形トランジスタ
２２のベースとが直結され、さらにこれらトラン
ジスタ２１，２２のコレクタも直結され、トラン
ジスタ２１のベースとトランジスタ２２のベース
との間にはバイアス抵抗２３が接続され、トラン
ジスタ２２のベース・エミツタ間にもバイアス抵
抗２４が接続されている。 Incidentally, a composite semiconductor device in which the collector is formed of a low concentration impurity includes, for example, a Darlington-connected semiconductor element. This Darlington-connected semiconductor element usually has an equivalent circuit configuration as shown in FIG. That is, the emitter of the PNP transistor 21 and the base of the PNP transistor 22 are directly connected, the collectors of these transistors 21 and 22 are also directly connected, and a bias resistor 23 is connected between the base of the transistor 21 and the base of the transistor 22. A bias resistor 24 is also connected between the base and emitter of the transistor 22.
このようなダーリントン接続をもつ半導体素子
の構造を第３図に示す。すなわち、トランジスタ
２１およびトランジスタ２２の間に接続されてい
るバイアス抵抗２３は両トランジスタ２１，２２
間に配置されている。なお、図中の斜線部分は電
極を示しており、３１はトランジスタ２１のベー
ス電極、３２はエミツタ電極、３３はトランジス
タ２２のベース電極、３４はエミツタ電極であ
る。 The structure of a semiconductor element having such a Darlington connection is shown in FIG. That is, the bias resistor 23 connected between the transistor 21 and the transistor 22
placed in between. Note that the hatched portions in the figure indicate electrodes; 31 is the base electrode of the transistor 21, 32 is the emitter electrode, 33 is the base electrode of the transistor 22, and 34 is the emitter electrode.
このように構成されるダーリントン接続の半導
体素子では、低濃度の不純物でＰ形のコレクタが
形成されているため、第１図に示したコレクタ領
域１の界面近傍部３に発生する反転層が第２図の
ダーリントン接続の半導体素子のＰ形コレクタ２
９にも発生し、このコレクタ２９のＮ形反転層の
影響を受け、ダーリントン接続ではコレクタ電流
（IC）に対するコレクタ・エミツタ間電圧の特性
は第４図に示す静特性となる。すなわち、コレク
タ領域に反転層を有するトランジスタでダーリン
トン接続の半導体素子を構成した場合には、コレ
クタ電流の小電流領域においてコレクタ飽和電圧
（VCE）が高くなるのである。この現象は、トラ
ンジスタ２２のベースに注入される電流（IB）は
コレクタ反転層のリーク電流を打消す分だけ余剰
に注入する必要があり、その分だけベース・エミ
ツタ間電圧（VBE）のバイアス電流が余剰に必要
となるため、見かけ上のコレクタ・エミツタ間電
圧が高くなることによるものと思われる。 In the Darlington-connected semiconductor element constructed in this way, a P-type collector is formed with impurities at a low concentration, so the inversion layer generated near the interface 3 of the collector region 1 shown in FIG. P-type collector 2 of the semiconductor device with Darlington connection in Figure 2
Under the influence of the N-type inversion layer of the collector 29, the characteristic of the collector-emitter voltage with respect to the collector current (I C ) in the Darlington connection becomes the static characteristic shown in FIG. 4. That is, when a Darlington-connected semiconductor element is configured with a transistor having an inversion layer in the collector region, the collector saturation voltage (V CE ) becomes high in a small collector current region. This phenomenon occurs because the current (I B ) injected into the base of the transistor 22 needs to be injected in excess to cancel out the leakage current in the collector inversion layer, and the base-emitter voltage (V BE ) increases accordingly. This is thought to be due to the apparent collector-emitter voltage becoming higher because an extra bias current is required.
本発明は上記事情に鑑みてなされたもので、そ
の目的とするところは、コレクタ領域の反転層の
影響を極少におさえて、このコレクタ小電流領域
のコレクタ・エミツタ飽和電圧の特性改善を図
り、常に正常な特性を得ることができる複合半導
体装置を提供することにある。 The present invention has been made in view of the above circumstances, and its purpose is to minimize the influence of the inversion layer in the collector region and improve the characteristics of the collector-emitter saturation voltage in this collector small current region. An object of the present invention is to provide a composite semiconductor device that can always obtain normal characteristics.
以下、本発明の一実施例について図面を参照し
て説明する。なおこの実施例は、第２図に示す等
価回路のダーリントン接続をもつ半導体素子に適
用した場合である。また、第２図および第３図と
同一部分には同一符号を付してある。 An embodiment of the present invention will be described below with reference to the drawings. Note that this embodiment is applied to a semiconductor element having a Darlington connection in the equivalent circuit shown in FIG. Further, the same parts as in FIGS. 2 and 3 are given the same reference numerals.
第５図Ａ，Ｂにおいて、トランジスタ２１，２
２のコレクタ２９を半導体基板に形成し、このコ
レクタ２９の領域にトランジスタ２１，２２のベ
ース２５，２７およびエミツタ２６，２８をそれ
ぞれ離隔して形成し、これらの間にトランジスタ
２１，２２のベースと同一伝導性を持ち同時に拡
散したバイアス抵抗２３をそれぞれ形成し、トラ
ンジスタ２１，２２のベース電極を接続状態に形
成する。そして、これら機能素子であるトランジ
スタ２１，２２およびバイアス抵抗２３のそれぞ
れを囲繞するように高濃度不純物で形成した壁５
１を形成する。この壁５１は、コレクタ２９と同
形のＰ形不純物、たとえばボロンを含ませて、コ
レクタ２９の不純物濃度よりもはるかに高い濃度
に形成する。この実施例では、たとえば1.5×
1020個／c.c.のボロン不純物濃度を拡散により形成
している。 In FIGS. 5A and 5B, transistors 21 and 2
2 collector 29 is formed on a semiconductor substrate, bases 25, 27 and emitters 26, 28 of transistors 21, 22 are formed spaced apart from each other in the region of this collector 29, and the bases of transistors 21, 22 and emitters 26, 28 are formed between these. Bias resistors 23 having the same conductivity and simultaneously diffused are formed, respectively, and the base electrodes of the transistors 21 and 22 are formed in a connected state. A wall 5 formed of highly concentrated impurities surrounds each of the transistors 21 and 22 and the bias resistor 23, which are these functional elements.
Form 1. This wall 51 contains a P-type impurity having the same shape as the collector 29, for example, boron, and is formed to have a much higher impurity concentration than the collector 29. In this example, for example 1.5×
A boron impurity concentration of 10 to 20 particles/cc is formed by diffusion.
このように壁５１を各素子を囲繞するように形
成することによつて、トランジスタ２１，２２お
よびバイアス抵抗２３のコレクタ側に対する反転
層の発生を停止させることができる。したがつ
て、ダーリントン接続をもつ半導体素子の静特性
は、第６図に示すようにコレクタ電流の小電流領
域でのコレクタ飽和電圧が高くなるのを防止で
き、常に正常な特性を得ることができる。 By forming the wall 51 so as to surround each element in this manner, the generation of an inversion layer on the collector side of the transistors 21 and 22 and the bias resistor 23 can be stopped. Therefore, the static characteristics of a semiconductor element with Darlington connection can prevent the collector saturation voltage from increasing in the small collector current region, as shown in Figure 6, and can always maintain normal characteristics. .
なお前記壁５１の形成は、トランジスタ２１，
２２のエミツタ２６，２８を形成するとき同時に
同じＰ形の不純物ボロンの拡散を行つて形成でき
るが、勿論エミツタ２６，２８の不純物濃度と異
なる不純物濃度に形成してもよい。要するに、コ
レクタ２９の不純物濃度より高濃度であれば良
い。 Note that the formation of the wall 51 involves the formation of the transistors 21,
When forming the 22 emitters 26 and 28, they can be formed by simultaneously diffusing the same P type impurity boron, but of course they may be formed to have an impurity concentration different from that of the emitters 26 and 28. In short, the impurity concentration may be higher than that of the collector 29.
また前記実施例では、PNP形トランジスタを
用いた場合について説明したが、NPN形トラン
ジスタを用いても同様の効果が得られる。この
NPN形の場合は、壁の不純物濃度が１×1022
個／c.c.以下である。さらに、ダーリントン接続の
半導体素子に適用した場合について説明したが、
コレクタが低不純物濃度で形成したトランジスタ
を複数接続した複合半導体装置であれば何れにも
適用できる。また、壁５１の形成を拡散によつて
行つたが、イオン注入により形成してもよいし、
エピタキシヤル技術により形成してもよい。 Further, in the above embodiment, a case was explained in which a PNP type transistor was used, but the same effect can be obtained even if an NPN type transistor is used. this
In the case of NPN type, the impurity concentration of the wall is 1×10 22
pcs/cc or less. Furthermore, we have explained the case where it is applied to semiconductor elements with Darlington connection.
The invention can be applied to any composite semiconductor device in which a plurality of transistors whose collectors are formed with low impurity concentration are connected. Further, although the wall 51 was formed by diffusion, it may also be formed by ion implantation.
It may also be formed by epitaxial technology.
以上説明したように本発明によれば、コレクタ
が低不純物濃度のトランジスタでコレクタに反転
層の形成される場合でも、このトランジスタを囲
繞するようにコレクタより高濃度な壁を形成する
ことによつて、反転層の発生を防止でき、よつて
コレクタ小電流領域のコレクタ・エミツタ飽和電
圧の特性改善が図れ、常に正常な特性が得られる
複合半導体装置を提供できる。 As explained above, according to the present invention, even when the collector is a transistor with a low impurity concentration and an inversion layer is formed on the collector, by forming a wall with a higher concentration than the collector so as to surround this transistor, It is possible to prevent the generation of an inversion layer, thereby improving the characteristics of the collector-emitter saturation voltage in the collector small current region, and to provide a composite semiconductor device in which normal characteristics can always be obtained.
第１図は不純物濃度のコレクタをもつトランジ
スタの反転層の発生状態説明図、第２図はダーリ
ントン接続をもつ半導体素子の等価回路図、第３
図Ａ，Ｂは第２図の半導体素子の構造図を示し、
Ａ図は平面図、Ｂ図はＡ図におけるＡ−A′線に
沿う断面図、第４図は第３図の半導体素子のコレ
クタ電流に対するコレクタ・エミツタ間飽和電圧
の特性曲線図、第５図Ａ，Ｂは本発明の一実施例
を示し、Ａ図は平面図、Ｂ図はＡ図におけるＢ−
B′線に沿う断面図、第６図は同実施例における
半導体素子のコレクタ電流に対するコレクタ・エ
ミツタ間飽和電圧の特性曲線図である。
２１，２２……PNP形トランジスタ、２３，
２４……バイアス抵抗、２５，２７……ベース、
２６，２８……エミツタ、２９……コレクタ、３
１，３３……ベース電極、３２，３４……エミツ
タ電極、５１……壁。
Figure 1 is an explanatory diagram of the occurrence of an inversion layer in a transistor with a collector having an impurity concentration, Figure 2 is an equivalent circuit diagram of a semiconductor element with Darlington connection, and Figure 3
Figures A and B show structural diagrams of the semiconductor element in Figure 2,
Figure A is a plan view, Figure B is a cross-sectional view taken along line A-A' in Figure A, Figure 4 is a characteristic curve diagram of the collector-emitter saturation voltage with respect to the collector current of the semiconductor element in Figure 3, and Figure 5. A and B show one embodiment of the present invention, where A is a plan view and B is a B- in A.
FIG. 6, a sectional view taken along line B', is a characteristic curve diagram of the collector-emitter saturation voltage with respect to the collector current of the semiconductor element in the same embodiment. 21, 22...PNP type transistor, 23,
24...Bias resistance, 25, 27...Base,
26, 28... Emitsuta, 29... Collector, 3
1, 33... Base electrode, 32, 34... Emitter electrode, 51... Wall.
Claims (1)
ス領域が形成され、ダーリントン接続された第１
および第２のトランジスタと、前記両ベース領域
とは独立してその両ベース領域の対向した辺それ
ぞれに対して長手方向が平行するような配置状態
で両ベース領域間に介在されるように前記コレク
タ領域内に形成されると共に、電極配線を介して
前記ベース領域間を接続するバイアス抵抗領域
と、前記各ベース領域およびバイアス抵抗領域を
それぞれ囲繞するように設けられ、前記コレクタ
領域と同一導電型でその不純物濃度より高濃度の
壁とを具備することを特徴とする複合半導体装
置。 ２ 前記壁の不純物濃度は１×1022個／c.c.以下で
ある特許請求の範囲第１項記載の複合半導体装
置。[Claims] 1. Each base region is formed in a collector region with a low impurity concentration, and the first base region is Darlington-connected.
and a second transistor, the collector being interposed between both base regions in a state where the longitudinal direction is parallel to each of the opposite sides of the both base regions, independently of the both base regions. a bias resistance region formed within the region and connecting the base regions via electrode wiring; What is claimed is: 1. A composite semiconductor device comprising a wall with a higher impurity concentration than that of the composite semiconductor device. 2. The composite semiconductor device according to claim 1, wherein the impurity concentration of the wall is 1×10 22 impurities/cc or less.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56033419A JPS57148369A (en) | 1981-03-09 | 1981-03-09 | Composite semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56033419A JPS57148369A (en) | 1981-03-09 | 1981-03-09 | Composite semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS57148369A JPS57148369A (en) | 1982-09-13 |
| JPH0130308B2 true JPH0130308B2 (en) | 1989-06-19 |
Family
ID=12386043
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56033419A Granted JPS57148369A (en) | 1981-03-09 | 1981-03-09 | Composite semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57148369A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0715134Y2 (en) * | 1983-09-21 | 1995-04-10 | 日本電気株式会社 | Semiconductor device |
| JPS61206262A (en) * | 1985-03-11 | 1986-09-12 | Shindengen Electric Mfg Co Ltd | High withstanding-voltage planar type semiconductor device |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54104779A (en) * | 1978-02-03 | 1979-08-17 | Fuji Electric Co Ltd | Semiconductor device |
| JPS54105977A (en) * | 1978-02-08 | 1979-08-20 | Hitachi Ltd | Semiconductor device |
| JPS5559768A (en) * | 1978-10-30 | 1980-05-06 | Hitachi Ltd | Darlington power transistor |
| JPS5545258B2 (en) * | 1975-05-22 | 1980-11-17 | ||
| JPS5629360A (en) * | 1979-08-17 | 1981-03-24 | Nec Corp | Composite semiconductor device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5545258U (en) * | 1978-09-19 | 1980-03-25 |
-
1981
- 1981-03-09 JP JP56033419A patent/JPS57148369A/en active Granted
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5545258B2 (en) * | 1975-05-22 | 1980-11-17 | ||
| JPS54104779A (en) * | 1978-02-03 | 1979-08-17 | Fuji Electric Co Ltd | Semiconductor device |
| JPS54105977A (en) * | 1978-02-08 | 1979-08-20 | Hitachi Ltd | Semiconductor device |
| JPS5559768A (en) * | 1978-10-30 | 1980-05-06 | Hitachi Ltd | Darlington power transistor |
| JPS5629360A (en) * | 1979-08-17 | 1981-03-24 | Nec Corp | Composite semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS57148369A (en) | 1982-09-13 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPH0550852B2 (en) | ||
| GB1533156A (en) | Semiconductor integrated circuits | |
| JPH0130308B2 (en) | ||
| JPS6217387B2 (en) | ||
| JPS6133261B2 (en) | ||
| US4160990A (en) | Semiconductor devices and circuit arrangements including such devices | |
| JPH0222405B2 (en) | ||
| JP3193368B2 (en) | Integrated circuit input terminal protection circuit | |
| JPS6211787B2 (en) | ||
| JPH0715134Y2 (en) | Semiconductor device | |
| JPS5916414B2 (en) | semiconductor equipment | |
| JP2501556B2 (en) | Optical sensor and manufacturing method thereof | |
| JPH05864B2 (en) | ||
| JPS6030106B2 (en) | complementary integrated circuit | |
| JPH02114645A (en) | Bipolar transistor | |
| JPS63107162A (en) | Vertical type pnp transistor | |
| JPS601843A (en) | Semiconductor integrated circuit | |
| JPS6116569A (en) | Semiconductor integrated circuit device | |
| JPH0157505B2 (en) | ||
| JPS6140062A (en) | Semiconductor device | |
| JPH0249032B2 (en) | ||
| JPS6225264B2 (en) | ||
| JPS59127865A (en) | Semiconductor device | |
| JPS5950108B2 (en) | transistor | |
| JPS6239546B2 (en) |