JPH0464184B2 - - Google Patents

Description

[Detailed Description of the Invention] (a) Industrial Application Field The present invention relates to a semiconductor injection integrated logic circuit device (hereinafter referred to as
It is called IIL. ) regarding.

(b) Conventional technology Two transistors Q _I on one semiconductor substrate,
Generally, an IIL configured with Q _R as shown in Figure 1 has a lateral PNP transistor Q _I on the injection side and a reverse vertical NPN transistor Q _R on the output side, as shown in Figure 2. It has a structure in which it is shared with the base of a vertical NPN transistor. That is, an N ⁺ type buried layer 2 is provided on a P type silicon substrate 1, an N type epitaxial layer 3 is formed by epitaxial growth, and this epitaxial layer 3 is formed into an island shape with a P ⁺ type isolation region 4. The island region 5 is formed by separating into two parts. P-type diffusion regions 6, 7 and N-type diffusion regions 8, 9 are sequentially formed in island region 5 by impurity diffusion, and electrodes 10 to 14 are provided through electrode holes in oxide film 3a. The lateral PNP transistor functions with the P-type diffusion region 6 as an emitter (injector), the epitaxial layer (island region) 5 as a base, and the P-type diffusion region 7 as a collector, with the base grounded. On the other hand, in the reverse vertical NPN transistor, the epitaxial layer (island region) 5 serves as an emitter, the P type diffusion region 7 serves as a base, and the N type diffusion regions 8 and 9 serve as a collector.

In such an IIL, a lateral PNP transistor is used as an injector.
Since a transistor is used, only a portion of the current is injected from the injector (emitter 6) to the NPN transistor, and the majority is reactive current.
There were problems such as a small current amplification factor (h _FE ).

In order to solve the above-mentioned problems, Japanese Patent Laid-Open No. 58-213463 discloses an IIL in which a vertical PNP transistor is used as an injector to reduce the reactive current from the injector. This IIL
As shown in FIG. 3, an N + type buried layer 2 and a P ⁺ type buried layer 15 are partially formed between a P type silicon substrate 1 and an N ^type epitaxial layer 3 epitaxially grown thereon. A P + type diffusion region 17 is formed on a part of the surface of the epitaxial layer 3 via an N ⁺ type diffusion region 16 in contact with the P ^{+ type} buried layer 15.
Vertical PNP that forms and uses this as an injector
constitutes a transistor, while epitaxial layer 3
A P type base region 18 partially in contact with the P ⁺ type buried layer 15 is formed on the other surface of the P type base region 18, and an N ⁺ type diffusion region 19 serving as a collector is partially formed on the surface of this P type base region 18. This is reversed vertically.
This constitutes an NPN transistor.

However, even in the above IIL, a part of the current supplied from the injector flows as a base current and does not contribute to the logic circuit operation.

(c) Object of the Invention The present invention aims to provide an IIL that eliminates reactive current from an injector and reduces power consumption.

(d) Structure of the Invention The present invention has an N (or P type) type semiconductor region as an emitter region, and a P type provided in this emitter region.
a reverse vertical transistor having at least one N (or P) type collector region in an N (or N) type base region;
(or P) type source and drain regions, and a junction field effect transistor in which a channel region is formed, the base region and the source region are connected, the emitter region is grounded, and the drain region is connected to an injector terminal. and the collector region is connected to an output terminal to use the junction field effect transistor as an injector.

(e) Embodiment An embodiment of the present invention will be described with reference to FIGS. 4 and 5. FIG. 4 is an equivalent circuit diagram of IIL according to the present invention,
FIG. 5 is a sectional view showing the basic structure of the IIL according to the present invention.

Junction field effect transistor (hereinafter referred to as J-FET) T _I and reverse vertical type on one semiconductor substrate
The NPN transistor _TR is constructed as shown in FIG. In other words, connect the drain of J-FET (T _I ) to the injector terminal, and connect the source to the reverse vertical type.
Connect to the base of NPN transistor T _R and
It is constructed by using a FET (T _I ) as an injector and connecting the collectors C ₁ and C ₂ of a reverse vertical NPN transistor _TR to the output terminal.

The basic structure of IIL according to the present invention will be explained with reference to FIG. An N ⁺ type buried layer 22 and a P ⁺ type buried layer 2 are formed at desired locations on a P type silicon semiconductor substrate 21.
3 is formed by impurity diffusion or the like, and an N-type epitaxial layer 24 is further formed by epitaxial growth. This epitaxial layer 24 acts as a semiconductor region. Next, a P ⁺ type isolation region 25 reaching the P ⁺ type buried layer 23 from the surface of the epitaxial layer 24 and a P ⁺ type isolation region 26 separating the epitaxial layer 24 into islands are formed by diffusion. By this heat treatment, the N ⁺ type buried layer 22 and the P ⁺ type buried layer 23 are diffused in the vertical direction, and a buried layer having a predetermined width is formed. Then, the epitaxial layer 24 surrounded by the P ⁺ type buried layer 23 and the isolation region 25 is J-
This becomes the channel region 24a of the FET (T _I ). Subsequently, a P-type base region 27, which will become the base of the reverse vertical transistor _TR , is formed on the surface of the epitaxial layer 24 by base diffusion, and a J-
A P-type front gate 28 of the FET (T _I ) is formed on the surface of the epitaxial layer 24 . Thereafter, an N ⁺ type collector region 29 is formed on the surface of this base region 27 by emitter diffusion, and an N ⁺ type contact region 30 and an N ⁺ type guard ring (collar) 31 are formed on the surface of the epitaxial layer 24 which will become the emitter region.
form. At the same time, the N ⁺ type drain region 32 and source region 33 of the J-FET are
It is formed on the surface of the epitaxial layer 24 surrounded by the P ⁺ type isolation regions 25, 25 by emitter diffusion.

Thereafter, electrode holes are formed in the oxide film 34 on the surface of the epitaxial layer 24, and electrodes in ohmic contact with each region and wiring between these are formed by well-known aluminum vapor deposition or the like.

In this way, an N-channel J-FET ( _TI ) and a reverse vertical NPN transistor _TR are formed on one semiconductor substrate. The drain electrode 35 of the J-FET (T _I ) is connected to the injector terminal I, the source electrode 36 is connected to the base electrode 37 of the reverse vertical NPN transistor, and the gate is grounded via the substrate 21. FET (T _I ) is used as a gate-grounded constant current circuit. Further, the base electrode 37 of the reverse vertical NPN transistor is connected to the base terminal B, the collector electrodes 38 and 39 are connected to the output terminals C ₁ and C ₂ , and the emitter electrode 40 is connected to the ground line GND.

Therefore, J-FET used as an injector
(T _I ) operates as a gate-grounded constant current circuit whose gate is grounded via the substrate 21, so the current supplied from the injector terminal I to the drain region 32 is entirely supplied to the base region 27 via the source region 33. be done.

Therefore, all of the current supplied to the injector can be used for logic circuit operation, resulting in lower power consumption.
Furthermore, since the gate-grounded J-FET ( _TI ) is connected to the reverse vertical transistor _TR as an injector, the V _BE voltage of the reverse vertical transistor _TR is biased to the gate of the J-FET ( _TI ). , the constant current effect of the J-FET (T _I ) becomes better.

Also, the entire circumference of the reverse vertical transistor T _R is N ⁺
By surrounding it with a mold guard ring (collar) 31, the reverse direction emitter efficiency is improved and the reverse β can be made higher than that of the conventional device, so high-speed operation is possible.

(f) Effects of the invention As explained above, since the present invention uses a junction field effect transistor as an injector,
Externally supplied current can be used for logic circuit operation without loss, making it possible to reduce power consumption and increase speed of IIL. Furthermore, due to the low power consumption of the IIL, the chip temperature does not rise even if the number of elements is increased, which improves reliability in terms of characteristics.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a basic IIL, and FIGS. 2 and 3 are cross-sectional views showing the structure of a conventional IIL. FIGS. 4 and 5 show an IIL according to the present invention, with FIG. 4 being an equivalent circuit diagram and FIG. 5 being a sectional view showing the principle structure. 21... Semiconductor substrate, 22... N ⁺ type buried layer, 23... P ⁺ type buried layer, 24... Epitaxial layer, 24a... Channel region, 25...
... isolation region, 27 ... base region, 29 ... collector region, 32 ... drain region, 33 ... source region.

Claims (1)

[Claims] 1. A semiconductor substrate 21 of one conductivity type, a semiconductor region 24 of an opposite conductivity type formed on the substrate, a base region 27 of one conductivity type formed on the surface of the semiconductor region 24, a collector region 29 of opposite conductivity type formed on the surface of the base region 27; the base region 27 and the collector region 29 form a reverse vertical transistor TR using the semiconductor region 24 as an emitter; a buried layer 23 of one conductivity type formed on the surface and an isolation region 2 of one conductivity type reaching the buried layer 23 from the surface of the semiconductor region 24;
5 and the other part 24a of the semiconductor region that is electrically independent from the region that becomes the emitter, a front gate region 28 of one conductivity type formed on the surface of the other part 24a of the semiconductor region, and a source of the opposite conductivity type. - The drain regions 32, 33, the front gate region 28, and the source/drain regions form a gate-grounded type constant current operation junction, with the buried layer 23 as a back gate and the other semiconductor region 24a as a channel region. A type field effect transistor TI is formed, the base region 27 and one of the source/drain regions 32, 33 are connected, the semiconductor region 24 serving as the emitter is grounded, and the other of the source/drain regions 32, 33 is connected to the ground. A semiconductor injection integrated logic circuit device characterized by having an injector terminal.