JPH04240764A - Iil semiconductor device - Google Patents

Abstract

PURPOSE:To increase the DC current-amplification factor of an NPN transistor without changing the DC current-amplification factor of a PNP transistor by a method wherein a first N-type epitaxial layer is formed, a second N-type high-concentration epitaxial layer is formed on it and an injector region and a guard-ring region are formed in the second layer. CONSTITUTION:A first N-type epitaxial layer 4-1 is formed on a P-type semiconductor substrate 1; a second N-type high-concentration epitaxial layer 4-2 is formed on it. Then, impurities are introduced selectively from the second layer 4-2; a P-type isolation region 5 is formed. Then, an N-type high-concentration collector region 11 is formed in the second layer 4-2; a P-type high-concentration injector region 6 and a P-type high-concentration base region 7 are formed simultaneously by a selective diffusion method. A P-type high-concentration guard-ring region 9 and an N-type high-concentration collector region 8 are formed around the region 7; an N-type high-concentration emitter region 10 is formed on the region 11. In addition, an injector electrode 13, a base electrode 14 and the like are formed.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an IIL type semiconductor device.

0002

[Prior Art] The basic structure of a conventional IIL circuit is shown in FIG.
) as shown. To explain this conventional example along the manufacturing process, an impurity concentration (per cubic centimeter) ranging from 10 to the 14th power (1E13 to 1E14) is formed on a P-type semiconductor substrate 1 having a high concentration N-type buried layer 2.
It is written as (hereinafter the same shall apply) N-type epitaxial layer 3
Then, impurities are selectively introduced from the surface of the N-type epitaxial layer 3 to form a P-type isolation region 5.

Next, a high concentration N type collector region 11 is formed in the isolated N type epitaxial layer 3, and a high concentration P type injector region 6 and a high concentration P type base region 7 are simultaneously formed by a selective diffusion method. do.

Next, a highly doped P-type guard ring region 9 with a higher concentration is formed around the highly doped P-type base region 7 , and then an N-type impurity is diffused to form a highly doped N-type impurity on the highly doped P-type base region 7 . A type collector region 8 is formed, and at the same time, a highly doped N-type emitter region 10 is formed on the highly doped N-type collector region 11.

Finally, an injector electrode 13, a base electrode 14, a collector electrode 15, and an emitter electrode 16 are formed through the openings in the silicon oxide film 2.

FIG. 2(b) shows an equivalent circuit diagram of this conventional example. Here, the injector electrode 13, emitter electrode 16, and base electrode 14 in the sectional view of FIG. 2(a) form the emitter, base, and collector of the PNP transistor Q1 in FIG. 2(b), and the collector electrode 15 and base electrode 1
4. Form the collector, base, and emitter of the NPN transistor Q2 using the emitter electrode 16.

[0007]

[Problem to be solved by the invention] The above-mentioned conventional IIL
The circuit has the following drawbacks.

In order to prevent surface inversion of the highly doped P-type base region 7, a highly doped P-type guard ring region 9 is formed.
As a result, the collector concentration of the PNP transistor Q1 increases, and the injection efficiency from the collector to the base of the PNP transistor Q1 increases, so that the DC current amplification factor of the NPN transistor Q2 when the injector electrode 13 is set to the same potential as the emitter electrode 16. The disadvantage is that it becomes smaller.

[0009]

Means for Solving the Problems The IIL type semiconductor device of the present invention includes first N type semiconductors deposited sequentially on a P type semiconductor substrate.
a highly doped P-type base region of a lateral PNP transistor selectively formed in the N-type second epitaxial layer of a semiconductor substrate having an epitaxial layer and an N-type second epitaxial layer with a higher concentration than the N-type first epitaxial layer; , a high concentration P type guard ring region provided around the high concentration P type base region and having a higher concentration than the high concentration P type base region; and a high concentration P type guard ring region provided at a predetermined distance from the high concentration P type guard ring region; and a heavily doped P-type injector region selectively formed in the second epitaxial layer.
It has a circuit.

0010

Embodiments Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1(a) shows I in one embodiment of the present invention.
1 is a cross-sectional view of a semiconductor chip showing the basic structure of an IL circuit.

To explain this embodiment along the manufacturing process, impurity concentration is 1E13 to 1E per cubic centimeter on a P type semiconductor substrate 1 having a high concentration N type buried layer 2.
14 N-type first epitaxial layers 4-1 are formed, and then an impurity concentration higher than that of the N-type first epitaxial layer is formed.
1E15-1E16 per cubic centimeter N type 2nd
An epitaxial layer 4-2 is formed. Next, impurities are selectively introduced into the N-type second epitaxial layer 4-2 to form a P-type isolation region 5.

Next, a high concentration N-type collector phosphorus region 1 is formed in the isolated N-type second epitaxial layer 4-2.
1 is formed, and then a high concentration P-type injector region 6 and a high concentration P-type base region 7 are simultaneously formed by a selective diffusion method.

Next, a high concentration P type guard ring region 9 with a higher concentration is formed around the high concentration P type base region 7.
Thereafter, N-type impurities are diffused to form a highly doped N-type collector region 8 on the heavily doped P-type base region 7, and at the same time, a highly doped N-type collector region 8 is formed on the highly doped P-type base region 7.
The type emitter region 10 is replaced by a highly doped N-type collector region 11.
Form on top. Finally, an injector electrode 13, a base electrode 14, a collector electrode 15, and an emitter electrode 16 are formed through the opening of the silicon oxide film 12.

Further, FIG. 1(b) shows an equivalent circuit diagram of the IIL circuit of FIG. 1(a). The injector electrode 13, emitter electrode 16, and base electrode 14 form the emitter, base, and collector of the PNP transistor Q1, and the collector electrode 15, base electrode 14, and emitter electrode 16 form the collector, base, and emitter of the NPN transistor Q2.

In this embodiment, by increasing the impurity concentration of the N-type second epitaxial layer, the PNP transistor Q
When the base concentration of PNP transistor Q1 increases and the injector electrode 13 is made to have the same potential as the emitter electrode 16 compared to the conventional example, the injection efficiency from the collector to the base of the PNP transistor Q1 decreases, resulting in a decrease in the NPN transistor Q2.
The DC current amplification factor increases.

Furthermore, if the concentration of the N-type first epitaxial layer 4-1 is made the same as that of the conventional N-type epitaxial layer 3, P
The DC current amplification factor of the NP transistor Q1 remains unchanged.

[0018]

Effects of the Invention As explained above, the present invention provides an N-type first
By providing an epitaxial layer and a highly doped N-type second epitaxial layer provided thereon, and providing an injector region and a guard ring region in the N-type second epitaxial layer, the DC current amplification factor of the PNP transistor in the IIL circuit is changed. It is possible to increase the direct current amplification factor of the NPN transistor without any increase in the current amplification factor. Therefore, there is an effect that the performance of the IIL circuit can be improved.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view (a) and an equivalent circuit diagram (b) for use in explaining one embodiment of the present invention.

FIG. 2 is a cross-sectional view (a) and an equivalent circuit diagram (b) for use in explaining a conventional example.

[Explanation of symbols]

1 P-type semiconductor substrate 2 High concentration N-type buried layer 3 N-type epitaxial layer 4-1 N-type first epitaxial layer 4-2
N-type second epitaxial layer 5 P-type isolation region 6 Highly doped P-type injector region 7 Highly doped P-type base region 8 Highly doped N-type collector region 9 Highly doped P-type guard ring region 10 Highly doped N-type emitter region 11 High Concentration N-type collectorin region 12
Silicon oxide film 13 Injector electrode 14 Base electrode 15 Collector electrode 16 Emitter electrode Q1 NPN transistor Q2 PNP transistor Q3 NPN transistor Q4 PNP transistor

Claims (1)

[Claims] 1. The N-type second epitaxial layer of the semiconductor substrate has an N-type first epitaxial layer sequentially deposited on a P-type semiconductor substrate and an N-type second epitaxial layer having a higher concentration than the N-type first epitaxial layer. A highly doped P-type base region of a lateral PNP transistor selectively formed in an epitaxial layer, and a highly doped P-type base region with a higher concentration than the highly doped P-type base region provided around the highly doped P-type base region.
and a high concentration P type injector region selectively formed in the N type second epitaxial layer apart from the high concentration P type guard ring region by a predetermined distance. IIL type semiconductor device.