JPS6341062A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To make an IIL operating at high speed and a vertical type PNP transistor to coexist effectively by using thickness only of a second epitaxial layer as the thickness of a substantial epitaxial layer in the IIL section. CONSTITUTION:Antimony forming first buried layers 24a, 24b, 24c in the surface of a P-type semiconductor substrate 21 is deposited, and boron shaping first diffusion layers 43 forming a collector buried layer 36 in a vertical type PNP transistor and isolation regions 25 is deposited previously on the buried layer 24c and the substrate 21 each surrounding the buried layers 24a, 24b, 24c. An N-type first epitaxial layer 22 is laminated on the whole surface of the substrate 21, and phosphorus shaping a buried base layer 37 through an ion implantation method and boron forming second diffusion layers 44 in the isolation regions 25 and first diffusion layers 45 in a collector leading-out region 38 through a selective diffusion method are shaped from the surface of the layer 22. Third diffusion layers 46, etc. in the isolation regions 25 can be formed simultaneously, thus simplifying and fining processes.

Description

Detailed Description of the Invention (a) Industrial Application Field The present invention relates to semiconductor integrated circuits, particularly high-speed IIL and N
The present invention relates to a semiconductor integrated circuit in which a PN transistor and a high fT vertical PNP transistor coexist.

(B) Prior Art A conventional semiconductor integrated circuit, for example, as shown in FIG. The plurality of buried layers (3a) (3b) (3c) formed and the buried layer (3a)
A P3 type isolation region (4) penetrating the epitaxial layer (2) so as to surround (3b) and (3c), respectively, and first, second, and third regions separated into islands by the isolation region (4). (5a) (5b) (5c) and the first island region (5a)
) P-type IIL base region (6) and injector region (7) formed on the surface, and IIL base region (6)
An N+ type collector region (8), an N type emitter contact region (9), and a second island region (5) formed on the surface.
b) A P type base region (10) formed on the surface and an N+ type emitter region (10) formed on the surface of the base region (10).
11), an N+ type collector contact region (12), and a P+ layer superimposed on the buried layer (3C) of the third island region (5C) and buried between this and the epitaxial layer (2). The collector buried layer (13) of the mold and the epitaxial layer (2)
The base region of the vertical PNP transistor (1
4), which extends from the surface of the third island region (5C) to the collector buried layer (13), and a P type collector region (15) formed on the surface of the base region (14). The emitter region (16) and the N+ type base contact region (17), the oxide film (18) covering the epitaxial layer (2), and the oxide film (18) are connected to each other through contact holes formed in the oxide film (18). It consists of an electrode (19) that makes ohmink contact.

The IIL formed in the first island region (5a) is described in Japanese Patent Application No. 60-206971, and the vertical PNP)-transistor formed in the third island region (5C) is described in,
Each of these is described in Japanese Patent No.-211270.

(c) Problems to be solved by the invention However, the vertical P formed in the third island region (5c)
An NP transistor has a predetermined breakdown voltage Vc due to its structure.

In order to obtain this, the epitaxial layer 2) must be considerably thick, at least 10 μm. Then the first island area (
In the IIL formed in 5a), the buried layer (3a) is separated from the base region (6), and the injection efficiency of minority carriers from the emitter to the base decreases, resulting in a decrease in the inverse β of the reverse vertical NPN transistor. As a result, the high speed of IIL cannot be utilized. Moreover, for the reasons mentioned above, vertical P
An NP transistor has a wide base width and cannot have a high fT, so it cannot be used as a high-speed element compatible with IIL. Therefore, it is difficult to coexist these elements while satisfying their respective characteristics.

(d) Means for solving the problems The present invention has been made in view of the above-mentioned drawbacks, and the present invention has been made in view of the above-mentioned drawbacks.
3), a second N1 type buried layer (27) buried in the surface of the first epitaxial layer (22), a P+ type buried base region (28) formed superimposed thereon, and An N° type collector region (29) formed on the surface of the second epitaxial layer (23) and a region surrounding the collector region (29) from the surface of the second epitaxial layer (23) to the buried base region (28). The P-type base lead-out region (30) reaching the base, the N"-type first buried Jl (24c) buried in the surface of the substrate (21) of the third island region (26c), and the 1 buried layer (24c) and a first epitaxial layer, 1
(22), a collector buried layer (36) buried between the
An N-type buried base layer (
37), and a third layer surrounding this embedded base layer (37).
A collector lead-out region (38) reaching from the surface of the island region (26c) to the collector buried layer (36), and a third island region (26c).
26c) By providing an emitter region (39) formed on the surface, a semiconductor integrated circuit is provided which greatly improves the conventional drawbacks.

(f) Function According to the present invention, since the thickness of only the second epitaxial FJ (22) in the IIL portion becomes the substantial thickness of the epitaxial layer, high speed performance can be easily obtained, and vertical PNP
) In the transistor part, the first and second epitaxial layers (2
3) The sum of the thicknesses (23) becomes the substantial thickness of the epitaxial layer, and the buried base thickness (37) has a breakdown voltage of V. ,. (
(equivalent to bunch through voltage), the base width can be narrowed and high r? can be converted into Therefore, according to the present invention, these elements can easily coexist while satisfying each of their requirements.

(f) Example Hereinafter, the present invention will be explained in detail with reference to the drawings.

FIG. 1 shows a cross-sectional view of a semiconductor integrated circuit according to the present invention,
N-type first and second epitaxial layers (22
) (23) and a plurality of N3 type first buried layers (24a) (24b) (24c) formed on the surface of the substrate (21).
and this first buried layer (24a) (24b) (24c)
A P-type isolation region (22) extending from the surface of the second epitaxial layer (23) to the first epitaxial layer (22) to the substrate (21) surrounds each of the P-type isolation regions (22); A plurality of island regions (26a
) (26b) (26c) and the first island area (26a)
A second buried layer (27) of N1 type buried between the first and second epitaxial layers (22) (23) of Second embedding W1 (27)
and a P+ type buried base region (28) buried between the first island region (23) and the second epitaxial layer (23).
N1 type collector region (29) formed on the surface of
), a P-type collector lead-out region (30) that extends from the surface of the first island region (26a) to the buried base region (28) so as to surround the collector region (29), and a first island region (
26a) P-type injector region (31) formed on the surface
> and N1 type emitter contact region (32), P type base region (33), N'' type emitter region (34) and N+ which constitute the NPN I- transistor formed on the surface of the second island region (26b). Type collector contact area (
35) and the first buried layer (26c) of the third island region <26c).
4C) and the first epitaxial layer (22
) P+ type collector buried layer (36) buried between
and the collector embedded between the first and second epitaxial, II (22) and (23) of the third island region (26c).
An N-type buried base layer (37) formed to reach t(36) and a second epitaxial J! layer surrounding this buried base layer (37). ! (23) P-type collector lead-out region (
), a P-type emitter region (39) and an N+-type base contact region (40) formed on the surface of the third island region (26c), and an oxide film covering the surface of the second epitaxial layer (23). (41) and an electrode (42) that makes ohmic contact with each region via a hole made in the oxide film (41), and the first island region (26)
In a), the implant-based IIL is located in the second island region (26
b) a normal NPN transistor is placed in the third island region (
In 26c), vertical PNP transistors are each integrally formed.

An example of the manufacturing method will be described below with reference to FIGS. 2A to 2E.

First, as shown in FIG. 2A, first buried layers (24a) (24b) (2) are formed in predetermined regions on the surface of the P-type semiconductor substrate (21).
deposit antimony (Sb) forming 4C),
On the predetermined first buried layer (24c) and on the first buried layer (24c)
A collector buried layer (36) of a vertical PNP transistor is on the substrate (21) surrounding 4a, 24b, and 24c, respectively.
And poron (B) forming the first diffusion layer (43) forming the isolation region (25) is deposited.

Next, as shown in FIG. 2B, an N-type first epitaxial layer (22
), and phosphorus (P) forming the buried base layer (37) is layered from the surface by ion implantation to form the second diffusion Jl (44) of the isolation region (25) and the second diffusion layer of the collector lead-out region (Japan). 1
Poron (B) forming the diffusion layer (45) is formed by a selective diffusion method and driven in together with the previously deposited impurities.

Next, as shown in FIG. 2C, a first epitaxial layer J'! corresponding to the first buried layer (24a) is formed. (22) Antimony (sb) forming a second embedded fi (27) on the surface
) and a poron (B) forming buried base region (28) is deposited or ion-implanted.

Then, as shown in the second diagram, the first epitaxial layer <
22) The second epitaxial layer 1 (23) is stacked on the entire surface, and the third diffusion layer (
46), IIL injector region (31) and base lead-out region (30), N P N ) - transistor base region (33), vertical PNP transistor emitter region (39) and collector lead-out region (Japan) The second diffusion region (47) is selectively diffused at the same time. Emitter area (39
) is formed to reach the buried base layer (37). In this step, the previously deposited impurities are driven in to form the base derivation region (30) and the buried base region (28).
) and the first, second, and third diffusion layers (43
) (44) (46> and the first of the collector derivation area (Japan)
, the second diffusion regions (45) (47) are completely connected.

Furthermore, as shown in FIG. 2E, a second epitaxial layer (
23) From the surface, the collector region (29) and emitter contact region (32) of IIL, the emitter region (34) and collector contact region (35) of NPN transistor,
Base contact region of vertical PNP transistor (4
0) at the same time, and finally, electrodes (42
) to complete the manufacturing process.

II formed in the first island region (26a) in this way
For L, the first and second epitaxial layers <22) (23)
Since the second buried layer (27) is provided in between, the substantial epitaxial layer thickness for IIL can be determined only by the thickness of the second epitaxial layer (22), and by setting it thin, It is possible to take advantage of the high-speed performance of IIL.Moreover, since the base of the reverse vertical NPN transistor of IIL is formed with a buried base region (28) that is diffused upward from the surface of the first epitaxial ff (22), the emitter A concentration gradient is generated from the base to the base, and the resulting electric field acts in the direction of accelerating the minority carriers completely injected into the base, resulting in a high inverse β.Furthermore, I
(inverted vertical NPN) of the IL - the substantial collector of the transistor is delimited by the base derivation region 30〉
Since it is formed of epitaxial Ji (23), NPN
Variations in the collector region (29), which is diffused and formed at the same time as the emitter region (34) of the transistor, do not affect the inverse β, and a stable inverse β can be obtained.

Furthermore, in the vertical PNP transistor formed in the third island region (26c), the buried base layer (37) suppresses the bunch-through effect between the emitter and the collector, so the base width can be narrowed and the ft can be improved. In other words, the embedded base layer (37
) whose impurity concentration is the same as that of the first and second epitaxial layers (
22) Since the setting is higher than (23) on the order of <10" to 10"am-", both the base-emitter junction and the base-collector junction become junctions in relatively high impurity concentration regions, and the impurity concentration from the emitter to the base side or The depletion layer spreading from the collector to the base side is suppressed and the bunch-through voltage increases.Therefore, while maintaining the desired breakdown voltage vc! (equal to the bunch-through voltage), the first and second epitaxial layers (22) ( By reducing the total thickness of 23), the base width can be made narrower and f''r can be improved. However, the first epitaxial layer (22) has a collector embedded f.
f(36) is largely diffused upward to a predetermined V. , (S
Since a thickness sufficient to obtain at) is required, the second epitaxial layer (23) may be made thin in order to narrow the base width. Second epitaxial layer (23)
It is advantageous to make it thin because it is consistent with the requirements of IIL. In this structure, the base is formed by a buried base layer (37) that is formed by diffusion with high precision by ion implantation, so that hF! Ya V. are the first and second epitaxial layers (
22) It is less affected by variations in (23) and has good controllability.

Furthermore, in the NPN transistor formed in the second island region (26b), the first and second epitaxial layers (22)
Since the sum of the thicknesses (23) becomes the substantial thickness of the epitaxial layer, a breakdown voltage can be easily obtained.

Furthermore, by adjusting the diffusion depth of the base region (33), it is possible to cope with higher rT.

According to the present invention, the second epitaxial layer (23
) is formed to have a relatively shallow diffusion depth of 1 to 2 μm.During the diffusion process of the base region (33) of the IIL,
) and the base lead-out region (30), the emitter region (39) of the vertical PNP transistor, the second diffusion region (47) of the collector lead-out region (47), and the third diffusion region (
46) can be formed at the same time, and the process can be simplified and miniaturized.

Further, as another embodiment of the present invention, it is possible to coexist with an even faster IIL by making the collector electrode (42) of the IIL a Schottky contact with the active region as a collector.

(g) As described in detail, according to the present invention, high speed IIL and high f7
vertical PNP transistor, and even normal NPN
It has the advantage that transistors can coexist effectively and easily. Moreover, it has the advantage that both vertical PNP transistors and NPN transistors can be made faster in response to faster IIL. And according to the invention, NP
N) The injector region (31) of the IIL, the emitter region (39) of the vertical PNP transistor, and the isolation region (25) are formed by the diffusion process of the base region (33) of the transistor.
Since the third diffusion layer (46) and the like can be formed at the same time, there is also an advantage that the process can be simplified and miniaturized.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view showing a semiconductor integrated circuit according to the present invention, FIGS. 2 A to E are process cross-sectional views for explaining the method of manufacturing a semiconductor integrated circuit according to the present invention, and FIG. 3 is a conventional semiconductor integrated circuit. FIG. (21) is the semiconductor substrate, (22) and (23) are the first and second epitaxial B, respectively, (27) is the second buried layer, (28) is the buried base region, and 30) is the base lead-out. (31) is the injector area, (33) is the base area, (36) is the collector buried layer, (37)
is the buried base layer, (38) is the collector derivation region, (
46) is the third diffusion layer of the separation region.

Claims (1)

[Claims] (1) first and second epitaxial layers of opposite conductivity type formed by sequentially stacking them on the entire surface of a semiconductor substrate of one conductivity type, and a plurality of first buried layers of opposite conductivity type formed on the surface of the substrate; isolation regions of one conductivity type extending from the surface of the second epitaxial layer to the substrate through the first epitaxial layer so as to surround each of the first buried layers; and an island-like isolation region formed by the isolation regions. a second buried layer of an opposite conductivity type formed buried between separated first, second, and third island regions and the first and second epitaxial layers of the first island region; and the second
a buried base region of one conductivity type which is superimposed on the buried layer and diffused upward from the surface of the first epitaxial layer;
a collector region of opposite conductivity type formed on the surface of the first island region; a collector lead-out region of one conductivity type extending from the surface of the second epitaxial layer to the buried base region so as to surround the collector region; an injector region of one conductivity type formed on the surface of the first island region, a base region of one conductivity type formed on the surface of the second island region, and an emitter region of opposite conductivity type formed on the surface of the base region; Said third
a collector buried layer of one conductivity type that is superimposed on the first buried layer in the island region and diffused upward from the substrate surface;
a buried base layer of an opposite conductivity type formed buried between the first and second epitaxial layers in the third island region; and the second epitaxial layer surrounding the buried base layer. A collector lead-out region of one conductivity type reaching from the surface to the collector buried layer, and an emitter region of one conductivity type formed on the surface of the third island region surrounded by the collector lead-out region. semiconductor integrated circuits.