JP2725773B2 - Semiconductor integrated circuit and manufacturing method thereof - Google Patents

Description

The present invention relates to a method of manufacturing a semiconductor integrated circuit incorporating a resistance element by an ion implantation method in which _hFE control of an NPN transistor is facilitated. (B) Conventional technology A bipolar IC is mainly composed of a vertical NPN transistor in which a base and an emitter are double-diffused on the surface of a semiconductor layer serving as a collector. Therefore, the NP
The base and emitter diffusion processes for manufacturing N-transistors are indispensable processes.The process of forming a high-concentration buried layer to reduce the series resistance of the collector, the process of growing an epitaxial layer, and the formation of isolation regions for junction isolation of each element. This is a step (basic step) that is indispensable for manufacturing a bipolar IC along with a step and an electrode forming step for electrical connection. On the other hand, there is a demand for incorporating other elements, for example, a PNP transistor, a resistor, a capacitor, a Zener diode, etc. on the same substrate due to circuit requirements. In this case, it is needless to say that it is preferable to divert the basic steps as much as possible from the viewpoint of simplifying the steps. However, in the base and emitter diffusion steps, various conditions are set with the characteristics of the NPN transistor being regarded as the most important. Therefore, in many cases, integration is difficult only by the basic steps. Therefore, a new process may be added for the purpose of incorporating another element or improving the characteristics of the other element, without the purpose of forming a basic NPN transistor. For example, a P ⁺ diffusion process for forming an anode region for controlling a Zener voltage of a Zener diode with a cathode region formed by the emitter diffusion, an R diffusion process for forming a resistance region having a specific resistance different from that of a base region, or an implantation process. These include a resistor formation process, a nitride film formation process to form a nitride film capacitance that can provide a larger capacitance than the MOS type, and a collector low resistance region formation process to further reduce the collector series resistance of the NPN transistor. This is a step (optional step) in which it is determined whether or not to add a bipolar IC in consideration of its use, purpose, and cost. FIG. 3 shows the MIS type capacitor formed by using the above optional process. In the figure, (1) is a P-type semiconductor substrate, (2) is an N-type epitaxial layer, (3) is an N ⁺ -type buried layer, (4) is a P ⁺ -type isolation region, (5) is an island,
(6) is an N ⁺ type lower electrode region by emitter diffusion,
(7) is a silicon nitride film (Si ₃ N) as a high dielectric constant insulator
₄ ) and (8) are upper electrodes made of aluminum material,
(9) is an oxide film, and (10) is an electrode. The MIS capacitor using a nitride film is described in, for example, Japanese Patent Application Laid-Open No. 60-244056. (C) Problems to be Solved by the Invention However, the conventional MIS type capacitor uses NPN as the lower electrode.
Since the emitter diffusion step of the transistor is used, a nitride film must be formed after depositing an N-type impurity for forming an emitter region, and then drive-in of the N-type impurity must be performed. Then, 800 used for depositing nitride film
Heat treatment around ℃ causes redistribution of the emitter region.
Transistors have a large variation in _hFE (current amplification factor), which makes it difficult to control _hFE . Further, since it is necessary to change the heat treatment conditions for the emitter region depending on whether or not an optional process required for forming a nitride film is added, process control for each model is required, and there is a disadvantage that the management cannot be shared. Was. (D) Means for Solving the Problems The present invention has been made in view of the above-mentioned drawbacks, and in a method of manufacturing a semiconductor integrated circuit in which an MIS type capacitor is incorporated, an MN is formed on the island surface prior to the emitter diffusion of the NPN transistor.
A lower electrode region (26) of the IS type capacitor and a dielectric thin film (28) are formed, and then the emitter of the NPN transistor is diffused, and the lower electrode (30) that makes ohmic contact with the lower electrode region (26) is comb-shaped. It is characterized by being arranged in. (E) Function According to the present invention, the region formed before the formation of the emitter region (30) is used as the lower electrode without using the emitter diffusion, and the emitter diffusion is performed after the nitride film is deposited. ) heat treatment step affect the h _FE after formation of the NPN transistor can be eliminated. Also, since the formation of the lower electrode region (26) is arranged in the first half of the process, the impurity concentration on the surface of the lower electrode region (26) decreases, and the lower electrode (30) contacts from the lower part of the dielectric thin film (28). Although the take-out resistance of the lower electrode (30) increases due to an increase in the diffusion resistance of the lower electrode region (26) up to the portion, according to the present application, the lower electrode (30) is arranged in a comb-teeth shape. The extraction resistance of the electrode (30) can be reduced. (F) Example Hereinafter, an example of the present invention will be described in detail with reference to the drawings. 1A and 1B show a semiconductor integrated circuit according to the present invention, wherein (21) is a P-type silicon substrate, (22) is an N ⁺ type buried layer provided on the surface of the substrate (21), and (23) ) Is an N-type epitaxial layer formed on the entire surface of the substrate (21), (24) is a P ⁺ -type isolation region penetrating the epitaxial layer (23), (2)
5) Epitaxial layer (23) by isolation region (24)
(26) is an island (2
5) Lower electrode region of a P-type or N-type MIS capacitor formed on the surface, (27) a silicon oxide film (SiO ₂ ) covering the surface of the epitaxial layer (23), and (28) an exposed lower electrode region A silicon nitride film (Si ₃ N) deposited on the surface of (26)
₄ ) Dielectric thin film consisting of (29) lower electrode region (26)
Upper electrode consisting of an aluminum layer provided on the surface of
Reference numeral 0) denotes a lower electrode that makes ohmic contact with the lower electrode region (26) through a contact hole (31). The lower electrode region (26) shows an example utilizing a separation region (24) forming step. Although the isolation region (24) is formed by high-impurity-concentration diffusion, the surface concentration is reduced because it is diffused considerably deeply and formed in the first half of the process. Then, the extraction resistance of the lower electrode increases as compared with the conventional example using emitter diffusion, and the MIS
The voltage dependency, frequency dependency, and hysteresis characteristics of the mold capacitor are all deteriorated. Therefore, by arranging the lower electrode (30) in a comb shape as a feature of the present application, the lower electrode (30)
To reduce the take-out resistance and prevent deterioration of various characteristics. According to the structure of the present invention, it is possible to deposit the dielectric thin film (28) before the emitter diffusion by forming the lower electrode region (26) of the MIS capacitor using the isolation region (24). become. Hereinafter, the manufacturing method of the present invention will be described with reference to FIGS. 2A to 2F. First, as shown in FIG. 2A, a surface of a P-type silicon semiconductor substrate (21) is coated with N such as antimony (Sb) or arsenic (As).
An N ⁺ -type buried layer (22) is formed by selectively doping type impurities, and an N-type epitaxial layer (23) having a thickness of 5 to 10 μ is laminated on the entire surface of the substrate (21). Next, as shown in FIG. 2B, boron (B) is selectively diffused from the surface of the substrate (21) to form a buried layer (22).
Penetrate the epitaxial layer (23) so as to surround
A P ⁺ type isolation region (24) is formed. The epitaxial layer (23) surrounded by the isolation region (24) becomes an island (25) for forming each circuit element. At the same time, the boron (B) in the isolation region (24) diffusion step is also diffused into a region corresponding to the buried layer (22) on the surface of the island (25), and the buried layer (22) is removed from the surface of the epitaxial layer (23). Is formed to reach the lower electrode region (26). The bottom of the lower electrode region (26) is formed so as to be entirely in contact with the buried layer (22), and the buried layer (22) electrically insulates the lower electrode region (26) from the ground potential of the substrate (21). . Therefore, the MIS capacitor is electrically independent, and there is no restriction on the circuit configuration. The diffusion of the isolation region (24) is performed by saturation diffusion. However, since the epitaxial layer (23) is penetrated, the surface concentration of the lower electrode region (26) is 10 ¹⁸ atoms.
・ It is around cm ^-2 . Next, as shown in FIG. 2C, boron (B) is selectively ion-implanted or diffused into the surface of the island (25) other than the island (25) in which the lower electrode region (26) is formed, thereby forming an NPN. Base region (3
2) Form At this time, if boron (B) is also diffused to the surface of the lower electrode region (26), the surface concentration of the lower electrode region (26) can be improved. Next, as shown in FIG. 2D, the thermal oxidation or CVD oxide film (27) formed on the surface of the epitaxial layer (23) is selectively removed by etching to expose a part of the surface of the lower electrode region (26). A silicon nitride film (Si ₃ N) having a thickness of several hundreds to several hundreds of millimeters is formed on the entire surface of the epitaxial layer (23) using a technique such as a normal pressure CVD method.
₄ ) Deposit. Since the silicon nitride film has a higher dielectric constant than the silicon oxide film, a large capacity can be formed. Then, a well-known resist pattern is formed on the surface of the silicon nitride film, and a dielectric thin film (28) covering the surface of the exposed lower electrode region (26) is formed by using a dry etching technique such as RIE. After that, the dielectric thin film (2
An oxide film (27) is deposited by CVD so as to cover 8). Next, as shown in FIG. 2E, an oxide film (27) on the surface of the base region (32) and the surface of the island (25) of the NPN transistor is opened, and phosphorus (P) is formed using the oxide film (27) as a mask. ) Is selectively diffused to form an N ⁺ -type emitter region (33) and a collector contact region (34). Next, as shown in FIG. 2F, a resist pattern of a negative or positive photoresist is formed on the oxide film (27), and the oxide film (27) on the dielectric thin film (28) is formed by wet or dry etching. Remove and further oxide film (27)
Contact holes (3
1) Open the hole. Then, an aluminum layer is formed on the entire surface of the epitaxial layer (23) by a well-known vapor deposition or sputtering technique, and the aluminum layer is patterned again to form an electrode (35) having a desired shape and an upper electrode (35) on the dielectric thin film (28). 29) and the lower electrode (30) are formed. According to the manufacturing method of the present invention, since the diffusion region formed by the diffusion step of the isolation region (24) is used as the lower electrode region (26) of the MIS capacitor, the dielectric thin film (28)
Can be arranged before the emitter diffusion step. Then, phosphorus (P) for forming the emitter region (33) is formed.
MIS before drive-in of Rin (P) from deposit
There is no need to arrange a heat treatment for forming the mold capacity, and the NP is immediately changed from the state where phosphorus (P) is initially diffused by the deposit.
A heat treatment (drive-in) process for controlling the _hFE (current amplification factor) of the N transistor can be performed. Therefore, variations in the h _FE of the NPN transistor is less, can solve the difficulty of h _FE control due to the fact that incorporating the MIS-type capacity. In addition, since the heat treatment conditions for the emitter region (33) can be unified regardless of whether the MIS type capacitor is incorporated or not, the process management for each model becomes extremely easy. The lower electrode region (26) of the present application takes various embodiments.
For example, using the upper / lower isolation technology, using only the upper diffusion region of the upper / lower isolation technology, using the P ⁺ type diffusion region deeper than the base region (32) with a high impurity concentration and forming the anode of a Zener diode And those using an N-type collector low resistance region for the purpose of reducing the collector resistance of the NPN transistor reaching from the surface of the epitaxial layer (23) to the buried layer (22). Since both are performed before the diffusion of the emitter, the surface concentration is lower than that of the emitter region (33). (G) As described above, according to the present, variations in the h _FE of the NPN transistor is not etc. small quantity due to the addition of the MIS capacitor as optional devices according to the present invention, the NPN transistor h
There is an advantage that a method of manufacturing a semiconductor integrated circuit in which _FE control is extremely easy can be provided. In addition, the emitter area (33) differs between models that incorporate the MIS type capacitor and models that do not.
Since the processing conditions can be unified, the process management for each model can be simplified, and further, there is an advantage that a small number of models can be produced in a small number, such as heat treatment of wafers of different models in the same diffusion furnace. According to the present application, since the lower electrode (30) has a comb-teeth shape to reduce the extraction resistance of the lower electrode (30), the lower electrode region (26) has a lower surface concentration than the emitter region (33). Despite using the area, MI
It also has the advantage that the deterioration of the characteristics of the S-type capacitor can be prevented.

BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1A and 1B are a plan view and a sectional view taken along the line AA, respectively, for explaining the present invention, and FIGS. 2A to 2F show a manufacturing method of the present invention, respectively. FIG. 3 is a cross-sectional view for explaining a conventional example. (21) is a semiconductor substrate, (26) is a lower electrode region, (28) is a dielectric thin film, (29) is an upper electrode, and (30) is a lower electrode.

Claims (1)

(57) [Claims] A reverse conductivity type epitaxial layer formed on the one conductivity type semiconductor substrate; a reverse conductivity type buried layer formed on the substrate surface; and a one conductivity type separation for separating the epitaxial layer so as to surround the buried layer, respectively. A plurality of islands formed by the isolation region; and one conductivity type or reverse conductivity type formed on the surface of the island prior to the emitter diffusion of the vertical bipolar transistor.
A lower electrode region of the MIS type capacitor; a dielectric thin film formed by depositing prior to the emitter diffusion so as to cover the lower electrode region; and a MI contacting the surface of the lower electrode region with an ohmic contact.
A lower electrode of an S-type capacitor; and an upper electrode disposed on the dielectric thin film so as to face the lower electrode region with the dielectric thin film interposed therebetween. A semiconductor integrated circuit having a surface concentration lower than that of a region and wherein the upper electrode and the lower electrode are formed in a comb shape. 2. Forming a reverse conductivity type buried layer in a desired region of the one conductivity type semiconductor substrate; forming a reverse conductivity type epitaxial layer on the substrate; forming a plurality of islands by separating the epitaxial layer Forming a one-conductivity-type or reverse-conductivity-type lower electrode region serving as a lower electrode of an MIS-type capacitor on one island surface; exposing a part of the surface of the lower electrode region,
Depositing a dielectric thin film of a type capacitor and forming it in a comb shape; after forming the dielectric thin film, an emitter of the opposite conductivity type of the vertical bipolar transistor by selectively diffusing impurities of the opposite conductivity type. Forming a region, forming a conductive film on the entire surface, and forming the MI on the dielectric thin film.
Arranging an upper electrode of an S-type capacitor, and an electrode in ohmic contact with the lower electrode region on the surface of the lower electrode region in a comb-like shape, wherein the surface concentration of the lower electrode region is equal to the emitter concentration. A method for manufacturing a semiconductor integrated circuit, wherein the surface concentration is lower than a surface concentration of a region.