JPH01133344A - Semiconductor integrated circuit and manufacture thereof - Google Patents

Abstract

PURPOSE:To control easily the amplification factor of an electric current in an NPN transistor, by using a lower electrode region which is formed by a diffusion process in an isolation region as a lower electrode where MIS type capacity is formed. CONSTITUTION:Isolation and lower electrode regions 24 and 26 are formed by diffusing selectively boron from the surface of an epitaxial at layer 23 and this lower electrode region 26 is used as a lower electrode of MIS type capacity and a nitriding film is deposited at the surface of the lower electrode region 26 as well and after forming a dielectric thin film 29 of MIS type capacity, the emitter diffusion of an NPN transistor is performed. In this way, as the lower electrode region 26 which is formed by making use of the diffusion process of the isolation regions 24 is used as the lower electrode of MIS type capacity, deposition of the nitriding film is performed prior to an emitter diffusion process and heat-treatment which makes hFE of the NPN transistor disperse after forming an emitter region 30 can be eliminated.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a method of manufacturing a semiconductor integrated circuit incorporating an MIS type capacitive element, which facilitates the mounting and control of an NPN l-transistor.

(b) Conventional technology Bipolar IC is a vertical NPN in which a base and an emitter are double-diffused on the surface of a semiconductor layer that serves as a collector.
The configuration is incorrect, mainly consisting of transistors. Therefore, the base and emitter diffusion processes for manufacturing the NPN transistor are essential processes, as well as the high-concentration buried layer formation process and epitaxial layer growth process to reduce the collector series resistance, and the junction isolation process for each element. This is an essential process (basic process) for manufacturing bipolar ICs, along with the isolation region forming process and the electrode forming process for electrical connection.

On the other hand, due to circuit requirements, there is a demand for incorporating other elements such as PNP transistors, resistors, capacitors, Zener diodes, etc. on the same substrate. In this case, it goes without saying that it is preferable to utilize the basic steps as much as possible in terms of process simplification. However, since the conditions for the base and emitter diffusion steps are set with the most important consideration being given to the characteristics of the NPN transistor, it is often difficult to integrate the base and emitter diffusion steps using only the basic steps. Therefore, a new process may be added not for the purpose of forming a basic NPN transistor, but for the purpose of incorporating other elements or improving the characteristics of other elements. For example, P is used to form an anode region that controls the Zener voltage of the Zener diode together with the cathode region formed by the emitter diffusion.
1 diffusion process, R diffusion process to form a resistance region with a different resistivity from the base region, implant resistance formation process, MO
This includes the process of forming a nitride film to form a nitride film capacitor that provides a larger capacitance than the S type (NPN) - the process of forming a collector low resistance region to further reduce the collector series resistance of transistors, etc. All bipolar ICs This is a process (optional process) that is determined whether to add it or not after considering its use, purpose, and cost.

FIG. 4 shows an MIS type capacitor formed using the above optional process. In the figure, (1) is a P-type semiconductor substrate, (2) is an N-type epitaxial layer, (3) is an N+-type buried layer, (4) is a P+-type isolation region, (5) is an island, (
6) is the N0 type lower electrode region by emitter diffusion, (7
) is a silicon nitride film (SiJa) as a high dielectric constant insulator.
), (8) are upper electrodes made of aluminum material, (9
) is an oxide film, and (10) is an electrode.

Incidentally, an MIS type capacitor using a nitride film is described in, for example, Japanese Patent Laid-Open No. 60-244056.

(c) Problems to be solved by the invention However, the conventional MIS type capacitor uses N as the lower electrode.
Since the emitter diffusion process of a PN transistor is used, a nitride film must be formed after the N-type impurity for forming the emitter region is deposited, and then the N-type impurity must be driven in.

As a result, the heat treatment at around 800° C. used to deposit the nitride film diffuses the emitter region, resulting in large variations in the NPN transistor thickness and t (current amplification factor), which is difficult to control.

In addition, it is necessary to change the heat treatment conditions for the emitter region depending on whether or not the optional process necessary for forming the nitride film is added, so process management is required for each model, and there is a drawback that management cannot be standardized. Ta.

(d) Means for Solving the Problems The present invention was made in view of the drawbacks, and is a method for manufacturing a semiconductor integrated circuit incorporating an MIS type capacitor, in which poron (B) is selectively diffused from the epitaxial M (23> surface). By doing so, the separation region (24) and the lower electrode region (26
), and this lower electrode region (26) is used as the lower electrode of the MIS type capacitor.
According to the present invention, the special effect is characterized in that the emitter diffusion of the NPN transistor is performed after depositing a nitride film (SisNa) on the surface and forming the dielectric thin film (29) of the MIS type capacitor. Since the lower electrode region (26) formed using the diffusion process of the region (24) is used as the lower electrode of the MIS type capacitor, the nitride film can be deposited before the emitter diffusion process, and the emitter region (24) can be deposited before the emitter diffusion process. 30) It is possible to eliminate heat treatment that would cause variations in the adhesiveness and □ of the NPN transistor after formation.

(F) Example Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows the cross-sectional structure of the semiconductor integrated circuit of the present invention, (
21) is a P-type silicon substrate, (22) is a substrate (21)
A plurality of N1 type buried layers are provided on the surface, (23) is the substrate (
21) An N-type epitaxial layer laminated on the entire surface, (24) a P+ type isolation region penetrating the epitaxial layer (23), and (25) an epitaxial layer (23) formed by the isolation region (24). An island (26) formed in the form of an island reaches from the surface of the epitaxial layer (23) formed simultaneously on the surface of one island (25) using the diffusion process of the isolation region (24) to the buried layer (22). (27) is the P-type base region of the NPN) transistor formed on the surface of the other island (25); (28) is the epitaxial layer (2);
3) Silicon oxide film (SiO*) covering the surface, (29)
(30) is the dielectric thin film of the MIS type capacitor deposited on the surface of the lower electrode region (26), (30) is the N+ type emitter region of the NPN transistor formed on the surface of the base region (27), (
31) is an N1 type collector contact region for extracting the collector of the NPN transistor formed on the surface of the island (25), (32) is an electrode made of aluminum material that makes ohmic contact with each region via a contact hole, and (33) is an electrode made of aluminum material that makes ohmic contact with each region through a contact hole. This is an upper electrode provided on the dielectric thin film (29) so as to face the lower electrode region (26). The entire bottom of the lower electrode region (26) is formed so as to be in contact with the buried layer (22), and the lower electrode region (26) is electrically insulated from the ground potential of the substrate (21) by the buried JFt (22). . Therefore, since the MIS type capacitor is electrically independent,
There are no restrictions on circuit configuration.

According to the structure of the present application, the lower electrode region (24) formed simultaneously with the separation region (24) serves as the lower electrode of the MIS type capacitor.
26), the dielectric thin film (29) formation process can be placed before the emitter diffusion process.

Hereinafter, the manufacturing method of the present application will be explained using FIGS. 2A to 2F.

First, as shown in FIG. 1A, a P-type silicon semiconductor substrate (
21) is selectively doped with N-type impurities such as antimony (sb) or arsenic (As) to form an N+-type buried Jl (2
2) with a thickness of 5 to 10 μm on the entire surface of the substrate (21).
A mold epitaxial layer (23) is deposited.

Next, as shown in FIG. 1B, by selectively diffusing boron (B) from the surface of the substrate (21), the buried layer (22
A P+ type isolation region (24) penetrating the epitaxial layer (23) is formed so as to surround each of the isolation regions (
The epitaxial layer (23) surrounded by 24) becomes an island (25) for forming each circuit element. At the same time, boron (B) from the separation region (24) diffusion process is also diffused into the region corresponding to the buried layer (22) on the surface of the island (25), and the buried JI is diffused from the surface of the epitaxial layer (23).
Since the zero separation region (24) forming the lower electrode region (26) reaching (22) is formed by saturated diffusion, the surface concentration of the lower electrode region (26) is 10"atoms-cm-
``It can be used as a lower electrode of MIS type capacitor.

Next, as shown in FIG. 1C, boron (B) is selectively ion-implanted or diffused into the surface of an island (25) different from the island (25) on which the lower electrode region (26) is formed. A base region (27) that will become the base of the transistor is formed.

Next, as shown in the first diagram, the oxide film (28) on the surface of the epitaxial layer (23) is selectively etched away to expose a part of the surface of the lower electrode region (26), and the entire surface of the epitaxial layer (23) is etched. A silicon nitride (Si) film with a film thickness of several hundred to 1,000 layers is produced using techniques such as atmospheric pressure CVD.

N,) is deposited. Since a silicon nitride film exhibits a higher dielectric constant than a silicon oxide film, it is possible to form a large capacitance. Then, a well-known resist pattern is formed on the surface of the silicon nitride film, and a dielectric thin film (29) is formed to cover the surface of the exposed lower electrode region (26) using a technique such as dry etching. After that, dielectric thin film (
An oxide film (28) is deposited by the CVD method so as to cover (29).

Next, as shown in FIG. 1E, the oxide film (
28) A hole is opened and phosphorus (P) is selectively diffused using the oxide film (28) as a mask to form an N+ type emitter region (30) and a collector contact region (31).

Next, as shown in FIG. 1F, a resist pattern of negative or positive photoresist is formed on the oxide film (28), and the oxide film (28) on the dielectric thin film (29) is removed.
Furthermore, by wet or dry etching, the sleeve-forming film (
28>, a contact hole for electrical connection is opened at a desired portion. Then, an aluminum layer is formed on the entire surface of the substrate (21) by a well-known vapor deposition or sputtering technique, and this aluminum layer is patterned again to form an electrode (32) in a desired shape and an upper electrode (33) on the dielectric thin film (29). ) to form.

According to the manufacturing method of the present application, since the lower electrode region (26) formed by the diffusion process of the separation region (24) is used as the lower electrode forming the MIS type capacitor, the manufacturing process of the dielectric thin film (29) is can be installed before the emitter diffusion process. Then, there is no need to perform heat treatment for forming the MIS type capacitor between the phosphorus (P) deposit for forming the emitter region (30) and the phosphorus (P) drive-in, and the phosphorus (P) is A heat treatment (drive-in) process for controlling h□ (current amplification factor) of the NPN transistor can be performed immediately from the diffused state. Therefore, h of NPN transistor
hFI with little variation in □ and incorporating MIS type capacitance! It can eliminate the difficulty of control. Furthermore, since the heat treatment conditions for the emitter region (30) can be unified for models that incorporate MIS type capacitors and models that do not, process management for each model becomes extremely easy.

The present invention is not limited to the embodiment shown in FIG. 1, but can also be applied to semiconductor integrated circuits using upper and lower separation techniques. moreover,
In the case where the upper and lower separation technology is used, instead of using both the upper and lower areas, the upper and lower separation areas (
C) Upper diffusion! It is also possible to form the lower electrode region (26>) using only (35). In this case, the lower electrode region (26) does not reach the buried W (22), so it is not connected to the substrate (21). Can provide electrical insulation.

(G) As described in detail, according to the present invention, there is little variation in h□ of NPN transistors due to the addition of MIS type capacitors as optional devices, so it is extremely possible to control h□ of NPN transistors. This method has the advantage of providing an easy method for manufacturing semiconductor integrated circuits. Also, M
Processing conditions for the emitter area (30) can be unified for models with IS-type capacitance and models without, simplifying process management for each model, and even allowing wafers of different models to be placed in the same diffusion furnace. Furthermore, according to the present application, since the lower electrode region (26) is formed using the diffusion process of the separation region (24), the process can be simplified. It is possible to
Since the first embodiment uses the buried layer (22), it also has the advantage that electrical insulation from the substrate (21) can be easily achieved.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view for explaining the present invention, FIGS. 2A to 2F are cross-sectional views for explaining the manufacturing method of the present invention, and FIG.
The figure is a sectional view for explaining the second embodiment of the present invention.
The figure is a sectional view for explaining a conventional example. (21) is a P-type semiconductor substrate, (26) is the lower electrode region of the MIS type capacitor, (27) is the P-type base region of the NPN transistor, (29) is the dielectric thin film, (30)
is the N+ type emitter region of the transistor (NPN), (
33) is the upper electrode of the MIS type capacitor.

Claims (2)

[Claims] (1) An epitaxial layer of the opposite conductivity type formed on a semiconductor substrate of one conductivity type, a buried layer of the opposite conductivity type formed on the surface of the substrate, and the epitaxial layers are separated so as to surround each of the buried layers. an isolation region of one conductivity type, a plurality of islands formed by the isolation region, and an MI of one conductivity type formed on the surface of one island in the same process as the isolation region.
A lower electrode region of an S-type capacitor, a dielectric thin film provided to cover a part of the surface of the lower electrode region, and the MIS provided to face the lower electrode region with the dielectric thin film sandwiched therebetween. A vertical bipolar transistor includes an upper electrode of a type capacitor, a base region of one conductivity type of a vertical bipolar transistor formed on the surface of another island, and an emitter region of an opposite conductivity type formed on the surface of this base region. Semiconductor integrated circuit. (2) A step of forming a buried layer of an opposite conductivity type on the surface of a semiconductor substrate of one conductivity type, a step of forming an epitaxial layer of an opposite conductivity type on the substrate, an isolation region of one conductivity type from the surface of the epitaxial layer. A plurality of islands are formed by forming a MIS on the surface of one island by the step of forming the isolation region.
forming a base region of a vertical bipolar transistor by selectively introducing impurities of one conductivity type into another island surface; a part of the surface of the lower electrode region; and the MI
a step of depositing and forming a dielectric thin film of S-type capacitance; a step of forming an emitter region of the vertical bipolar transistor by selectively diffusing impurities of opposite conductivity type after forming the dielectric thin film; A conductive film is formed on the entire surface, and the M
1. A method of manufacturing a semiconductor integrated circuit, comprising the step of providing an upper electrode of an IS type capacitor in desired regions, and an electrode that makes ohmic contact with each region.