JPH061813B2 - Method for manufacturing semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a semiconductor integrated circuit in which a resistance element by an ion implantation method and a MIS type capacitance element, which facilitates h _FE control of an NPN transistor, are incorporated. It relates to a manufacturing method.

(B) Conventional Technology A bipolar IC is mainly composed of a vertical NPN transistor in which a base / emitter is double-diffused on the surface of a semiconductor layer serving as a collector. Therefore, the base and emitter diffusion steps for manufacturing the NPN transistor are indispensable steps, and a high-concentration buried layer forming step for reducing collector series resistance, an epitaxial layer growing step, and junction separation for each element. This is a step (basic step) essential for manufacturing a bipolar IC along with the isolation region forming step, the electrode forming step for electrical connection, and the like.

On the other hand, there is a demand for incorporating other elements such as a PNP transistor, a resistor, a capacitor, and a Zener diode on the same substrate in view of circuit requirements. In this case, needless to say, it is preferable to divert the basic process as much as possible from the viewpoint of simplifying the process. However, in the base and emitter diffusion process, since various conditions are set with the characteristics of the NPN transistor as the most important factor, integration is often difficult only by the basic process. So, basic NP
A new process may be added for the purpose of incorporating another element or improving the characteristics of another element without forming the N-transistor. For example, a P ⁺ diffusion process for forming an anode region for controlling the Zener voltage of a Zener diode with the cathode region by the emitter diffusion, an R diffusion process for forming a resistance region having a specific resistance different from that of the base region, and an implantation process. A resistance forming step, a nitride film forming step for forming a nitride film capacitor that can provide a larger capacity than that of a MOS type, and a collector low resistance region forming step for further reducing the collector series resistance of an NPN transistor are all included in it. This is a process (optional process) in which it is determined whether or not to add the bipolar IC by considering the use and purpose and cost of the bipolar IC.

FIG. 4 shows an example of a conventional semiconductor integrated circuit formed by using the above optional process. In the figure, (1) is P
Type substrate, (2) N type epitaxial layer, (3) N ⁺ type buried layer, (4) P ⁺ type isolation region, (5) island, (6) NP
P type base region of N transistor, (7) N ⁺ type emitter region, (8) N ⁺ type collector contact region, (9) P type resistance region of resistance element, (10) resistance region (9 ) Contact region, (11) is N ^{+ of} MIS type capacitance due to emitter diffusion
The mold lower electrode region, (12) is a silicon nitride film (Si ₃ N ₄ ) as a dielectric thin film, (13) is an oxide film, (14) is an upper electrode, and (15) is an electrode. An MIS type capacitor using a nitride film is described in, for example, Japanese Patent Laid-Open No. 60-244056, and a resistance element using ion implantation is disclosed in, for example, Japanese Patent Publication No. 57-2182.
It is described in Japanese Patent Publication No.

Since the MIS type capacitor uses the lower electrode region (11) by emitter diffusion, the step of forming the dielectric thin film (12) must be performed after the step of depositing the N type impurities forming the emitter region (7). I have to. Further, the resistance region (9) by ion implantation was also performed after the emitter diffusion as described in the above publication.

(C) the invention the problem to be solved point, however, to perform some kind of process to emitter diffusion after the conventional semiconductor integrated circuit, the NPN transistor h _FE
A final heat treatment for control must be placed after any of the above steps. Then, the phosphor used for the heat treatment or the emitter region (7) formation used in any of the above steps is formed.
The heat treatment performed immediately after depositing (P) once diffuses the phosphorus (P) for forming the emitter region (7), so that the h _FE (current amplification factor) of the NPN transistor varies widely, and its control is difficult. was there. The heat treatment used in any of the above steps is a silicon nitride film (Si ₃ N ₄ )
There is a heat treatment at about 800 ° C. by CVD when depositing the.

Further, the drive-in condition of the emitter region (7) needs to be changed depending on whether an optional step for incorporating a MIS type capacitor and a resistance element by ion implantation is added.
There was a drawback that it was necessary to manage the process for each model and it could not be shared.

(D) Means for solving the problem The present invention has been made in view of the above drawbacks, and a step of removing the thick oxide film (27) used in forming the isolation region and reattaching the thin oxide film (29). A step of forming a resistance region (31) and a base region (32) of the NPN transistor by ion-implanting a P-type impurity through the oxide film (29), and a lower electrode region formed prior to the emitter diffusion. MI on the surface of (28)
The present invention is characterized in that the step of forming the S-type capacitor dielectric thin film (36) and the heat treatment for incorporating the optional device are completed, and then the emitter region (38) of the NPN transistor is diffused.

(E) Action According to the present invention, since the heat treatment for incorporating the optional device is completed prior to the emitter diffusion, any extra heat treatment from the deposit of the emitter region (38) to the drive-in is eliminated. be able to.

(F) Embodiment Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.

First, as shown in FIG. 1A, a P-type silicon semiconductor substrate (2
N ⁺ -type buried layer (22) formed by selectively doping the N-type impurity of antimony (Sb) or arsenic (As) or the like on the surface of 1), the substrate surrounding the buried layer (22) ( 21) Boron (B) on the surface
Is doped to form a lower diffusion layer (23) which is vertically separated. After that, a thickness of 5 is formed on the entire surface of the substrate (21) by a known vapor deposition method.
An N-type epitaxial layer (24) of 10 μm is laminated.

Next, as shown in FIG. 1B, boron (B) is selectively diffused from the surface of the epitaxial layer (24) to form the epitaxial layer (24).
A plurality of islands (25) are formed by separating the junctions. (26) is an upper diffusion layer that is separated into upper and lower parts, and (27) is an oxide film.

At the same time, by using the diffusion process of the upper diffusion layer 26, M
A lower electrode region (28) to be the lower electrode of the IS type capacitor is formed. According to the present embodiment, the steps can be shared, so that the steps can be simplified. Needless to say, the P ⁺ type diffusion region may be formed alone or by utilizing the process for forming the anode of the Zener diode, or may be formed before or after the subsequent base diffusion process. Further, regardless of the diffusion depth of the lower electrode region (28),
It is desirable that the impurity concentration is a high impurity concentration, for example, 10 ¹⁸ atoms · cm ⁻² or more in view of the hysteresis of the MIS-type capacitance. Since this step is used as a mask for selective diffusion and heat treatment is performed in an oxidizing atmosphere, a thick oxide film (27) having a film thickness of 5000 to 8000Å is formed on the surface of the epitaxial layer (24).

Next, as shown in FIG. 1C, the thick oxide film (27) is removed by 10%.
Completely remove with an HF solution, etc.
4) Expose the surface. Then, thermal oxidation is performed again to form a new thin oxide film (29) having a film thickness of several hundred to 1000 Å on the surface of the epitaxial layer (24). Since the step formed during the deposition of boron (B) remains on the surface of the epitaxial layer (24), the step also appears on the surface of the thin oxide film (29). Therefore, the subsequent mask alignment can be performed.

Next, as shown in FIG. 1D, a positive or negative photoresist is spin-on coated, exposed, and developed on the oxide film (29) on the surface of the epitaxial layer (24) to develop a first resist pattern of a desired shape ( 30) is formed. After that, boron (B) is selectively penetrated through the oxide film (29) and ion-implanted by using the first resist pattern (30) as a mask, and the resistance regions having the same impurity concentration are formed on the surfaces of the two islands (25).
(31) and the base region (32) of the NPN transistor are formed respectively. In the first ion implantation, the dose amount and accelerating voltage of boron (B) are set in accordance with the impurity concentration of the side where the specific resistance is increased, that is, the resistance region (31). The heat treatment (drive-in) of the impurities ion-implanted in the first time is not performed at this stage.

Next, as shown in FIG. 1E, the first resist pattern (3
A negative type photoresist film is spin-on coated on the surface with 0) removed or left to form a second resist pattern (33). The second resist pattern (33) has a smaller shielded portion than the first resist pattern (30). Therefore, in the second opening of the resist pattern (33), the oxide film (29) in the region ion-implanted in the previous step is formed.
The edge portion of the resist pattern (30) for the second time is exposed. Part (34) of the second resist pattern (33)
Directly covers the surface of the oxide film (27) except both ends of the resistance region (31) and exposes only the contact portion of the resistance region (31).

Then, using the first resist pattern (30) formed in the previous step from the surface of the epitaxial layer (24) as a mask, the second ion implantation of boron (B) is performed through the oxide film (29). Since boron (B) is ion-implanted in the base region (32) of the NPN transistor, the second ion-implantation is performed so that the impurity concentration of the side where the specific resistance is lowered, that is, the base region (32) is determined at this stage. The dose amount is set.
The impurity concentration of the base region (32) is set so that ohmic contact with an electrode to be formed later can be performed, and the second region is also ion-implanted at both ends of the resistance region (31). A contact region (35) for arranging an electrode having the same impurity concentration as that of (32) is formed. Since the resistance region (31) between the contact regions (35) is covered with a part (34) of the second resist pattern (33), the second boron (B) is not ion-implanted. Therefore, the impurity concentration of the portion covered by a part (34) of the second resist pattern (33) remains the impurity concentration set by the first ion implantation, and this region substantially has the resistance value of the implantation resistance. It becomes the area to be decided. Moreover, since the impurity concentration is low, the contact region (35) is required.

Although the presence or absence of the first resist pattern (30) does not matter at the second ion implantation stage, the advantage of being able to omit the etching step once and the thickness of the oxide film (29) can be made thin if it is left. Have advantages. Also, the resistance region (31) and the base region
The formation of (30) may be performed using a single resist pattern. Further, by diffusing boron (B) also on the surface of the lower electrode region (28) at the same time as the base diffusion, the surface concentration of the lower electrode region (28) can be improved.

Next, as shown in FIG. 1F, the first and second resist patterns (30) and (33) are removed, and the oxide film (29) on the surface of the epitaxial layer (24) is selectively etched to remove the lower electrode region. (2
8) Part of the surface is exposed, and a silicon nitride film (Si ₃ N ₄ ) having a film thickness of several hundred to several thousand and several hundred Å is deposited on the entire surface of the epitaxial layer (24) by using a technique such as atmospheric pressure CVD. Since the silicon nitride film has a higher dielectric constant than the silicon oxide film, it is possible to form a large capacity. Then, a well-known resist pattern is formed on the surface of the silicon nitride film, and a dielectric thin film (36) covering the exposed surface of the lower electrode region (28) is formed by using a technique such as dry etching.

Next, as shown in FIG. 1G, a thick oxide film (37) having a film thickness of 2000 to 6000Å is formed on the entire surface so as to cover the dielectric thin film (36) by a normal pressure CVD method, and the dielectric film (1000) is heated to 1000 in a non-oxidizing atmosphere. ℃
Perform a heat treatment to some extent. Oxide film by CVD in this process (37)
And the drive-in of the base region (32) of the NPN transistor is performed. The resistance area (31) is
Due to the difference in concentration, it is shallower than the base region (32). Of course, the drive-in of the base region (32) may be performed in the step of FIG. 1E, but since the base region (32) is covered with a thin oxide film (29) during the process, On the nitride film
After (Si ₃ N ₄ ) formation, baking can be performed at the same time. This process is a non-oxidizing process, and the CVD
Since the surface of the epitaxial layer (24) is covered with the thin oxide film (29) when the oxide film (37) is formed by the method, there is almost no depletion of impurities on the surface of the base region (32) and the resistance region (31). Therefore, the impurity concentration and depth of the base region (32) can be formed with high precision and controllability, and the high precision of the resistance element using the ion implantation method will not be impaired. Further, since heat treatment can be performed in a non-oxidizing atmosphere, crystal defects do not occur on the surface of the epitaxial layer (24).

In addition, the thick oxide film (37) in this step is formed by the nitride film and P in the next step.
It is intended to prevent the SG film from reacting into glass and reducing the thickness of the dielectric thin film (36) during etching.

Next, as shown in FIG. 1H, an oxide film (37) on the surface of the base region (31) and the surface of the island (25) of the NPN transistor is opened, and phosphorus (P) is used as a mask with this oxide film (37). Deposit and remove the Ring Lath (PSG) film. After that, a non-doped or phosphorus-doped oxide film is deposited on the entire surface, and phosphorus (P) is driven in by applying heat treatment to the entire substrate (21) to form the emitter region (38) and collector contact region (39) of the NPN transistor. Form to a depth. The drive-in of this process controls h _FE (current amplification factor) of the NPN transistor.

Next, as shown in FIG. 1I, a resist pattern made of a negative or positive photoresist is formed on the oxide film (37),
Dielectric thin film by wet or dry etching (36)
The upper oxide film (37) is removed, and a contact hole for electrical connection is opened in a desired portion of the oxide film (37). Then, an aluminum layer is formed on the entire surface of the substrate (21) by a well-known evaporation or sputtering technique, and the aluminum layer is patterned again to form an electrode (40) having a desired shape and an upper electrode (41) on the dielectric thin film (36). ) Is formed.

According to the above-described manufacturing method of the present application, the lower electrode region of the MIS type capacitor is formed by utilizing the upper diffusion layer (26) forming process of upper and lower separation.
Since (28) is formed, the dielectric thin film (36) can be formed prior to emitter diffusion. Also, the formation of the resistance region (31) by ion implantation can be performed prior to the emitter diffusion. Therefore, phosphorus for forming the emitter region (38)
It is not necessary to place a heat treatment for incorporating an optional device between the deposit of (P) and the drive-in of phosphorus (P), and the _hFE control of the NPN transistor is immediately performed from the state where phosphorus (P) is initially diffused by the deposit. it is possible to shift to a heat treatment for, of the NPN transistor h _FE
Can be significantly suppressed. Further, since the heat treatment conditions for the emitter region (38) can be unified regardless of whether or not the optional device is incorporated, the process control for each model becomes extremely easy.

Then, according to the present invention, the thick oxide film (27) generated at the time of forming the isolation region is removed and the thin oxide film (29) is attached again, so that ion implantation is performed by penetrating the thin oxide film (29). It can be carried out. Therefore, it is not necessary to use an expensive device such as an RIE device for etching the thick oxide film (27) with high precision, and it is possible to prevent crystal defects on the surface of the epitaxial layer (24).

Further, since the surface of the base region (32) is covered with the thin oxide film (29), the drive-in of the base region (32) can be postponed, and by doing so, the CVD oxide film (3
It can be shared with baking in 7). Further CV
Since the surface concentration of the base region (32) is hardly reduced by the D oxide film (37), the impurity concentration of the base region (32) is set to 200 to
By setting a relatively low value of 400Ω / □, it is possible to further suppress the variation of h _FE .

Moreover, it is possible to form the lower electrode region (28) without using a single process, and to form the base region (32) and the resistance region.
(31) No etching process is required to form a thin oxide film (2
By using 9), the process can be standardized, and the process can be simplified.

By the way, the lower electrode region (28) of the MIS type capacitor of the present application takes various embodiments. FIG. 2 shows a second embodiment of the present application, which is an example applied to an IC of a normal separation type rather than upper and lower separation. As is clear from the figure, the lower electrode region (28) of the MIS type capacitor is formed at the same time as the formation of the isolation region (42), and the entire bottom surface of the lower electrode region (28) is made to collide with the buried layer (22). Has a structure in which the lower electrode of the MIS type capacitor is separated from the ground potential of the substrate (21). Further, FIG. 3 shows the third of the present application.
The present invention will be described with reference to FIG. 4 and an example applied to an IC having an N ⁺ type collector low resistance region (41) for the purpose of reducing V _CE (sat) of the NPN transistor. As is clear from the figure, the lower electrode region (28) of the MIS type capacitor may be formed at the same time when the collector low resistance region (43) is formed, and then the process of FIG. 1C may be performed.

(G) Effect of the Invention As described above, according to the present invention, there is provided a method of manufacturing a semiconductor integrated circuit capable of solving the difficulty of h _FE control of an NPN transistor due to incorporation of a MIS type capacitor and a resistance element by ion implantation. It has the advantage that it can. In addition, since the heat treatment conditions for the emitter region (38) can be unified, the process control for each model can be simplified, and there is also the advantage that it is possible to heat treat different types of wafers at the same time and to produce multiple models in small quantities. Have.

Further, according to the embodiment of the present application, a single step is not required for forming the lower electrode region (28) of the MIS type capacitor, and etching is performed without deteriorating the accuracy of the etching process of the base region (32) and the resistance region (31). Can be omitted, and the heat treatment can be made common by using a thin oxide film (29), which also has an advantage that the process can be simplified.

[Brief description of drawings]

1A to 1I are sectional views for explaining the present invention,
2 and 3 are sectional views for explaining the second and third embodiments of the present invention, and FIG. 4 is a sectional view for explaining the conventional example. (21) is a P-type substrate, (28) is a lower electrode region of MIS-type capacitor, (29) is a thin oxide film, (31) is a resistance region, (32) is a base region of an NPN transistor, and (36) is MIS. A type capacitor dielectric thin film, (38) is an emitter region of an NPN transistor.

Claims (1)

[Claims] 1. A step of forming a buried layer of opposite conductivity type in a desired region of a semiconductor substrate of one conductivity type, a step of forming an epitaxial layer of opposite conductivity type on the substrate, and a separation for separating the epitaxial layer. Forming the lower electrode region of the MIS-type capacitor at the same time as forming the region or at the same time as forming the collector low resistance region of the vertical bipolar transistor; removing the thick oxide film formed on the surface of the epitaxial layer; A step of forming a new relatively thin oxide film on the surface of the epitaxial layer; a resistance element for forming a base region of a transistor on the thin oxide film; and a resistance element having a resistance portion and contact portions at both ends of the resistance portion. And a step of forming a selective mask for forming an impurity, and a step of ion-implanting impurities of one conductivity type from above the thin oxide film twice. One of the two ion implantations has a dose amount that determines the resistivity of the resistance portion, and the other has a dose amount that is added to the one dose amount to determine the resistivity of the base region of the transistor. Then, both the one and the other ion implantations are performed on the entire surface of the base region of the transistor and the contact portion of the resistance element, and only the one ion implantation is performed on the resistance portion using a selection mask. And a step of forming an opening part of which is exposed on the surface of the lower electrode region, and forming a dielectric thin film of the MIS type capacitor made of a silicon nitride film by a CVD method so as to cover the opening part, Selective diffusion of impurities of opposite conductivity type to the surface of the base region to form an emitter region of the bipolar transistor, covering the entire surface with an electrode material and patterning the same And a step of forming an upper electrode covering the dielectric thin film and an electrode contacting each diffusion region.