JPH061807B2 - Method for manufacturing semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a method of manufacturing a semiconductor integrated circuit in which a MIS-type capacitor is incorporated, in which h _FE of an NPN transistor is facilitated.

(B) Conventional Technology A bipolar IC is mainly composed of a vertical NPN transistor in which a base and an emitter are double-diffused on the surface of a semiconductor layer serving as a collector. Therefore, the base and emitter diffusion steps for manufacturing the NPN transistor are indispensable steps, and a high-concentration buried layer forming step for reducing collector series resistance, an epitaxial layer growing step, and junction separation for each element. This is a step (basic step) essential for manufacturing a bipolar IC along with the isolation region forming step, the electrode forming step for electrical connection, and the like.

On the other hand, there is a demand for incorporating other elements such as a PNP transistor, a resistor, a capacitor, and a Zener diode on the same substrate in view of circuit requirements. In this case, needless to say, it is preferable to divert the basic process as much as possible from the viewpoint of simplifying the process. However, in the base and emitter diffusion process, since various conditions are set with the characteristics of the NPN transistor as the most important factor, integration is often difficult only by the basic process. So, basic NP
A new process may be added for the purpose of incorporating another element or improving the characteristics of another element without forming the N-transistor. For example, a P ⁺ diffusion process for forming an anode region for controlling the Zener voltage of a Zener diode with the cathode region by the emitter diffusion, an R diffusion process for forming a resistance region having a specific resistance different from that of the base region, and an implantation process. A resistance forming step, a nitride film forming step for forming a nitride film capacitor that can provide a larger capacity than that of a MOS type, and a collector low resistance region forming step for further reducing the collector series resistance of an NPN transistor are all included in it. This is a process (optional process) in which it is determined whether or not to add the bipolar IC by considering the use and purpose and cost of the bipolar IC.

FIG. 3 shows a MIS type capacitor formed by using the above optional process. In the figure, (1) is a P-type semiconductor substrate,
(2) is an N type epitaxial layer, (3) is an N ⁺ type buried layer, (4) is a P ⁺ type isolation region, (5) is an island, and (6) is an N ⁺ type lower electrode region by emitter diffusion. , (7) is a silicon nitride film (Si ₃ N ₄ ) as a high dielectric constant insulator, (8) is an upper electrode made of an aluminum material, (9) is an oxide film, and (10) is an electrode.
A MIS type capacitor using a nitride film is described in, for example, Japanese Patent Laid-Open No. 60-244056.

(C) Problems to be Solved by the Invention However, the conventional MIS-type capacitor has an N-type lower electrode.
Since the emitter region of the PN transistor is used, it is necessary to deposit the N-type impurity for forming the emitter region, form a nitride film, and then drive-in the N-type impurity. Then, the 80 used for the nitride film depot
Since heat treatment at around 0 ° C diffuses the emitter region, NP
The variation in h _FE (current amplification factor) of the N-transistor is large, and it is difficult to control it.

Also, since it is necessary to change the heat treatment conditions for the emitter region depending on whether or not the optional process necessary for forming the nitride film is added, it is necessary to control the process for each model, and there is a drawback that the control cannot be standardized. It was

(D) Means for Solving the Problems The present invention has been made in view of the above drawbacks, and includes a step of simultaneously forming a collector low resistance region (26) of an NPN transistor and a lower electrode region (27) of a MIS type capacitor. , Lower electrode area (27)
A step of patterning the surface oxide film (29) to partially expose it; a step of selectively introducing N-type impurities using the pattern; and a dielectric on the exposed surface of the lower electrode region (27). The method is characterized by comprising a step of forming a thin film (30) and a step of forming an emitter region (31) of an NPN transistor by diffusion after forming the dielectric thin film (30).

(E) Function According to the present invention, the NPN is used as the lower electrode of the MIS type capacitor.
Since the collector low resistance region (26) of the transistor is used, the nitride film can be deposited before the emitter diffusion process, and the heat treatment is performed so that the h _FE of the NPN transistor after the emitter region (31) is formed is varied. Can be eliminated. Further, since the N-type impurities are ion-implanted or deposited using the oxide film pattern for the nitride film (Si ₃ N ₄ ) deposition, the resistance component of the lower electrode region (27) under the dielectric thin film (30) is reduced. it can.

(F) Embodiment Hereinafter, one embodiment of the present invention will be described in detail with reference to FIGS. 1A to 1F.

First, as shown in FIG. 1A, a P-type silicon semiconductor substrate (2
The surface of 1) is selectively doped with N-type impurities such as antimony (Sb) or arsenic (As) to form an N ⁺ -type buried layer (22).
(21) N-type epitaxial layer (2
3) is laminated.

Next, as shown in FIG. 1B, the buried layer is formed by selectively diffusing boron (B) from the surface of the epitaxial layer (22).
P ⁺ -type isolation regions (24) are formed so as to surround the (22) and penetrate the epitaxial layer (23). The epitaxial layer (23) surrounded by the isolation region (24) becomes an island (25) for forming each circuit element.

Then, again, phosphorus is removed from the surface of the epitaxial layer (23).
By selectively diffusing N-type impurities such as (P),
The collector low resistance region (26) of the N ⁺ type NPN transistor reaching the buried layer (22) from the surface of the island (25) and the MIS
A lower electrode region (27) of the mold capacitor is formed. Since the collector low resistance region (26) is formed by saturation diffusion, the impurity concentration on its surface is about 10 ¹⁹ atoms · cm ⁻² .

Next, as shown in FIG. 1C, the base region (28) of the NPN transistor is formed on the surface of the island (25) by selectively ion-implanting or diffusing boron (B) from the surface of the epitaxial layer (23). .

Further, the thermal oxide film or the CVD oxide film (29) on the surface of the epitaxial layer (23) is patterned to form the lower electrode region (27).
An oxide film pattern having an opening is formed on a part of the surface of the lower electrode region (2
7) Selectively ion-implant or deposit N-type impurities on the surface. The N-type impurities include phosphorus (P) and antimony
(Sb), arsenic (As), etc. are selected, and the ion-implanted or deposited impurities do not diffuse deeply. Lower electrode area in this process
(27) The concentration of impurities on the surface is improved to about 10 ²⁰ atoms · cm ⁻² . Therefore, the resistance component of the lower electrode region (27) can be reduced.

Next, as shown in FIG. 1D, a silicon nitride film (Si ₃ N ₄ ) having a film thickness of several hundred to several thousand hundred Å is deposited on the entire surface of the epitaxial layer (23) by using a technique such as atmospheric pressure CVD. The dielectric thin film (30) covering the surface of the exposed lower electrode region (27) is formed by selectively removing the silicon nitride film using a technique such as dry etching. Since the silicon nitride film (Si ₃ N ₄ ) has a higher dielectric constant than the silicon oxide film (SiO ₂ ), it is possible to form a large capacity. After that, the dielectric thin film (3
An oxide film (29) is deposited by the CVD method so as to cover 0).

Next, as shown in FIG. 1E, the oxide film (29) on the surface of the base region (28) of the NPN transistor is selectively opened, and phosphorus (P) is selectively diffused using this oxide film (29) as a mask. As a result, an N ⁺ type emitter region (31) is formed.

Next, as shown in FIG. 1F, a resist pattern made of a negative or positive photoresist is formed on the oxide film (29),
The oxide film (29) on the dielectric thin film (30) is removed, and a contact hole for electrical connection is opened in a desired portion of the oxide film (29) by wet or dry etching. And
An aluminum layer is formed on the entire surface of the substrate (21) by a known vapor deposition or sputtering technique, and the aluminum layer is patterned to form an electrode (32) having a desired shape and a dielectric thin film (3).
Form the upper electrode (33) on the (0).

According to the manufacturing method of the present application described above, the collector low resistance region
Since the lower electrode of the MIS type capacitor is formed simultaneously with the diffusion of (26), it is possible to coexist efficiently without using a single process,
The manufacturing process of the dielectric thin film (30) can be installed before the emitter diffusion process. Then, there is no need to arrange a heat treatment for forming the MIS type capacitor between the phosphorus (P) deposit for forming the emitter region (31) and the phosphorus (P) drive-in, and the phosphorus (P) is initially formed by the deposit. From the diffused state, a heat treatment (drive-in) process for controlling h _FE (electrode amplification factor) of the NPN transistor can be immediately performed. Therefore, there is little variation in the h _FE of the NPN transistor, h _FE that due to the fact that incorporating the MIS capacity
The difficulty of control can be eliminated. In addition, the emitter area is different between models that incorporate MIS-type capacitors and those that do not.
Since the heat treatment conditions of (30) can be unified, the process control for each model becomes extremely easy.

And further, the present invention provides for the lower electrode region immediately before the nitride film deposition.
(27) Since N-type impurities are introduced into the surface, the resistance component of the lower electrode can be reduced, and the voltage dependence and hysteresis characteristics of the MIS-type capacitance can be reduced. Moreover, since the N-type impurities are introduced using the mask pattern for forming the dielectric thin film 30, the process can be simplified.

(G) Effect of the Invention As described above, according to the present invention, there is an advantage that the low saturation type NPN transistor and the high performance MIS type capacitor can coexist efficiently. Further, by performing the nitride film deposition before forming the emitter region (31), there is little variation in h _FE of the NPN transistor, so that it is possible to provide a method for manufacturing a semiconductor integrated circuit whose control is extremely easy. . Since the processing conditions for the emitter region (31) can be unified between the model incorporating the MIS type capacitor and the model not incorporating it, the process control for each model can be simplified, and wafers of different models can be diffused in the same manner. It also has the advantage of being able to carry out heat treatment in a furnace in small quantities on multiple models.

Furthermore, since N-type impurities are introduced into the surface of the lower electrode region (27) immediately before the nitride film deposition, a MIS-type capacitor having good characteristics with both small voltage dependence and hysteresis can be incorporated, and patterning can be done only once. There is also an advantage that the process can be simplified.

[Brief description of drawings]

1A to 1F are sectional views for explaining the present invention, and FIG. 2 is a sectional view for explaining a conventional example. (21) is a P-type semiconductor substrate, (27) is a lower electrode region of a MIS-type capacitor, (28) is a P-type base region of an NPN transistor, (30) is a dielectric thin film, (31) is N ⁺ of an NPN transistor. The type emitter region (33) is the upper electrode of the MIS type capacitor.

Claims (1)

[Claims] 1. A method of manufacturing a semiconductor integrated circuit, wherein a bipolar transistor and a MIS type capacitor are formed on electrically isolated islands, respectively, wherein a buried layer of opposite conductivity type is formed on the surface of a semiconductor substrate of one conductivity type. A step of forming a reverse conductivity type epitaxial layer on the substrate, a collector low resistance of the bipolar transistor connected to the buried layer by diffusing a reverse conductivity type impurity from the surface of the epitaxial layer. A region and a lower electrode region of the MIS-type capacitor at the same time, a step of forming an opening in the insulating film covering the surface of the epitaxial layer to expose a part of the surface of the lower electrode region, Ion-implanting an impurity of opposite conductivity type into the surface of the lower electrode region using an opening, and sili- con by a CVD method so as to cover the opening. Forming a derivative thin film of the MIS-type capacitive element formed of a nitride film, selectively diffusing impurities of opposite conductivity type on the surface of another island where a bipolar transistor is to be formed, and A step of forming an emitter region, and a step of covering the entire surface with an electrode material and patterning the same to form an upper electrode covering the dielectric thin film and an electrode contacting each diffusion region. A method of manufacturing a semiconductor integrated circuit, comprising: