JPH0583192B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (A) Field of Industrial Application The present invention relates to a manufacturing method that facilitates _hFE control of an NPN transistor in a semiconductor integrated circuit incorporating an MIS type capacitive element.

(b) Conventional technology A bipolar IC is mainly composed of a vertical NPN transistor in which a base and an emitter are double-diffused on the surface of a semiconductor layer that serves as a collector. Therefore, the base and emitter diffusion processes for manufacturing the NPN transistor are essential processes, as well as the high-concentration buried layer formation process and epitaxial layer growth process to reduce the collector series resistance, and the junction separation of each element. This is an essential process (basic process) for manufacturing bipolar ICs, along with the isolation region formation process for electrical connections and the electrode formation process for electrical connections.

On the other hand, due to circuit requirements, other elements, such as
There is a demand for incorporating PNP transistors, resistors, capacitors, Zener diodes, etc. on the same board. In this case, it goes without saying that it is preferable to utilize the basic steps as much as possible in terms of process simplification. However, since the conditions for the base and emitter diffusion steps are set with the most important consideration given to the characteristics of the NPN transistor, it is often difficult to integrate the base and emitter diffusion steps using only the basic steps. Therefore,
Not aimed at forming basic NPN transistors,
A new process may be added for the purpose of incorporating other elements or improving the characteristics of other elements. For example, a P ⁺ diffusion process to form an anode region that controls the Zener voltage of a Zener diode with the cathode region by the emitter diffusion, an R diffusion process to form a resistance region with a different resistivity from the base region, and an implant resistor. forming process,
These include the nitride film formation process to form a nitride film capacitor that provides a larger capacitance than the MOS type, and the collector low resistance region formation process to further reduce the collector series resistance of NPN transistors, all of which are used for bipolar ICs. This is a step (optional step) in which it is decided whether or not to add it based on consideration of the purpose, purpose, and cost.

FIG. 4 shows an MIS type capacitor using the above optional steps. In the figure, 1 is a P-type semiconductor substrate, 2 is an N-type epitaxial layer, 3 is an N ⁺ type buried layer, 4 is a P ⁺ type isolation region, 5 is an island, and 6 is an N ⁺ type lower part by emitter diffusion. In the electrode region, 7 is a silicon nitride film (Si ₃ N ₄ ) as a high dielectric constant insulator, 8 is an upper electrode made of an aluminum material, 9 is an oxide film, and 10 is an electrode. Furthermore, as an MIS type capacitor using a nitride film, for example,
-Described in Publication No. 244056.

(c) Problems to be solved by the invention However, since conventional MIS type capacitors use the emitter region of the NPN transistor as the lower electrode, a nitride film is formed after depositing N-type impurities to form the emitter region. After that, drive-in of N-type impurities must be performed. As a result, the heat treatment at around 800°C used to deposit the nitride film diffuses the emitter region, resulting in large variations in the h _FE (current amplification factor) of NPN transistors, which is difficult to control.

In addition, it is necessary to change the heat treatment conditions of the emitter region depending on whether an optional process necessary for forming the nitride film is added, which requires process control for each model, which has the disadvantage that management cannot be standardized. .

(d) Means for Solving the Problems The present invention has been made in view of the above-mentioned drawbacks, and utilizes the isolation region 24 as the lower electrode of the MIS type capacitor and selects boron (B) from the surface of the epitaxial layer 23. A step of forming the isolation region 24 and the first lower electrode region 26 by diffusing boron.
Base region 2 by selectively introducing (B)
7 and a second lower electrode region 28 overlapping with the first lower electrode region 26;
A nitride film (Si ₃ N ₄ ) is deposited on the surfaces of the lower electrode regions 26 and 28 of the dielectric thin film 3 of the MIS type capacitor.
The feature is that after forming 0, the emitter of the NPN transistor is diffused.

(E) Effect According to the present invention, since the separation region 24 is used as the lower electrode of the MIS type capacitor, the nitride film can be deposited before the emitter diffusion step, and the NPN transistor after the emitter region 31 is formed can be deposited. h Heat treatment that causes _FE variation can be eliminated. Also,
The second and lower electrode regions 2 using base diffusion process
8, the surface concentration of the lower electrode can be improved.

(F) Embodiment Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows a cross-sectional structure of a semiconductor integrated circuit according to the present invention, in which 21 is a P-type silicon semiconductor substrate, 22 is a plurality of N ⁺ type buried layers provided on the surface of the substrate 21, 2
3 is an N-type epitaxial layer laminated on the entire surface of the substrate 21, and 24 is an epitaxial layer 23.
P ⁺ type isolation region passing through, 25 is isolation region 2
4, an island in which the epitaxial layer 23 is formed in the form of an island, and 26 is a P layer that reaches from the surface of the epitaxial layer 23 to the buried layer 22, which is simultaneously formed on the surface of one island 25 using the diffusion process of the isolation region 24. The first lower electrode region 27 of ^{the +} type MIS type capacitor is formed on the surface of the other island 25.
28 is a P-type base region of the NPN transistor; 28 is a second lower electrode region formed on the surface of one island 25, overlapping the first lower electrode region 26 and simultaneously with the base region 27; 29 is the epitaxial layer 23;
Silicon oxide film (SiO ₂ ) covering the surface, 30 is the first
and the dielectric thin film of the MIS type capacitance deposited on the surfaces of the second lower electrode regions 26 and 28; 31 is the N ⁺ type emitter region of the NPN transistor formed on the surface of the base region 27; 32 is the NPN formed on the surface of the island 25; N ⁺ for extracting the collector of the transistor
33 is an electrode made of aluminum material that is in ohmic contact with each region through a contact hole; 34 is a first and second lower electrode region 26 on the dielectric thin film 30;
This is an upper electrode provided to face 28. The entire bottom of the first lower electrode region 26 is formed so as to be in contact with the buried layer 22, and the first lower electrode region 26 is electrically insulated from the ground potential of the substrate 21 by the buried layer 22. Therefore, since the MIS type capacitor is electrically independent, there are no restrictions on the circuit configuration.

According to the structure of the present application described above, since the first lower electrode region 26 formed at the same time as the separation region 24 is used as the lower electrode of the MIS type capacitor, the dielectric thin film 3
0 formation step can be placed before the emitter diffusion step. Furthermore, since the second lower electrode region 28 was provided to overlap the first lower electrode region 26,
It is possible to improve the impurity concentration on the surface of the lower electrode and lower the resistance of the lower electrode.

Below, the manufacturing method of the present application is shown in FIGS. 2A to 2F.
Explain using.

First, as shown in FIG. 2A, the surface of a P-type silicon semiconductor substrate 21 is selectively doped with N-type impurities such as antimony (Sb) or arsenic (As) to form N ⁺
A mold embedding layer 22 is formed to a thickness of 5 to 50% over the entire surface of the substrate 21.
A 10μ N-type epitaxial layer 23 is laminated.

Next, as shown in FIG. 2B, by selectively diffusing boron (B) from the surface of the substrate 21, ^P A separation region 24 is formed. The epitaxial layer 23 surrounded by the isolation region 24 becomes an island 25 for forming each circuit element. At the same time, boron (B) in the separation region 24 diffusion process
is also diffused into a region corresponding to the buried layer 22 on the surface of the island 25, thereby forming a first lower electrode region 26 reaching the buried layer 22 from the surface of the epitaxial layer 23. Since the isolation region 24 is formed by saturated diffusion and penetrates the epitaxial layer 23, the impurity concentration on its surface is approximately 10 ¹⁸ atoms·cm ⁻² .

Next, as shown in FIG. 2C, boron (B) is selectively ion-implanted or diffused into the surface of the island 25 other than the island 25 on which the first lower electrode region 26 is formed, thereby forming an NPN transistor. A base region 27 is formed to serve as a base. At the same time, boron (B) is diffused onto the surface of one island 25 so as to overlap with the first lower electrode region 26 to form a second lower electrode region 28 of an MIS type capacitor.

Next, as shown in FIG. 2D, an epitaxial layer 2 is formed.
The oxide film 29 on the surface of the epitaxial layer 23 is selectively etched away to expose a part of the surfaces of the first and second lower electrode regions 26 and 28, and the entire surface of the epitaxial layer 23 is etched using a technique such as atmospheric pressure CVD. Film thickness from several hundred to several thousand Å
A silicon nitride film (Si ₃ N ₄ ) is deposited. Since a silicon nitride film exhibits a higher dielectric constant than a silicon oxide film, it is possible to form a large capacitance.
Then, a well-known resist pattern is formed on the surface of the silicon nitride film, and a dielectric thin film 30 is formed to cover the exposed surfaces of the first and second lower electrode regions 26 and 28 using techniques such as dry etching. . Thereafter, an oxide film 29 is deposited by CVD so as to cover the dielectric thin film 30.

Next, as shown in FIG. 1E, holes are opened in the oxide film 29 on the surface of the base region 27 and the surface of the island 25 of the NPN transistor, and phosphorus (P) is selectively diffused using the oxide film 29 as a mask to form an N ⁺ An emitter region 31 and a collector contact region 32 are formed.

Next, as shown in FIG. 2F, a resist pattern of negative or positive photoresist is formed on the oxide film 29, the oxide film 29 on the dielectric thin film 30 is removed, and then wet or dry etching is performed. A contact hole for electrical connection is opened in a desired portion of the oxide film 29. And board 2
1. An aluminum layer is formed on the entire surface by a well-known vapor deposition or sputtering technique, and this aluminum layer is patterned again to form an electrode 2 in a desired shape.
9 and an upper electrode 34 on the dielectric thin film 30.

According to the manufacturing method of the present application described above, since the diffusion process of the isolation region 24 and the diffusion process of the base region 27 of the NPN transistor are used to form the lower electrode of the MIS type capacitor, no additional process is required. The manufacturing process of the MIS type capacitive dielectric thin film 29 can be installed before the emitter diffusion process. Then, there is no need to perform heat treatment for forming MIS type capacitance between the phosphorus (P) deposit for forming the emitter region 31 and the phosphorus (P) drive-in, and the phosphorus (P) is Immediately from the spread state
Heat treatment (drive-in) process can be performed to control the h _FE (current amplification factor) of NPN transistors. Therefore, h _FE of NPN transistor
There is little variation in _FE , which eliminates the difficulty of hFE control due to the built-in MIS type capacitor.
Furthermore, since the heat treatment conditions for the emitter region 30 can be unified for models that incorporate MIS type capacitors and models that do not, process management for each model becomes extremely easy.

The present invention is not limited to the embodiment shown in FIG. 1, but can also be applied to semiconductor integrated circuits using upper and lower separation techniques. Furthermore, in the case where the upper and lower separation techniques are used, the upper diffusion layer 36 of the upper and lower separation regions 35 is not used in both the upper and lower regions as in the second embodiment shown in FIG.
It is also conceivable to form the first lower electrode region 26 by using only the same. In this case, since the first lower electrode region 26 does not reach the buried layer 22, electrical insulation from the substrate 21 can be achieved.

(G) Effects of the invention As explained above, according to the present invention, the MIS type capacitor is added as an optional device.
Since there is little variation in the h _FE of the NPN transistor, there is an advantage that it is possible to provide a semiconductor integrated circuit and its manufacturing method in which the h _FE of the NPN transistor can be extremely easily controlled. Moreover, the separation area 24
Since the lower electrode of the MIS type capacitor is formed using the diffusion process of the base region 27, it is possible to provide a semiconductor integrated circuit that does not require any additional process and can reduce the resistance component of the lower electrode. have In addition, since the processing conditions for the emitter area 31 can be unified for models that incorporate MIS type capacity and models that do not, process management for each model can be simplified, and wafers of different models can be processed in the same diffusion furnace. It also has the advantage of making it possible to produce a wide variety of products in small quantities when processed.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view for explaining the present invention, FIGS. 2A to 2F are cross-sectional views for explaining the manufacturing method of the present invention, and FIG. 3 is a cross-sectional view for explaining the manufacturing method of the present invention. FIG. 4 is a sectional view for explaining a conventional example. 21 is a P-type semiconductor substrate, 26 is a first lower electrode region of an MIS type capacitor, 27 is a P-type base region of an NPN transistor, 28 is a second lower electrode region of an MIS type capacitor, 30 is a dielectric thin film, 31 is the N ⁺ type emitter region of the NPN transistor, and 34 is the upper electrode of the MIS type capacitor.

Claims (1)

[Claims] 1. An epitaxial layer of opposite conductivity type formed on a semiconductor substrate of one conductivity type, a buried layer of opposite conductivity type formed on the surface of the substrate, and the epitaxial layer is formed into a plurality of islands. an isolation region of one conductivity type for electrical isolation; and an isolation region of one conductivity type formed on the surface of one island simultaneously with the formation of the isolation region.
A first lower electrode region of an MIS type capacitor, a base region of one conductivity type of a vertical bipolar transistor formed on the surface of another island, and a base region that overlaps with the first lower electrode region of the one island. a second lower electrode region formed simultaneously with the formation of the base region, an emitter region of opposite conductivity type of the vertical bipolar transistor formed on the surface of the base region, and a second lower electrode region formed on the surface of the base region; a dielectric thin film made of a silicon nitride film provided so as to cover a part of the area;
and an upper electrode of a MIS type capacitor formed on the dielectric film so as to oppose the second lower electrode region. 2. A step of forming a buried layer of an opposite conductivity type on the surface of a semiconductor substrate of one conductivity type, a step of forming an epitaxial layer of an opposite conductivity type on the substrate, a separation region of one conductivity type from the surface of the epitaxial layer. forming a plurality of islands by forming a plurality of islands, and forming a first lower electrode region of a MIS type capacitor on the surface of one island by the step of forming the separation region; By selectively introducing type impurities, the base region of the vertical bipolar transistor is formed on the surface of the other island, and the base region of the vertical bipolar transistor is formed on the surface of the one island.
simultaneously forming a second lower electrode region of the MIS type capacitor overlapping the lower electrode region of the lower electrode region, exposing a part of the surface of the lower electrode region;
a step of depositing a silicon nitride film to form a dielectric thin film of the MIS type capacitor, and forming an emitter of the vertical bipolar transistor by selectively thermally diffusing impurities of the opposite conductivity type onto the surface of the base region; forming a region; coating the entire surface with an electrode material and patterning it to form an upper electrode covering the dielectric thin film and an electrode contacting each diffusion region; Features: A method for manufacturing semiconductor integrated circuits.