JP2840488B2 - Semiconductor integrated circuit and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit incorporating a capacitor and a method for manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, a capacitance element incorporated in an integrated circuit uses a junction capacitance of a PN junction, a gate capacitance between a gate electrode and a diffusion layer, or a connection between an electrode wiring and an electrode wiring. The one using the capacitance of the insulating film between them is known. The one using the insulating film capacitance has an advantage that a material having a high dielectric constant can be used and there is no voltage dependency.

FIG. 8 shows a structure described in, for example, JP-A-2-226755. In the figure, (1)
Is a silicon substrate, (2) is a silicon oxide film, (3) is a polysilicon layer, (4) is an interlayer insulating film, (5) is a dielectric thin film such as a silicon nitride film (SiN), and (6) is an Al electrode. It is.

[0004]

However, in the capacitor having the above-described structure, the dielectric thin film (5) is formed so as to cover the opening of the interlayer insulating film (4). In FIG. 1A, there is a disadvantage that the dielectric thin film (5) is apt to cause disconnection and the like, and the breakdown voltage is apt to be deteriorated between the upper electrode and the lower electrode.

[0005]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned drawbacks, and has been made in view of the above-mentioned drawbacks. The present invention has been made in view of the following circumstances. Forming a silicon nitride film (SiN) to be a dielectric thin film (25) of the capacitive element (24) on the entire surface of the layer; providing an opening (34) in an interlayer insulating film (28) covering the lower electrode (23); The upper electrode (26) of the capacitive element (24) is formed so as to cover the opening (34).

[0006]

According to the present invention, since the dielectric thin film (25) extends substantially horizontally along the surface of the lower electrode (23), the step is eliminated and there is no fear of step disconnection or the like. Further, by simultaneously forming the gate electrode (15) of the MOS element (16), a silicon nitride film can be deposited on the surface of the gate electrode (15).

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment in which the present invention is applied to a Bi-CMOS integrated circuit will be described below in detail with reference to the drawings. In FIG. 1, (11) is a P-type silicon semiconductor substrate, (12)
Is an N ⁺ -type buried layer, (13) is a P ⁺ -type isolation region for junction separation of an epitaxial layer formed on the surface of the substrate (11), (14) is a LOCOS oxide film for element isolation, (1)
5) is a gate electrode of a P-channel type MOS device (16), (17) is a P-type source / drain region of the MOS device (16), and (18) is a P-type transistor of an NPN transistor (19).
Type base region, (20) is a P ⁺ type base contact region, (21) is an N ⁺ type emitter region of an NPN transistor (19), (22) is an N ⁺ type collector contact region, and (23) is a capacitive element (24). ) Lower electrode, (25)
Is a dielectric thin film, (26) is an upper electrode of the capacitive element (24), (27) is an extraction electrode of the lower electrode (23), (2)
8) is an interlayer insulating film, (29) is an Al electrode, (30) is S
iN insulating film, (31) is a polyimide-based insulating film, (32)
Is a second layer Al wiring. In the finished product, a polyimide insulating film for a jacket is further formed on the second-layer Al wiring (32).

The gate electrode (15) of the MOS device (16)
Lower electrode (23) of the capacitor (24) The R _S =. 10 to
The gate electrode (15) is formed of a polysilicon layer doped with phosphorus so as to have a resistance of 20 Ω · cm on the gate oxide film (33) in the element region surrounded by the LOCOS oxide film (14). The lower electrode (23) is disposed on the thick LOCOS oxide film (14) of about 6 to 1.0 μm. The polysilicon layer also becomes a part of the electrode wiring extending on the LOCOS oxide film (14).

The dielectric thin film (25) on the lower electrode (23)
Consists of a heat-generating silicon nitride film (Si ₃ N ₄ ) having a thickness of 100 to 300 ° by the LPCV method. This silicon nitride film has a surface of the lower electrode (23) and a gate electrode (15) of the MOS device (16). And a part of the surface of the electrode wiring by the polysilicon layer. The interlayer insulating film (28) is composed of a BPSG film heavily doped with phosphorus (P) and boron (B). After the BPSG film is deposited, it is reflowed to planarize the surface. The SiN insulating film (30) thereon is a nitride film formed by a plasma CVD method,
This is provided to compensate for the disadvantage of the SG film having poor moisture resistance.

An interlayer insulating film (28) covering the dielectric thin film (25) of the capacitive element (24) has an opening (34) having a size corresponding to the capacitance value and a contact hole for the lower electrode (23). (35) is provided. The opening (34) exposes the surface of the dielectric thin film (25) to form a contact hole (35).
Exposes the surface of the lower electrode (23) through the dielectric thin film (25).

The upper electrode (26) of the capacitive element (24)
It is provided on the dielectric thin film (25) extending substantially horizontally along the surface of the lower electrode (23) so as to cover the opening (34). The dielectric thin film (25) is an interlayer insulating film (2)
8), the upper electrode (26) is in close contact with the interlayer insulating film (28) around the side wall of the opening (34) and around the opening (34). The extraction electrode (27) of the lower electrode (23) makes ohmic contact with the lower electrode (23) via the contact hole (35). The electrical connection with the gate electrode (15) of the MOS element (16) or a part of the electrode wiring made of the polysilicon layer is made in the same manner as the extraction electrode (27) of the lower electrode (23).

According to the structure of the present invention described above, the dielectric thin film (25) of the capacitive element (24) extends substantially horizontally along the surface of the lower electrode (23), and the interlayer insulating film (25) is formed thereon. 2
Since 8) is provided, there is no step in the dielectric thin film (25).
Therefore, there is no deterioration of the breakdown voltage between the upper electrode (26) and the lower electrode (23) due to the disconnection of the dielectric thin film (25). Further, since there is no disconnection, the dielectric thin film (25) can be made thin. If the thickness can be reduced, the capacitance value per unit area can be increased.

Further, the surface of the gate electrode (15) of the MOS element (16) and a part of the electrode wiring formed by the polysilicon layer are also covered by the silicon nitride film (36), so that the gate electrode is formed by the passivation effect of the nitride film. (15)
And the like are improved in reliability. In particular, BPSG as a planarization technology
In the configuration of the present invention in which the film is used and the SiN insulating film (30) is formed by the plasma CVD method in order to compensate for the moisture resistance, hydrogen ions (H ⁺ ) unavoidably present in the SiN insulating film (30). The change (threshold trapping phenomenon) of the threshold value (V _T ) of the MOS element (16) due to the movement of
The heat-generated silicon nitride film (36) provided on the gate electrode (15) can prevent the invasion of the hydrogen ions, thereby preventing the hydrogen ions. Further, since the multi-layer wiring material (Poly-Si and Al) is used for the counter electrode sandwiching the dielectric thin film (25), the series resistance is reduced and the capacitance element (24) is used.
Characteristics can be improved, and the capacitance element (24) can be
Since it is arranged on the oxide film (14), there is no leakage current to the substrate (11), and the parasitic effect peculiar to the integrated circuit can be completely prevented.

The manufacturing method of the present invention will be described below in detail with reference to the drawings. First, an N ⁺ -type buried layer (12) and a P ⁺ -type isolation region (1) are formed on the surface of a P-type silicon semiconductor substrate (11).
3) Form the lower part and other necessary areas, and
1) An N-type epitaxial layer is formed thereon. And forming an upper portion of an isolation region (13) for forming an island region by diffusing a P-type impurity from the surface of the epitaxial layer;
Furthermore, the surface of the epitaxial layer is selectively oxidized to a film thickness of 0.8.
LOCOS oxide film (14) of ~ 1.0μ is formed and FIG.
To get the structure.

A film thickness of 500 to be a gate oxide film (18)
800 Å silicon oxide film formed by thermal oxidation
Deposit non-doped polysilicon 0.4-0.8μ thick
You. Doping impurities (phosphorus) into the deposited polysilicon
To give conductivity, and furthermore, a film is formed on the entire surface by LPCVD.
Silicon nitride film (S
i_ThreeN_FourDeposit). Polysilicon layer and silicon nitride film
Is patterned by photo-etching and LOCO
A MOS element is formed on the gate oxide film surrounded by the S oxide film (14).
The gate electrode (15) of the child (16) is formed by a LOCOS oxide film.
(14) On the lower electrode (23) of the capacitive element (24)
(FIG. 3). The method is, for example, CF _Four+ O_TwoBy gas
Continuous anisotropic etch.

The formation of a selection mask using photoresist and the ion implantation of impurities are repeated a plurality of times to form all the diffusion regions of a bipolar element such as an NPN transistor (19) and the diffusion region of a MOS element (16) (FIG. 4). ). The NPN transistor (19) includes a P-type base region (18), an N ⁺ -type emitter region (21), a P ⁺ -type base contact region (20), and an N ⁺ -type collector contact region (22). The PchMOS transistor (16) includes a gate electrode (15) formed earlier and P ⁺ -type source / drain regions (17) formed on both sides of the gate electrode (15). The source / drain region (17) of the PchMOS transistor (16) is NP
N-transistor (19) base contact region (2
0) and the source of an NchMOS transistor (not shown).
The drain region is shared with the emitter region (21) of the NPN transistor (19).

A film thickness of 1.0 is formed on the entire surface by LPCVD or the like.
A BPSG (boron phosphorus silicate glass) film having a thickness of 2.0 μm is deposited to form an interlayer insulating film (28), and the surface is flattened by reflow. Thereafter, a first resist pattern is formed, and the interlayer insulating film (28) is etched with a hydrofluoric acid buffer solution to form an opening (34) exposing the dielectric thin film (25) (FIG. 5).

After removing the first resist pattern, a second resist pattern is formed, and an interlayer insulating film (2) is formed.
8) and the dielectric thin film (25) are successively etched to form a contact hole (35) (FIG. 6). At this time,
In addition to the contact hole (35) on the polysilicon layer, a contact hole on the diffusion region of each element is formed at the same time. The etching is performed, for example, by anisotropic dry etching in a CF ₄ + O ₂ gas atmosphere.

Al or Al-Si is deposited on the entire surface and is photo-etched to form an electrode wiring (2) of each device.
9), an upper electrode (26) of the capacitive element (24), and a lower electrode extraction electrode (27) are formed (FIG. 7). According to such a manufacturing method, the gate electrode (1) of the MOS element (16) is
5) Simultaneously with formation, lower electrode (2) of capacitive element (24)
Since 3) and the formation of the dielectric thin film (25) are performed, the process can be simplified.

[0020]

As described above, according to the present invention,
Since there is no step in the dielectric thin film (25) of the capacitor (24), there is an advantage that the capacitor (24) can be provided with no withstand voltage deterioration due to disconnection of the step. Similarly, a silicon nitride film (36) is formed on the gate electrode (15) of the MOS device (16).
Has an advantage that a highly reliable element having no fluctuation in threshold value or the like can be incorporated.

Further, since the gate electrode (15) of the MOS element (16) and the lower electrode (23) of the capacitive element (24) can be formed simultaneously, there is an advantage that the process can be simplified.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view for explaining the present invention.

FIG. 2 is a first sectional view for explaining the manufacturing method of FIG. 1;

FIG. 3 is a second cross-sectional view for explaining the manufacturing method in FIG. 1;

FIG. 4 is a third cross-sectional view for explaining the manufacturing method in FIG. 1;

FIG. 5 is a fourth cross-sectional view for explaining the manufacturing method in FIG. 1;

FIG. 6 is a fifth sectional view for describing the manufacturing method in FIG. 1;

FIG. 7 is a sixth sectional view for explaining the manufacturing method in FIG. 1;

FIG. 8 is a sectional view for explaining a conventional example.

Claims (5)

(57) [Claims] 1. A semiconductor integrated circuit in which at least a capacitive element is integrated, comprising: a lower electrode of the capacitive element provided on an insulating film; a dielectric thin film of the capacitive element covering an entire surface of the lower electrode; An interlayer insulating film covering the dielectric thin film; an opening provided in the interlayer insulating film, exposing a surface of the dielectric thin film; and the lower electrode provided in the interlayer insulating film, penetrating the dielectric thin film. A semiconductor integrated circuit, comprising: a contact hole that exposes a surface of the capacitor; an upper electrode of a capacitor provided to cover the opening; and an extraction electrode that contacts the lower electrode through the contact hole. 2. A semiconductor integrated circuit in which at least an MIS type element and a capacitance element are integrated, wherein a LOCOS oxide film for element isolation, and an M disposed in an element region surrounded by the LOCOS oxide film.
A gate electrode of an OS element, a lower electrode of a capacitive element made of the same material as the gate electrode material disposed on the LOCOS oxide film, a dielectric thin film covering substantially all surfaces of the gate electrode and the lower electrode, An interlayer insulating film covering the dielectric thin film; an opening provided in the interlayer insulating film, exposing a surface of the dielectric thin film on the lower electrode; and the dielectric thin film provided in the interlayer insulating film. A contact hole for a lower electrode that penetrates and exposes a surface of the lower electrode; a contact hole that exposes a surface of a diffusion region forming each element; an upper electrode of a capacitive element formed to cover the opening; An electrode that contacts the lower electrode through a contact hole for the lower electrode, and an electrode that contacts the diffusion region through the contact hole. A semiconductor integrated circuit characterized by the above-mentioned. 3. The semiconductor integrated circuit according to claim 2, wherein said dielectric thin film is a silicon nitride film. 4. A step of forming a LOCOS oxide film for element isolation, a step of depositing an electrode material to be a gate electrode of a MOS element and a lower electrode of a capacitor on the entire surface, and a step of forming a dielectric thin film of the capacitor on the entire surface. Depositing an insulating material, and simultaneously patterning the insulating material on the electrode material to form a gate electrode of a MOS element, a lower electrode of a capacitive element on the LOCOS oxide film, and a dielectric thin film. Depositing an interlayer insulating film covering the entire surface; forming an opening in the interlayer insulating film to expose the surface of the dielectric thin film on the lower electrode by one resist process; and performing another resist process. A lower electrode contact hole that penetrates the dielectric thin film and exposes a surface of the lower electrode; and a capacitor that covers the opening by depositing and patterning an electrode material. Forming an upper electrode of an element and an electrode wiring of each element. 5. The method according to claim 3, wherein said one resist process is a wet process, and said another resist process is a dry process.