JP2000349301A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To form a small contact hole and to make fine an integrated circuit by connecting a conductive material layer and a second metal pipe at the bottom of the contact hole. SOLUTION: Wiring 112-115 are provided with lamination structure of first metal films 112 and 113 that are provided in contact on an organic material film and second metal films 114 and 115 that are provided on the film, and only the second metal films 114 and 115 are formed in contact with the inner wall and the bottom of a contact hole being provided at the organic material film. Then, since a material with Al as a main constituent is used as the first metal film, the resistance of the wiring is reduced. Also, since titanium nitride is used as the second metal film, resistivity is higher than that of aluminum but coverage to a region with recessed and projecting parts is appropriate, and at the same time the contact interface with a semiconductor layer is improved. In this manner, since the organic material is used for the interlayer insulation film and the first metal film is used as an etching mask, a smaller contact hole can be formed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure and a manufacturing method of a semiconductor device. In particular, the present invention relates to an active matrix type liquid crystal display device using a semiconductor thin film and a method for manufacturing the same. Further, the present invention can be applied to an electro-optical device having such a display device.

[0002] In this specification, all devices that can function by utilizing semiconductor characteristics are called semiconductor devices. Therefore, the semiconductor device described in the claims includes not only a single semiconductor element such as a TFT, but also a semiconductor circuit or an electro-optical device including the semiconductor element, and an electric device having the same as a component. . A typical example of the semiconductor element is a thin film transistor (TFT). Other examples include an insulated gate field effect transistor (IGFET), a thin film diode, an MIM element, and a varistor element.

[0003]

2. Description of the Related Art In recent years, a technique for manufacturing a semiconductor device in which a semiconductor thin film is formed on an insulating substrate, for example, a semiconductor device using a semiconductor element such as a thin film transistor (TFT) has been rapidly developed. The reason is that the demand for liquid crystal display devices (typically, active matrix liquid crystal display devices) has increased. The active matrix type liquid crystal display device displays an image by controlling the charge flowing into and out of tens to millions of display pixels arranged in a matrix by the switching elements of the display pixels.

[0004] In addition, semiconductor devices include active matrix circuits, ICs, ULSIs, and the like formed using TFTs and the like.
In recent years, integrated circuits such as VLSI have been developed. In recent years, these integrated circuits have tended to be more and more miniaturized, and processing dimensions in the submicron region are required.

Therefore, attempts have been made to reduce the size (wiring width, channel width, contact hole diameter, etc.) of each part of a semiconductor element in an integrated circuit. In particular, the necessity of making an electrical connection at the bottom of a contact hole having a small diameter has been increased by a miniaturization technique and a multilayer wiring technique.

Conventionally, an insulating film (such as a silicon oxide film or a silicon nitride film) formed by a CVD method is often used as an interlayer insulating film, and a contact hole is formed by a dry etching method or a wet etching method. I have.

For example, when a silicon oxide film is used as a first interlayer insulating film of a thin film transistor, a contact hole is formed by a wet etching method in view of the selectivity between the interlayer insulating film and the semiconductor layer and the ease of operation. Is used. When the dry etching method is used, the semiconductor layer mainly containing silicon and the silicon oxide film have the same main constituent,
There is a problem that a semiconductor layer having a low selectivity and a small thickness is simultaneously removed.

[0008] However, when a contact hole smaller than the conventional one is to be formed, the overetching is inevitably generated in the wet etching method because of the isotropic etching, which hinders miniaturization. For example, when an attempt was made to form a contact hole having a diameter of 2 μm, a contact hole having a diameter of about twice or more was formed, depending on the film thickness and the like.

The present invention particularly relates to a method of forming a contact hole (typically, 2 to 3 μm or less) smaller than a conventional one in a method of manufacturing a thin film transistor in a submicron region.

[0010]

According to the present invention, an organic material is used for an interlayer insulating film, and a contact hole is formed in the interlayer insulating film made of an organic material by dry etching.

Conventionally, when a resist mask is used in a dry etching method, it is difficult to obtain a selectivity between an organic material film and a resist mask because the constituent components are similar, so that a contact hole is formed, especially a minute contact hole. It was difficult to form. Therefore, the use of a resist mask for forming a contact hole provided in an interlayer insulating film made of an organic material has been avoided.

An object of the present invention disclosed in the present specification is to solve the above problem and form a minute contact hole to miniaturize an integrated circuit.

[0013]

The structure of the present invention disclosed in this specification comprises an interlayer insulating film made of an organic material on a conductive material layer, and a first metal layer on the interlayer insulating film. ,
A second metal layer on the first metal layer, wherein the conductive material layer and the second metal layer are connected at a bottom of a contact hole provided in the interlayer insulating film; A semiconductor device characterized by the above-mentioned.

That is, the above structure is characterized in that the conductive material layer and the second metal layer are in contact with each other at the bottom of a contact hole provided in the interlayer insulating film and the first metal layer. And

Still another aspect of the present invention is an interlayer insulating film made of an organic material on a thin film transistor, a first metal layer on the interlayer insulating film, and a second metal layer on the first metal layer. And a source or drain region of the thin film transistor and the second metal layer are connected at a bottom of a contact hole provided in the interlayer insulating film.

That is, as shown in FIG.
A source region 105 of the thin film transistor and the second metal layer 114 are in contact with each other at a bottom of a contact hole provided in the interlayer insulating film 111 and the first metal layer 112,
The drain region 106 of the thin film transistor is in contact with the second metal layer 115 at the bottom of a contact hole provided in the first interlayer insulating film 111 and the first metal layer 113.

As the first metal layer or the second metal layer in each of the above structures, a conductive material can be used. For example, Al, Ta, Ti, Cr, W,
A material layer containing Mo or silicon to which conductivity is imparted as a main component or a stacked film thereof can be used. Note that it is preferable that the first metal layer be formed of aluminum having a low resistance or a material containing aluminum as a main component.

Further, it is preferable that the second metal layer is made of titanium which is a material having good contact characteristics or a material containing titanium as a main component.

In each of the above structures, the interlayer insulating film is made of polyimide, polyimide amide, polyamide, acrylic,
It is characterized by being made of an organic resin material containing BCB (benzocyclobutene) as a main component.

Further, in order to realize the above configuration, the configuration of the present invention includes a step of forming a thin film transistor on an insulating surface;
Forming an interlayer insulating film made of an organic material over the thin film transistor, forming a first metal film over the interlayer insulating film, patterning the first metal film, Forming a metal layer of, and etching the interlayer insulating film using the first metal layer as a mask;
Forming a contact hole, forming a second metal film covering the first metal layer and the contact hole, patterning the first metal layer and the second metal film, Forming a wiring having a part of a laminated structure.

Further, according to another aspect of the invention, a step of forming a first material layer having conductivity on an insulating surface and forming an interlayer insulating film made of an organic material over the first material layer are provided. Performing a step of forming a first metal film covering the interlayer insulating film; patterning the first metal film to form a first metal layer; Forming a contact hole by etching the interlayer insulating film using the mask as a mask; forming a second metal film covering the first metal layer and the contact hole; Forming an inorganic insulating film over the film, and patterning the first metal layer, the second metal film, and the inorganic insulating film to form a wiring having an inorganic insulating layer on an upper surface And a second material having conductivity in contact with the wiring Forming a, the inorganic insulating layer as a dielectric, a manufacturing method of a semiconductor device characterized by having the steps of forming a capacitor between the second material layer and the wiring.

In each of the above structures, the inorganic insulating film is
It is characterized by being formed by a CVD method.

Further, in each of the above structures, the first metal film and the second metal film are formed by a sputtering method.

Further, in each of the above structures, the step of etching the interlayer insulating film and forming a contact hole is performed by a dry etching method.

In this specification, the film immediately after the film formation is called a "film", and the patterned film is called a "layer".

[0026]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIG.

In the structure of the present invention, a material made of an organic material is used as an interlayer insulating film covering the switching element and each wiring, and a mask made of a metal film is used.
It is characterized in that a contact hole is formed by a dry etching method.

In the structure of the present invention, at least a part of the wiring (112 to 115) existing on the organic material film has a laminated structure [first metal layer (lower layer) / second metal layer (upper layer). )]. The first metal layers (112, 1
The region where 13) is formed has at least a laminated structure. Further, the wiring inside the contact hole is not formed in a laminated structure, but is formed of the second metal layer (114, 115).
It is in contact with and electrically connected to the source region 106 or the drain region 105.

In the structure of the present invention, the first metal layer (11
2, 113) or the second metal layer (114, 115) is made of a conductive material. For example, Al,
A material layer containing Ta, Ti, Cr, W, Mo, TiN, or the like as a main component or a stacked film thereof can be used. Note that the first metal layer is made of a low-resistance material such as aluminum, and the second metal layer is a material that does not diffuse from the contact interface due to heat treatment after film formation and has good coverage, for example, It is preferable to use a material containing titanium as a main component.

In the present invention, the insulating substrate, each wiring and the semiconductor element (TFT) formed on the substrate, which exist under the interlayer insulating film (111, 116, 118) made of an organic material, have any structure. For example, top gate type (planar type, coplanar type, stagger type) or bottom gate type (channel etch type, channel stop type)
However, it is applicable.

Next, the step of forming a contact hole according to the present invention will be described below with reference to FIGS.

First, each defeat or semiconductor element is formed on a substrate, and polyimide, polyimide amide, polyamide,
A flat first interlayer insulating film 111 made of an organic material such as acrylic or BCB (benzocyclobutene) is formed. In addition, these organic resin materials may be thermosetting or photocurable. In the present invention, the first interlayer insulating film 111 having a thickness in the range of 0.6 to 2 μm is formed in order to reduce a parasitic capacitance generated between each signal wiring provided on a different interlayer insulating film. Preferably, it is provided. (Fig. 2 (A))

A first metal film is formed on the first interlayer insulating film thus obtained, and is patterned using a resist mask 201. (FIG. 2 (B))

Thereafter, dry etching is performed using the patterned first metal film 204 as a mask to form contact holes 202 and 203. (Figure 2
(C) In this step, the resist mask 201 can be removed simultaneously with the formation of the contact hole. Also, Al, T
When i, Cr, W, or TiN is used for the first metal film, etching may be performed using a chlorine-based etchant gas. When Ta is used for the first metal film, etching may be performed using a fluorine-based etchant gas.
Note that the present invention is characterized in that the first metal film used as a mask in a subsequent step is patterned again and used as a part of a wiring.

In the present invention, the TFT structure is not limited to the structure shown in FIG.
The present invention can be easily applied to a structure having an FT or silicide structure as required by a practitioner.

In this specification, a dry etching method is used to remove an interlayer insulating film made of a resin material. However, a chlorine-based, fluorine-based, or oxygen-based etchant gas may be used as necessary. Use as appropriate.

As used herein, the term "chlorine-based etchant gas" refers to chlorine or a gas partially containing chlorine, for example, Cl ₂ , BCl ₃ , SiCl ₄ , HCl, CCl.
₄ or other single gas or mixed gas, and furthermore, these single gas or mixed gas is a gas containing no chlorine (for example, H
₂ , O ₂ , N _2, etc.).

Further, the fluorine-based etchant gas referred to in the present specification refers to fluorine or a gas containing fluorine partially, for example, F ₂ , BF ₃ , SiF ₄ , HF, C
Single gas or a mixed gas of F ₄ or the like, refers to those diluted in these single gases or gas the mixed gas not containing chlorine (e.g. H _2, O _2, N _2, etc.).

Further, a detailed description of a semiconductor device and a method of manufacturing the same will be given in the following examples.

[0040]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below, but it is needless to say that the present invention is not limited to these embodiments.

[Embodiment 1] In this embodiment, a sectional structural view of a semiconductor device of the present invention formed on an insulating substrate will be described with reference to FIG.

In the figure, 100 is a substrate, and 101 is a base film. Also, 102 is a channel formation region, 103 and 104 are low concentration impurity regions, 105 is a drain region,
06 is a source region, 107 is a gate insulating film, 108 is a gate wiring, 109 is an anodized film, 110 is a protective film, 11
1 is an organic material film (first interlayer insulating film), 112 and 113
Is a first metal layer, 114 and 115 are second metal layers, 11
6 is an organic material film (second interlayer insulating film), 117 is a black mask, 118 is an organic material film (third interlayer insulating film),
119 is a pixel electrode.

The wirings (112 to 115) of the present invention are formed on a first metal film (112, 1) provided in contact with the organic material film.
13) and a second metal film (114, 1) provided on the film.
15). Further, it has a structure in which only the second metal film (114, 115) is formed in contact with the inner wall portion and the bottom of the contact hole provided in the organic material film.

The first metal layer or the second metal layer is not particularly limited as long as the material has conductivity. For example, a material layer containing Al, Ta, Ti, Mo, W, or Cr as a main component or a stacked film thereof can be used. In this embodiment, the resistance of the wiring was reduced because the first metal film was made of a material containing Al as a main component. In addition,
It is not particularly problematic that a material mainly composed of Al is formed on a flat surface, but when the film is formed by a sputtering method in a region having irregularities on the surface, coverage on the irregularities is poor. In addition, since aluminum may diffuse into the semiconductor layer from the contact interface, formation in contact with the semiconductor layer (for example, silicon) is avoided.

Therefore, in this embodiment, titanium nitride (TiN) was used as the second metal film. Titanium nitride has a higher resistivity than aluminum, but has good coverage of a region having irregularities and a good contact interface with a semiconductor layer (for example, silicon).

[Embodiment 2] In this embodiment, a process for manufacturing a semiconductor element, particularly a process for forming a contact hole and a process for forming a wiring on a substrate having an insulating surface will be described below with reference to FIGS. Show.

First, a base film 101 is formed on a substrate 100 having an insulating surface. As the substrate, a glass substrate, a quartz substrate, a ceramics substrate, or a semiconductor substrate can be used. Alternatively, a plastic substrate may be used if the process temperature is within a temperature range that can be endured. In this embodiment, a glass substrate was used. As the base film, a silicon oxide film, a silicon nitride film, or a silicon nitride oxide film having a thickness of 100 to 300 nm can be used. In this embodiment, a silicon oxide film is formed to a thickness of 200 nm using TEOS as a raw material.
In addition, if it has sufficient flatness like a quartz substrate,
The base film does not need to be particularly provided.

Next, an active layer is formed on the substrate or the underlying film. The active layer has a thickness of 20 to 100 nm (preferably 25 to 70 nm).
nm) of a crystalline semiconductor film (typically, a crystalline silicon film). As a method of forming the crystalline silicon film, any known means may be used.
The film was formed to a thickness of 50 nm using the technique described in Japanese Patent No. 2260.

The crystalline silicon film thus formed is patterned to form an active layer, and a gate insulating film 107 is formed. As the gate insulating film, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a stacked film of these can be used with a thickness of 100 to 300 nm. In this embodiment, plasma CVD
The silicon nitride oxide film was formed to a thickness of 150 nm by a method to form the gate insulating film 107.

Next, aluminum or a material containing aluminum as a main component (in this embodiment, a film formed using a target containing 2 wt% scandium,
(aluminum film having a thickness of nm) was formed by a sputtering method and patterned to form a gate wiring 108.

Next, a Group 13 or Group 15 element is added by using the technique described in Japanese Patent Application Laid-Open No. 7-135318 to form a source region 106, a drain region 105, a channel forming region 102, and an LDD (Lightly doped drain) region 103. ,
104 was formed. In this embodiment, the distance between the source and drain regions and the channel formation region is 0.5 to 1.5 μm.
(Typically 0.7 to 1 μm) LDD regions 103 and 10
4 was formed. In this embodiment, the gate wiring 108
Although the anodic oxide film 109 was formed in contact with, it was not particularly necessary to form it.

Next, the impurity element (13
(Group 15 element) was activated by thermal annealing or laser irradiation. In this example, after activation using an excimer laser, thermal annealing was further performed at 450 ° C. for 2 hours.

Thereafter, the entire surface of the substrate is covered with the protective film 110.
To form As the protective film, a silicon nitride film or a silicon nitride oxide film can be used. In this embodiment, a silicon nitride film serving as a protective film is formed with a thickness of 25 nm. Note that FIG. 2A is a cross-sectional view after formation of the protective film.

Further, an organic material film having a thickness of 0.5 to 3 μm is formed as the first interlayer insulating film 111 covering the entire surface of the substrate. As a film forming method, a film having a flat surface can be easily obtained by using a spin coating method using a spinner. Subsequently, baking is performed by heating at 250 ° C. for 1 hour. In this embodiment, the acrylic is 1 μm.
m was formed. Further, as the first interlayer insulating film, polyimide, BCB (benzocyclobutene), or another organic material can be used in addition to acrylic.

On the thus obtained flat first interlayer insulating film, a first metal film is formed by RF sputtering. After that, a resist 201 is provided, and the first metal film is patterned by dry etching. The first metal film was formed to a thickness of 100 nm to 2 μm, and in this embodiment, a metal film containing aluminum as a main component was formed to a thickness of 500 nm and dry-etched with a chlorine-based etchant gas. (Figure 2
(B))

Next, the patterned first metal film 1
Dry etching is performed using the mask 12 as a mask to form contact holes 202 and 203 in the first interlayer insulating film. At the same time, the resist made of a material having a composition similar to the material of the first interlayer insulating film is also removed by this step.
(FIG. 2C) When a protective film is provided as in this embodiment, etching is performed again to remove the protective film 110, and the semiconductor layers (106, 105) are formed at the bottom of the contact hole.
To expose. In this embodiment, the silicon nitride film as the protective film is etched by anisotropic dry etching such as RIE (reactive ion etching). As an etchant gas, a fluorine-based gas or CHF ₃ gas was used.

In order to reduce the number of steps, it is preferable to simultaneously etch the first interlayer insulating film and the protective film using a mixed gas of CF ₄ , oxygen and He.

After that, a second metal film 301 is formed by RF sputtering. (FIG. 3A) Through this step, a contact is formed by contacting the drain region 105 of the thin film transistor with the second metal film at the bottom of the contact hole provided in the organic material film. The thickness of the second metal film is 10 nm to 1 μm, and in this embodiment, the thickness of the TiN film is 150 nm.
m was formed.

The first metal layer or the second metal layer is not particularly limited as long as it is a conductive material to which a sputtering method can be applied. For example, Al, Ta, Ti, Cr
Or a stacked layer of these. Note that a structure in which the first metal layer and the second metal layer are formed using the same material may be employed.

Next, patterning was performed, and the first metal film and the second metal film were etched by dry etching to form an electrode pattern of a source electrode and a drain electrode. In this embodiment, a chlorine-based etchant gas, Cl ₂
/ BCl ₃ / SiCl ₄ at 40 sccm / 10 sccm / 180
Dry etching was performed using sccm. (FIG. 3 (B))

The completed wiring (112 to 115)
Has a laminated structure of a first metal film provided in contact with an organic material film and a second metal film provided on the film. The second metal film (1) contacts the inner wall and the bottom of the contact hole provided in the organic material film 111.
14, 115) alone. In this embodiment, since the first metal film mainly composed of aluminum is used, the resistance of the wiring can be reduced, and the second metal film mainly composed of titanium is used for the contact. Could be formed.

Then, a second interlayer insulating film 116 is formed to cover the entire surface of the substrate. Note that an organic material film having a thickness of 0.5 to 3 μm is formed as a second interlayer insulating film. In this embodiment, acrylic was formed again to a thickness of 1 μm. A Ti film is formed thereon as a black mask 117 by a sputtering method and patterned.

Thereafter, a third interlayer insulating film 118 is formed to cover the entire surface of the substrate. Note that an organic material film having a thickness of 0.5 to 3 μm is formed as a third interlayer insulating film. In this embodiment, acryl was formed again to a thickness of 1 μm.

A contact hole for electrically connecting to the drain electrode is formed in the second interlayer insulating film and the third interlayer insulating film. In this step, a fluorine-based etchant gas, in this embodiment, CF ₄ / O ₂ / He is added at 5 sccm /
It is performed by dry etching using 95 sccm / 40 sccm. Note that when the first interlayer insulating film, the second interlayer insulating film, and the third interlayer insulating film are formed of the same material as in this embodiment, stress can be suppressed, and each interlayer insulating film can be connected to each other. Excellent adhesion can be obtained.

Then, a conductive film to be the pixel electrode 119 was formed, and was electrically connected to the drain region 105 of the TFT via wirings (112 to 115). (FIG. 3 (C)) In this example, a transmission type liquid crystal display device was manufactured by using ITO for the conductive film. However, a reflection type liquid crystal display device was formed by using a reflection electrode such as Al or Ti for a pixel electrode. Can also be produced. The reflective electrode such as Al or Ti may be formed by a sputtering method.

By the above manufacturing steps, a switching element (TFT) for applying a voltage for driving liquid crystal to a pixel electrode was completed, and a plurality of pixels were formed to complete an active matrix substrate having a pixel matrix circuit. At least one switching element and a first storage capacitor may be arranged in each pixel in the pixel matrix circuit. Note that in this specification, the element configured in FIG. 3B is referred to as a switching element (typically, a TFT or an MIM element).

It should be noted that a drive circuit (driver circuit) other than the pixel matrix circuit is provided on the active matrix substrate.
And a signal processing circuit (a logic circuit such as a gamma correction circuit and a D / A converter) can be formed. The manufacturing steps of these circuits are basically the same as the manufacturing steps described in this embodiment (actually, the steps are completed in the step of FIG. 3B), and thus detailed description is omitted.

Further, since the present invention relates to the formation of a contact hole and the configuration of a wiring, the configuration of another element (capacitance element or storage element) formed on the same substrate may be any. The manufacturing process and structure of such a circuit may be appropriately determined by a practitioner.

[Embodiment 3] In this embodiment, an inverted staggered TFT is used as shown in FIG. The process of this embodiment, which is different from the process of manufacturing an inverted staggered TFT by a known technique, includes a process of using an organic material for the interlayer insulating film 411 and a process of forming a contact hole by dry etching using a metal film as a mask. ,
The method includes a step of forming a wiring composed of the first metal layer 412 and the second metal film 414. The TFT structure is not limited to the structure shown in FIG. 4 (channel stop type), and the present invention may be applied to a structure having a channel-etch type TFT or a silicide structure according to the needs of the practitioner. It is easy to apply.

[Embodiment 4] In this embodiment, a switching element (TF) for applying a voltage for controlling liquid crystal to a pixel electrode is used.
This is an example in which a storage capacitor is formed simultaneously with T). In FIG.
A cross-sectional view of a contact portion where a storage capacitor is formed is illustrated.

This embodiment is manufactured by the same steps as those in FIG. 2C of the first embodiment, and therefore the description and drawings are omitted.

Conventionally, when an inorganic insulating film formed by a CVD method or the like is provided on an organic material film, when the organic material is exposed on the surface, a gas such as water or methane is generated from the organic material film,
It was difficult to obtain a good quality film.

In the present embodiment, FIG.
When the same state as in (C) is obtained, a second metal film is formed by a sputtering method so as to cover the entire surface of the substrate, completely exposing portions where the organic material is exposed to prevent generation of the above gas, and then continuously. An inorganic insulating film was formed by a CVD method. The inorganic insulating film has a thickness of 10 to 100 n using a plasma CVD method.
m, in this example, a silicon nitride film was formed to a thickness of 50 nm. The inorganic insulating film may have a single-layer structure or a stacked structure of two or more layers, for example, a silicon nitride film (lower layer) / a silicon oxide film (upper layer).

Next, patterning is performed to form wirings 512 and 514 whose upper surfaces are covered with the inorganic insulating film 521. Then, the entire surface of the substrate is covered with a second interlayer insulating layer 516.
Was formed, and a concave portion was provided only in a portion constituting the storage capacitor 520 later. The second interlayer insulating film may have a single-layer structure or a stacked structure of two or more layers.

In this embodiment, an insulating layer made of an acrylic film (1 μm) is used as the second interlayer insulating layer. Polyimide instead of acrylic, BCB (benzocyclobutene)
Other organic materials may be used.

Then, in order to form the concave portion, the acrylic film is opened by a dry etching method. At this time, the silicon nitride film 521 functions as an etching stopper. Therefore, the silicon nitride film remains on the bottom of the recess. In the case of this embodiment, this film 521 is used as a dielectric of a storage capacitor.
Of course, wet etching may be used. Further, a thinned portion formed by forming a concave portion by half etching may be used as a dielectric of a storage capacitor.

After forming the concave portion in the second interlayer insulating layer in this way, a black mask is formed at a desired position.
In this embodiment, titanium is used as the black mask 517, but another metal film such as chromium or tantalum may be used.

In this state, the drain electrodes 512, 514
And a black mask 517 as upper and lower electrodes, and a storage capacitor 520 using the second interlayer insulating layer 521 (more precisely, a silicon nitride film) as a dielectric. (Fig. 5)

Thus, a storage capacitor 520 was formed simultaneously with a switching element (TFT) for applying a voltage for controlling liquid crystal to the pixel electrode.

Each of the interlayer insulating films made of the organic material in each of the above embodiments may be a single layer or a laminated structure of two or more layers.

This embodiment can be freely combined with any one of the first to third embodiments.

[Embodiment 5] FIG. 6 shows an embodiment of the present invention.
This will be described with reference to FIG. Here, a method for simultaneously manufacturing a pixel circuit and a driver circuit for driving the pixel circuit over the same substrate will be described. However, for the sake of simplicity, the driving circuit shows a CMOS circuit which is a basic circuit such as a shift register circuit and a buffer circuit, and an n-channel TFT forming a sampling circuit.

In FIG. 6A, a quartz substrate or a silicon substrate is desirably used as the substrate 601. In this embodiment, a quartz substrate was used. Alternatively, a substrate obtained by forming an insulating film on the surface of a metal substrate or a stainless steel substrate may be used as the substrate. In the case of this embodiment, since heat resistance that can withstand a temperature of 800 ° C. or more is required, any substrate may be used as long as it meets the requirement.

Then, the surface of the substrate 601 on which the TFT is formed is 20 to 100 nm (preferably 40 to 80 nm).
A semiconductor film 602 having an amorphous structure with a thickness of m) is formed by a low pressure thermal CVD method, a plasma CVD method, or a sputtering method.

The semiconductor film having an amorphous structure includes an amorphous semiconductor film and a microcrystalline semiconductor film, and further includes a compound semiconductor film having an amorphous structure such as an amorphous silicon germanium film. . Further, it is also effective to continuously form a base film and an amorphous silicon film on a substrate without exposing them to the atmosphere. By doing so, it becomes possible to prevent contamination of the substrate surface from affecting the amorphous silicon film, and it is possible to reduce the variation in characteristics of the TFT to be manufactured.

Next, a mask film 603 made of an insulating film containing silicon (silicon) is formed on the amorphous silicon film 602, and openings 604a and 604b are formed by patterning. This opening serves as an addition region for adding a metal element that promotes crystallization in the next crystallization step.
(FIG. 6 (A))

Note that as the insulating film containing silicon, a silicon oxide film, a silicon nitride film, or a silicon nitride oxide film can be used. The silicon nitride oxide film is an insulating film containing silicon, nitrogen, and oxygen in predetermined amounts, and is an insulating film represented by SiOxNy. Silicon nitride oxide film is Si
H ₄ , N ₂ O, and NH ₃ can be produced as a source gas, and the contained nitrogen concentration is 25 atomic% or more.
It is better to be less than 0 atomic%.

At the same time as patterning of the mask film 603, a marker pattern serving as a position reference is formed in a subsequent patterning step.

Next, a semiconductor film having a crystal structure is formed according to the technique described in Japanese Patent Application Laid-Open No. Hei 10-247735 (corresponding to US Application No. 09 / 034,041). The technique described in this publication is based on the fact that when crystallization of a semiconductor film having an amorphous structure, one or more elements selected from elements promoting crystallization (nickel, cobalt, germanium, tin, lead, palladium, iron, copper) Is a crystallization means using the above-mentioned element).

Specifically, heat treatment is performed with the surface of the semiconductor film including an amorphous structure holding a metal element which promotes crystallization, and the semiconductor film including the amorphous structure is converted into a crystal structure. Semiconductor film. As the crystallization means, the technique described in Example 1 of JP-A-7-130652 may be used. In addition, a semiconductor film including a crystalline structure includes a so-called single crystal semiconductor film and a polycrystalline semiconductor film, and a semiconductor film including a crystal structure formed in the publication has a crystal grain boundary.

In this publication, a spin-coating method is used to form a layer containing a metal element which promotes crystallization on a mask film. However, a thin film containing a metal element which promotes crystallization is formed by a sputtering method or the like. Means for forming a film using a vapor phase method such as an evaporation method may be employed.

The amorphous silicon film is preferably subjected to a heat treatment at 400 to 550 ° C. for about 1 hour, depending on the amount of hydrogen contained therein, and is preferably crystallized after sufficient desorption of hydrogen. . In this case, the hydrogen content is preferably set to 5 atom% or less.

First, the crystallization step is performed at 400 to 500 ° C. for 1 hour.
After performing a heat treatment process for about an hour to desorb hydrogen from the film, the heat treatment is performed at 500 to 650 ° C. (preferably 550 to 600
C.) for 6 to 16 hours (preferably 8 to 14 hours).

In this embodiment, nickel is used as a metal element for promoting crystallization, and heat treatment is performed at 570 ° C. for 14 hours. As a result, crystallization proceeds in a direction substantially parallel to the substrate (the direction indicated by the arrow) starting from the openings 604a and 604b, and a semiconductor film having a crystal structure in which macroscopic crystal growth directions are aligned (this embodiment) Then, a crystalline silicon film) 605a
To 605d are formed. (Fig. 6 (B))

Next, a gettering step of removing nickel used in the crystallization step from the crystalline silicon film is performed.
In this embodiment, a step of adding an element belonging to Group 15 (phosphorus in this embodiment) using the mask film 603 formed earlier as a mask is performed, and the openings 604a and 604b are formed.
1 × 10 ¹⁹ to 1 × 10 ²⁰ on the crystalline silicon film
Phosphorus-added regions (hereinafter, referred to as gettering regions) 606a and 606b containing phosphorus at a concentration of atoms / cm ³ are formed. (FIG. 6 (C))

Next, at 450 to 650 ° C. in a nitrogen atmosphere.
(Preferably 500 to 550 ° C.) and a heat treatment step for 4 to 24 hours (preferably 6 to 12 hours) are performed. By this heat treatment step, nickel in the crystalline silicon film moves in the direction of the arrow, and nickel is removed from the crystalline silicon film by the gettering action of phosphorus. Therefore, the crystalline silicon films 607a to 607d after gettering are obtained. Can be reduced to 1 × 10 ¹⁷ atms / cm ³ or less, preferably 1 × 10 ¹⁶ atms / cm ³ .

Next, the mask film 603 is removed, and a protective film 608 is formed on the crystalline silicon films 607a to 607d for the purpose of adding impurities later. The protective film 608 is 100 to
It is preferable to use a silicon nitride oxide film or a silicon oxide film with a thickness of 200 nm (preferably 130 to 170 nm). The protective film 608 has a meaning to prevent the crystalline silicon film from being directly exposed to plasma at the time of adding an impurity and to enable fine concentration control.

Then, a resist mask 609 is formed thereon, and an impurity element imparting p-type (hereinafter, referred to as a p-type impurity element) is added via a protective film 608. As the p-type impurity element, an element belonging to Group 13 typically, typically, boron or gallium can be used.
This step (called a channel doping step) is a step for controlling the threshold voltage of the TFT. Here, boron is added by an ion doping method in which diborane (B ₂ H ₆ ) is plasma-excited without mass separation. Of course, an ion implantation method for performing mass separation may be used.

By this step, 1 × 10 ¹⁵ to 1 × 10 ¹⁸ at
oms / cm ³ (typically 5 × 10 ^{16 to} 5 × 10 ¹⁷ atoms / cm
Impurity regions 610a and 610b containing a p-type impurity element (boron in this embodiment) at a concentration of ³ ) are formed. In addition,
In the present specification, an impurity region containing a p-type impurity element in the above concentration range (however, a region not containing phosphorus) is defined as a p-type impurity region (b). (FIG. 6 (D))

Next, the resist mask 609 is removed, and the crystalline silicon film is patterned to form island-shaped semiconductor layers (hereinafter, referred to as active layers) 611 to 614. In addition,
The active layers 611 to 614 are formed of a crystalline silicon film having very good crystallinity by selectively adding nickel and crystallizing. Specifically, it has a crystal structure in which rod-shaped or columnar crystals are arranged with a specific direction. Further, after crystallization, nickel is removed or reduced by the gettering action of phosphorus.
The concentration of nickel element remaining in 614 is 1 × 10 ¹⁷
atoms / cm ³ or less, preferably 1 × 10 ¹⁶ atoms / cm ³ . (FIG. 6E)

Further, the active layer 611 of the p-channel TFT
Is a region that does not contain an impurity element that is intentionally added, and the active layers 612 to 614 of the n-channel TFT are p-type impurity regions (b). In this specification, the active layers 611 to 614 in this state are all defined as being intrinsic or substantially intrinsic. That is, a region to which an impurity element is intentionally added to such an extent that the operation of the TFT is not hindered may be considered as a substantially intrinsic region.

Next, an insulating film containing silicon having a thickness of 10 to 100 nm is formed by a plasma CVD method or a sputtering method. In this embodiment, a 30-nm-thick silicon nitride oxide film is formed. As the insulating film containing silicon, another insulating film containing silicon may be used as a single layer or a stacked layer.

Next, at 800-1150 ° C. (preferably 9 ° C.)
A heat treatment step at a temperature of (00 to 1000 ° C.) for 15 minutes to 8 hours (preferably 30 minutes to 2 hours) is performed in an oxidizing atmosphere (thermal oxidation step). In this embodiment, a heat treatment step is performed at 950 ° C. for 80 minutes in an atmosphere in which 3% by volume of hydrogen chloride is added in an oxygen atmosphere. Note that boron added in the step of FIG. 6D is activated during this thermal oxidation step. (FIG. 7
(A))

During this thermal oxidation step, an oxidation reaction also proceeds at the interface between the insulating film containing silicon and the active layers 611 to 614 thereunder. In the thermal oxidation step of the present embodiment, 60 nm
25 nm of the thick active layer is oxidized to
The film thickness of 614 is 45 nm. Further, a 50-nm-thick thermal oxide film is added to the 30-nm-thick silicon-containing insulating film, so that the final gate insulating film 615 has a thickness of 110 nm.

Next, resist masks 616 to 61 are newly added.
9 is formed. Then, an impurity element imparting n-type (hereinafter, referred to as an n-type impurity element) is added to form impurity regions 620 to 622 exhibiting n-type. Note that as the n-type impurity element, an element belonging to Group XV, typically, phosphorus or arsenic can be used. (FIG. 7
(B))

These impurity regions 620 to 622 will be
N-channel type TF of MOS circuit and sampling circuit
T is an impurity region for functioning as an LDD region. The impurity region formed here has n
The type impurity element is contained at a concentration of 2 × 10 ^{16 to} 5 × 10 ¹⁹ atoms / cm ³ (typically, 5 × 10 ^{17 to} 5 × 10 ¹⁸ atoms / cm ³ ). In this specification, an impurity region containing an n-type impurity element in the above concentration range is defined as an n-type impurity region (b).

In this case, phosphorus is added at a concentration of 1 × 10 ¹⁸ atoms / cm ³ by an ion doping method in which phosphine (PH ₃ ) is plasma-excited without mass separation. Of course, an ion implantation method for performing mass separation may be used. In this step, phosphorus is added to the crystalline silicon film via the gate film 615.

Next, at 600-1000 ° C. (preferably 7 ° C.)
Heat treatment is performed in an inert atmosphere (at 00 to 800 ° C.) to activate the phosphorus added in the step of FIG. In this embodiment, the heat treatment at 800 ° C. for 1 hour is performed in a nitrogen atmosphere.
(FIG. 7 (C))

At this time, the active layer damaged at the time of adding phosphorus and the interface between the active layer and the gate insulating film can be repaired at the same time. In this activation step, furnace annealing using an electric heating furnace is preferable, but optical annealing such as lamp annealing or laser annealing may be used together.

By this step, n-type impurity region (b) 62
A boundary portion between 0 and 622, that is, a junction with an intrinsic or substantially intrinsic region (including the p-type impurity region (b)) existing around the n-type impurity region (b) becomes clear. . This means that when the TFT is completed later, LDD
This means that the region and the channel forming region can form a very good junction.

Next, a conductive film to be a gate wiring is formed. Note that the gate wiring may be formed using a single-layer conductive film, but is preferably a stacked film such as two layers or three layers as necessary. In this embodiment, a stacked film including the first conductive film 623 and the second conductive film 624 is formed. (FIG. 7 (D))

Here, the first conductive film 623 and the second conductive film 62
4 include tantalum (Ta), titanium (Ti), molybdenum (Mo), tungsten (W), chromium (C
r), an element selected from silicon (Si), or a conductive film containing the above element as a main component (typically, a tantalum nitride film, a tungsten nitride film, a titanium nitride film), or an alloy film combining the above elements ( Typically, Mo-W alloy,
Mo-Ta alloy) can be used.

Note that the first conductive film 623 has a thickness of 10 to 50 nm.
(Preferably 20 to 30 nm), and the second conductive film 624.
Is 200 to 400 nm (preferably 250 to 350 n
m). In this embodiment, a 50-nm-thick tungsten nitride (WN) film is used as the first conductive film 623, and a 350-nm-thick tungsten film is used as the second conductive film 624. Although not shown, it is effective to form a silicon film under the first conductive film 623 with a thickness of about 2 to 20 nm.

Next, the first conductive film 623 and the second conductive film 62
4 are collectively etched to form gate wirings 625 to 628 having a thickness of 400 nm. At this time, the gate wirings 626 and 627 formed in the drive circuit are n-type impurity regions (b).
It is formed so as to overlap with part of 620 to 622 with the gate insulating film 615 interposed therebetween. This overlapping portion will later become a Lov region. Although the gate wirings 628a and 628b appear to be two in cross section, they are actually formed from one continuous pattern. (FIG. 7E)

Next, a resist mask 629 is formed, and p
The impurity regions 630 and 631 containing boron at a high concentration are formed by adding a type impurity element (boron in this embodiment).
In this embodiment, an ion doping method using diborane (B ₂ H ₆ ) (of course, an ion implantation method may be used).
To add boron at a concentration of 3 × 10 ^{20 to} 3 × 10 ²¹ atoms / cm ³ (typically, 5 × 10 ²⁰ to 1 × 10 ²¹ atoms / cm ³ ). In this specification, an impurity region containing a p-type impurity element in the above concentration range is defined as a p-type impurity region (a). (FIG. 8A)

Next, the resist mask 629 is removed, and resist masks 632 to 634 are formed so as to cover the gate wiring and the region to be the p-channel TFT. And n
The impurity regions 635 to 641 containing phosphorus at a high concentration are formed by adding a type impurity element (phosphorus in this embodiment). Also in this case, the ion doping method using phosphine (PH ₃ ) (of course, the ion implantation method may be used), and the concentration of phosphorus in this region is 1 × 10 ²⁰ to 1 × 10 ²¹ at.
oms / cm ³ (typically 2 × 10 ^{20 to} 5 × 10 ²¹ atoms / cm
³ ). (FIG. 8 (B))

Note that in this specification, an impurity region containing an n-type impurity element in the above concentration range is defined as an n-type impurity region (a). The region where the impurity regions 635 to 641 are formed contains phosphorus or boron already added in the previous step, but phosphorus is added at a sufficiently high concentration. You do not need to consider the effect of phosphorus or boron. Therefore, in this specification, the impurity regions 635 to 641 may be rephrased as n-type impurity regions (a).

Next, the resist masks 632 to 634 are removed, and a protective film 642 made of an insulating film containing silicon is formed. The film thickness is 25 to 100 nm (preferably 30 to 50 n
m). In this embodiment, a silicon nitride film having a thickness of 25 nm is used.

Next, an n-type impurity element (phosphorus in this embodiment) is added in a self-aligned manner using the gate wirings 625 to 628 as a mask. The impurity region 643 thus formed
To 646 are 1/2 to 1/1 / of the n-type impurity region (b).
10 (typically 1/3 to 1/4) (however, 5% higher than the boron concentration added in the channel doping step described above).
〜１０10-fold higher concentration, typically 1 × 10 ¹⁶ -5 × 10 ¹⁸
atoms / cm ³ , typically 3 × 10 ^{17 to} 3 × 10 ¹⁸ atoms / cm ³
Adjust so that phosphorus is added in cm ³ ). Note that, in this specification, an impurity region containing an n-type impurity element (excluding the p-type impurity region (a)) in the above concentration range is defined as an n-type impurity region (c). (FIG. 8 (C))

In this step, an insulating film having a thickness of 105 nm (a laminated film of the cap film 642 and the gate insulating film 615)
, The protective film 642 also functions as a mask. That is, an offset region having a length corresponding to the thickness of the protective film 642 is formed.

In this step, 1 × 10 ^{16 to} 5 × 1 is applied to all the impurity regions except for the portion hidden by the gate wiring.
Although phosphorus is added at a concentration of 0 ¹⁸ atoms / cm ³ , the function is extremely low and does not affect the function of each impurity region. The n-type impurity regions (b) 643 to 646 already have 1 × 10 ¹⁵ to 1 × 10 ¹⁸ atoms in the channel doping step.
Although boron is added at a concentration of s / cm ³ , phosphorus is added at a concentration of 5 to 10 times that of boron contained in the p-type impurity region (b) in this step.
It may be considered that the function of the type impurity region (b) is not affected.

Thereafter, a heat treatment step was performed to activate the n-type or p-type impurity element added at each concentration. This step can be performed by furnace annealing, laser annealing, lamp annealing, or a combination thereof. When performing the furnace annealing method,
The heat treatment may be performed at 500 to 800C, preferably 550 to 600C in an inert atmosphere. In this embodiment, 600
A heat treatment is performed at 4 ° C. for 4 hours to activate the impurity element.
(FIG. 8 (D))

In this embodiment, the silicon nitride film 642
Are covered with the gate wiring, and the activation step is performed in that state. In this embodiment, since the silicon nitride film is stacked, the activation step can be performed at a high temperature without concern about the problem of the pinhole.

Next, after the activation step, heat treatment is performed at 300 to 450 ° C. for 1 to 4 hours in an atmosphere containing 3 to 100% hydrogen to hydrogenate the active layer. In this step, dangling bonds in the semiconductor layer are terminated by thermally excited hydrogen. Plasma hydrogenation (using hydrogen excited by plasma) as another means of hydrogenation
May be performed.

When the activation step is completed, 500 nm to 1.
A first interlayer insulating film 650 having a thickness of 5 μm is formed. In this embodiment, 1 μm-thick acrylic is formed as the first interlayer insulating film 650 by a coating method. Further, the other first interlayer insulating film 65
As 0, it is also possible to use an organic resin film of polyimide, polyamide, polyimide amide, BCB (benzocyclobutene) or the like.

Thereafter, a contact hole reaching the source region or the drain region of each TFT is formed. At this time, after a Ti film is formed on the entire surface by the sputtering method, the T film is formed by dry etching using a resist mask.
A contact hole penetrating the i film and the organic resin film is formed.
At the same time as the dry etching, the resist mask is removed, and a film mainly containing aluminum is formed on the entire surface,
By performing patterning, source wirings 651 to 654,
Drain wirings 655 to 657 are formed. Thus, the contact structure shown in the embodiment of the present invention is realized.

In order to form a CMOS circuit, the drain wiring 655 is formed of a p-channel TFT and an n-channel TFT.
Common with FT. Although not shown, in this embodiment, this wiring is formed by a Ti film of 200 nm
A laminated film having a two-layer structure in which an aluminum film containing i is formed to a thickness of 500 nm. (FIG. 9A)

After this, a hydrogenation step may be further performed. For example, in an atmosphere containing 3 to 100% hydrogen,
It is preferable to perform heat treatment at 300 to 450 ° C. for 1 to 12 hours, or similar effects can be obtained by using a plasma hydrogenation method.

Thereafter, a second interlayer insulating film 659 made of an organic resin is formed to a thickness of about 1 μm. As the organic resin, polyimide, acrylic, polyamide, polyimide amide, BCB (benzocyclobutene), or the like can be used. The advantages of using an organic resin film include that the film formation method is simple, the parasitic capacitance can be reduced because the relative dielectric constant is low, and the flatness is excellent. Note that an organic resin film or an organic SiO 2 compound other than those described above can also be used. Here, it is formed by baking at 300 ° C. using a type of polyimide which is thermally polymerized after being applied to the substrate.

Next, in a region to be a pixel circuit, the second
A shielding film 660 is formed over the interlayer insulating film 659. In addition,
In this specification, the term shielding film is used to mean that light and electromagnetic waves are shielded. The shielding film 660 is made of aluminum (A
1) A film made of an element selected from titanium (Ti) and tantalum (Ta) or a film containing any one of the elements as a main component and having a thickness of 100 to 300 nm. In this embodiment, 1w
An aluminum film containing t% titanium is formed to a thickness of 125 nm.

If an insulating film such as a silicon oxide film is formed on the second interlayer insulating film 659 in a thickness of 5 to 50 nm, the adhesion of the shielding film formed thereon can be improved. In addition, when plasma treatment using CF ₄ gas is performed on the surface of the second interlayer insulating film 659 formed of an organic resin, adhesion of a shielding film formed on the film by surface modification can be improved.

Further, using the aluminum film containing titanium, not only a shielding film but also other connection wirings can be formed. For example, a connection wiring for connecting elements in a drive circuit can be formed. However, in that case, before forming the material for forming the shielding film or the connection wiring, the second
It is necessary to form a contact hole in the interlayer insulating film.

Next, an oxide 661 having a thickness of 20 to 100 nm (preferably 30 to 50 nm) is formed on the surface of the shielding film 660 by anodic oxidation or plasma oxidation (in this embodiment, anodic oxidation). In this embodiment, the shielding film 660 is used.
Is used, an aluminum oxide film (alumina film) is formed as the anodic oxide 661.

Next, a contact hole reaching the drain wiring 657 is formed in the third interlayer insulating film 659 and the passivation film 658, and a pixel electrode 662 is formed. In addition,
The pixel electrode 663 is a pixel electrode of another adjacent pixel.
For the pixel electrodes 662 and 663, a transparent conductive film may be used for a transmissive liquid crystal display device, and a reflective material film may be used for a reflective liquid crystal display device. Here, in order to form a transmissive liquid crystal display device, an indium tin oxide (ITO) film is formed to a thickness of 110 nm by a sputtering method.

At this time, the pixel electrode 662 and the shielding film 6
60 overlap with each other via the anodic oxide 661 to form a storage capacity (capacity-stretch) 664. Note that in this case, it is desirable that the shielding film 660 be set to a floating state (an electrically isolated state) or a fixed potential, preferably a common potential (an intermediate potential of an image signal transmitted as data).

Thus, an active matrix substrate having a drive circuit and a pixel circuit on the same substrate was completed. Note that in FIG. 9B, a p-channel TFT 301 and n-channel TFTs 802 and 803 are formed in a driver circuit, and a pixel T including an n-channel TFT is formed in a pixel circuit.
An FT 804 is formed.

Here, a process for manufacturing an active matrix type liquid crystal display device from an active matrix substrate will be described. An alignment film is formed on the substrate in the state shown in FIG. In this embodiment, a polyimide film is used as an alignment film. Further, a transparent conductive film and an alignment film 4 are formed on the counter substrate. Note that a color filter and a shielding film may be formed on the counter substrate as needed.

Next, after forming the alignment film, a rubbing treatment is performed to adjust the liquid crystal molecules so as to be aligned with a certain pretilt angle. Then, the pixel circuit, the active matrix substrate on which the drive circuit is formed, and the opposing substrate are attached to each other via a sealing material or a spacer (both not shown) by a known cell assembling process. afterwards,
Liquid crystal is injected between both substrates, and completely sealed with a sealing agent (not shown). A known liquid crystal material may be used for the liquid crystal. Thus, an active matrix liquid crystal display device is completed.

Next, the structure of the active matrix type liquid crystal display device will be described with reference to the perspective view of FIG. In FIG. 8, common reference numerals are used to correspond to the cross-sectional structural views of FIGS. The active matrix substrate includes a pixel circuit 901 formed on a quartz substrate 601.
And a scanning (gate) signal driving circuit 902 and an image (source) signal driving circuit 903. The pixel TFT 804 of the pixel circuit is an n-channel TFT, and a peripheral driving circuit is configured based on a CMOS circuit. Scanning signal drive circuit 902 and image signal drive circuit 9
Numeral 03 denotes a gate line 628 and a source line 654 which are connected to the pixel circuit 901 respectively. In addition, FPC904
There are provided connection wirings 906 and 907 from the external input / output terminal 905 to which is connected to the input / output terminal of the drive circuit.

Next, FIG. 11 shows an example of a circuit configuration of the active matrix type liquid crystal display device shown in FIG. The active matrix type liquid crystal display device of this embodiment includes an image signal driving circuit 1001 and a scanning signal driving circuit (A) 100.
7, a scanning signal driving circuit (B) 1011, a precharge circuit 1012, and a pixel circuit 1006. In this specification, the driving circuit includes an image signal processing circuit 10
01 and the scanning signal drive circuit 1007.

The image signal driving circuit 1001 includes a shift register circuit 1002, a level shifter circuit 1003, a buffer circuit 1004, and a sampling circuit 1005. The scan signal driver circuit (A) 1007 includes a shift register circuit 1008, a level shifter circuit 1009, and a buffer circuit 1010. The scanning signal driving circuit (B) 1011 has a similar configuration.

The structure of this embodiment can be easily realized by fabricating a TFT according to the steps shown in FIGS. In this embodiment, only the configurations of the pixel circuit and the driving circuit are shown. However, according to the manufacturing process of this embodiment, other components such as a signal dividing circuit, a frequency dividing circuit, and a D / A
A signal processing circuit (also referred to as a logic circuit) such as a converter circuit, an operational amplifier circuit, a γ correction circuit, and a microprocessor circuit can be formed over the same substrate.

As described above, the present invention provides a semiconductor device including at least a pixel circuit and a driving circuit for driving the pixel circuit on the same substrate, for example, a signal processing circuit on the same substrate.
A semiconductor device including a driving circuit and a pixel circuit can be realized.

When the steps up to FIG. 7B of this embodiment are performed, a crystalline silicon film having a unique crystal structure having continuity in the crystal lattice is formed. Hereinafter, the features of the crystal structure experimentally examined by the present applicant will be briefly described. In addition,
This feature coincides with the feature of the semiconductor layer forming the active layer of the TFT completed by this embodiment.

The crystalline silicon film has a crystal structure in which a plurality of needle-like or rod-like crystals (hereinafter abbreviated as rod-like crystals) are gathered and lined up microscopically. This is T
It can be easily confirmed by observation by EM (transmission electron microscopy).

The crystalline silicon film of this example has extremely few defects in crystal grains and can be regarded as having substantially no crystal grain boundaries. Therefore, it is considered that the crystalline silicon film is a single crystal silicon film or a substantially single crystal silicon film. good.

The structure of this embodiment can be freely combined with any of the structures of the first to fourth embodiments.

[Embodiment 6] The present invention relates to a conventional MOSFET.
It is also possible to form an interlayer insulating film thereon and use it when forming a TFT thereon. That is, it is possible to realize a semiconductor device having a three-dimensional structure. In addition, S
An SOI substrate such as IMOX, Smart-Cut (registered trademark of SOITEC), ELTRAN (registered trademark of Canon Inc.) can also be used.

The structure of this embodiment can be freely combined with any of the structures of the first to fifth embodiments.

[Embodiment 7] The present invention can also be applied to an active matrix EL display. An example is shown in FIG.

FIG. 12 is a circuit diagram of an active matrix EL display. Reference numeral 81 denotes a pixel circuit, around which an X-direction drive circuit 82 and a Y-direction drive circuit 83 are provided. Each pixel of the pixel circuit 81 has a switching TFT 84, a capacitor 85, a current control TFT 86, and an organic EL element 87. The switching TFT 84 has an X-direction signal line 88a (or 88b).
), And the Y direction signal line 89a (or 89b, 89c) are connected. Power supply lines 90a and 90b are connected to the current control TFT 86.

In the active matrix type EL display of this embodiment, the TFTs used for the X-direction drive circuit 82, the Y-direction drive circuit 83 or the current control TFT 86 are replaced by the p-channel TFT 301 and the n-channel TFT 302 shown in FIG. Alternatively, it is formed by combining 303. Further, the TFT of the switching TFT 84 is formed by the n-channel TFT 804 in FIG. 9B.

It should be noted that any of the structures of the first to sixth embodiments may be combined with the active matrix EL display of the present embodiment.

[Embodiment 8] Various liquid crystal materials can be used for a liquid crystal display device manufactured according to the present invention. Such materials include TN liquid crystal, PDLC (polymer dispersed liquid crystal), FLC (ferroelectric liquid crystal), AFLC
(Antiferroelectric liquid crystal) or a mixture of FLC and AFLC (antiferroelectric mixed liquid crystal).

For example, “H. Furue et al .; Charakteristi
cs and Drivng Scheme of Polymer-Stabilized Monosta
ble FLCD Exhibiting Fast Response Time and High Co
ntrast Ratio with Gray-Scale Capability, SID, 199
8 "," T. Yoshida et al .; A Full-Color Thresholdless "
Antiferroelectric LCD Exhibiting Wide Viewing Ang
le with Fast Response Time, 841, SID97DIGEST, 199
7 "," S. Inui et al .; Thresholdless antiferroelectr
icity in liquid crystals and its application to di
splays, 671-673, J. Mater. Chem. 6 (4), 1996 ", or the materials disclosed in U.S. Patent No. 5,594,569.

In particular, a thresholdless antiferroelectric liquid crystal (TL-TL) exhibiting an electro-optical response characteristic in which the transmittance changes continuously with respect to an electric field.
AFLC) has a V-shaped (or U-shaped) electro-optical response characteristic, and its driving voltage is about ±
Some have a voltage of about 2.5 V (cell thickness of about 1 μm to 2 μm). Therefore, the power supply voltage for the pixel circuit is 5 to 8
In some cases, the voltage may be about V, which suggests that the driving circuit and the pixel circuit may be operated at the same power supply voltage. That is, power consumption of the entire liquid crystal display device can be reduced.

The ferroelectric liquid crystal and the antiferroelectric liquid crystal are T
There is an advantage that the response speed is faster than that of the N liquid crystal. TFTs used in the present invention are very fast operating TFTs
Therefore, it is possible to realize a liquid crystal display device having a high image response speed by making full use of the response speed of the ferroelectric liquid crystal and the antiferroelectric liquid crystal.

In general, a thresholdless antiferroelectric mixed liquid crystal has a large spontaneous polarization and a high dielectric constant of the liquid crystal itself. Therefore, when a thresholdless antiferroelectric mixed liquid crystal is used for a liquid crystal display device, a relatively large storage capacitance is required for a pixel. Therefore, it is preferable to use a thresholdless antiferroelectric mixed liquid crystal having a small spontaneous polarization. In that sense, the storage capacitor of Embodiment 5 shown in FIG. 9B is preferable because a large capacitance can be stored in a small area.

It is needless to say that it is effective to use the liquid crystal display device of this embodiment as a display for electronic equipment such as a personal computer.

The structure of this embodiment can be freely combined with any of the structures of the first to seventh embodiments.

[Embodiment 9] In this embodiment, an example in which an EL (electroluminescence) display device is manufactured by using the present invention will be described. FIG. 13 (A) shows E of the present invention.
FIG. 13B is a top view of the L display device, and FIG. 13B is a cross-sectional view thereof.

In FIG. 13A, reference numeral 4001 denotes a substrate;
4002 is a pixel portion, 4003 is a source side driver circuit, 40
Reference numeral 04 denotes a gate-side drive circuit. Each drive circuit reaches an FPC (flexible print circuit) 4006 via a wiring 4005 and is connected to an external device.

At this time, a first sealant 4101, a cover 4102, a filler 4103, and a second sealant 4104 are provided so as to surround the pixel portion 4002, the source side drive circuit 4003, and the gate side drive circuit 4004.

FIG. 13 (B) shows FIG. 13 (A) as A-
The driving TFTs included in the source-side driving circuit 4003 on the substrate 4001 (however,
Here, an n-channel TFT and a p-channel TFT are illustrated. ) 4201 and a current controlling TFT (TF controlling the current to the EL element) included in the pixel portion 4002.
T) 4202 is formed.

In this embodiment, a TFT having the same structure as the p-channel TFT or the n-channel TFT shown in FIG.
Uses a TFT having the same structure as the p-channel TFT of FIG. The pixel portion 4002 has a current controlling TFT.
A storage capacitor (not shown) connected to the gate of 4202 is provided.

Driving TFT 4201 and Pixel TFT 420
On top of 2 is an interlayer insulating film (planarization film) made of an organic resin material
4301 are formed, and a pixel electrode (anode) 4302 electrically connected to the drain of the pixel TFT 4202 is formed thereon. As the pixel electrode 4302, a transparent conductive film having a large work function is used. As the transparent conductive film, a compound of indium oxide and tin oxide, a compound of indium oxide and zinc oxide, zinc oxide, tin oxide, or indium oxide can be used. Further, a material obtained by adding gallium to the transparent conductive film may be used.

Then, an insulating film 4303 is formed on the pixel electrode 4302, and the insulating film 4303 is formed on the pixel electrode 430.
2, an opening is formed. In this opening, an EL (electroluminescence) layer 4304 is formed on the pixel electrode 4302. For the EL layer 4304, a known organic EL material or inorganic EL material can be used. As the organic EL material, there are a low-molecular (monomer) material and a high-molecular (polymer) material, and either may be used.

[0168] As a method for forming the EL layer 4304, a known vapor deposition technique or coating technique may be used. The EL layer may have a stacked structure or a single-layer structure by freely combining a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, or an electron injection layer.

On the EL layer 4304, a cathode 4305 made of a light-shielding conductive film (typically, a conductive film containing aluminum, copper, or silver as a main component or a laminated film of these and another conductive film) is provided. It is formed. In addition, the cathode 4305
It is desirable that moisture and oxygen existing at the interface between the EL layer and the EL layer 4304 be eliminated as much as possible. Therefore, the two layers are continuously formed in a vacuum or the EL layer 4304 is formed in a nitrogen or rare gas atmosphere, and the cathode 430 is not exposed to oxygen or moisture.
5 is required. In this embodiment, the above-described film formation is made possible by using a multi-chamber type (cluster tool type) film formation apparatus.

The cathode 4305 is electrically connected to the wiring 4005 in a region 4306. A wiring 4005 is a wiring for applying a predetermined voltage to the cathode 4305, and an FPC through an anisotropic conductive film 4307.
4006.

As described above, the pixel electrode (anode) 43
02, an EL element including the EL layer 4304 and the cathode 4305 is formed. This EL element has a first sealing material 410
Are surrounded by a cover material 4102 bonded to the substrate 4001 by the first and first seal materials 4101,
3 enclosed.

As the cover material 4102, a glass material, a metal material (typically, a stainless steel material), a ceramic material, and a plastic material (including a plastic film) can be used. As a plastic material, FRP (Fi
Berglass-Reinforced Plast
ics) plate, PVF (polyvinyl fluoride) film, mylar film, polyester film or acrylic resin film. Further, a sheet having a structure in which an aluminum foil is sandwiched between PVF films or mylar films can also be used.

However, when the direction of light emission from the EL element is directed toward the cover material, the cover material must be transparent. In that case, a transparent material such as a glass plate, a plastic plate, a polyester film or an acrylic film is used.

As the filler 4103, an ultraviolet curable resin or a thermosetting resin can be used. PVC (polyvinyl chloride), acrylic, polyimide, epoxy resin, silicone resin, PVB (polyvinyl butyral) or EVA (ethylene vinyl) is used. Acetate) can be used. By providing a hygroscopic substance (preferably barium oxide) or a substance capable of adsorbing oxygen inside the filler 4103, deterioration of the EL element can be suppressed.

A spacer may be contained in the filler 4103. At this time, if the spacer is made of barium oxide, the spacer itself can have hygroscopicity. In the case where a spacer is provided, it is also effective to provide a resin film on the cathode 4305 as a buffer layer for relaxing pressure from the spacer.

The wiring 4005 is electrically connected to the FPC 4006 via the anisotropic conductive film 4307. The wiring 4005 transmits a signal transmitted to the pixel portion 4002, the source driver circuit 4003, and the gate driver circuit 4004 to the FPC 4006, and is electrically connected to an external device by the FPC 4006.

In this embodiment, the first sealing material 4101 is used.
A second sealing material 4104 is provided so as to cover the exposed part of the FPC 4006 and a part of the FPC 4006, and the EL element is completely shut off from the outside air. Thus, an EL display device having the cross-sectional structure of FIG.

Note that the EL display device of this embodiment is the same as that of the first embodiment.
Any of the structures of the above-described structures 7 to 7 may be combined.

[Embodiment 10] FIG. 14 shows a more detailed sectional structure of the pixel portion, FIG. 15A shows a top structure thereof, and FIG. 15B shows a circuit diagram thereof. In FIGS. 14, 15A and 15B, a common reference numeral is used, so that they may be referred to each other.

In FIG. 14, a switching TFT 4402 provided on a substrate 4401 is formed using the n-channel TFT shown in FIG. Therefore, the description of the structure is n
See the description of the channel type TFT. Also, 44
The wiring denoted by 03 is a switching TFT 4402
This is a gate wiring for electrically connecting the gate electrodes 4404a and 4404b.

Although the present embodiment has a double gate structure in which two channel formation regions are formed, a single gate structure in which one channel formation region is formed or a triple gate structure in which three channel formation regions are formed. good.

The drain wiring 4405 of the switching TFT 4402 is electrically connected to the gate electrode 4407 of the current control TFT 4406. Note that the current control TFT 4406 is formed using the p-channel TFT of FIG. Therefore, the description of the structure is p-channel type T
See the description of FT. In this embodiment, a single gate structure is used, but a double gate structure or a triple gate structure may be used.

The first passivation film 4 is formed on the switching TFT 4402 and the current control TFT 4406.
408 are provided, and a planarizing film 44 made of resin is provided thereon.
09 is formed. It is very important to flatten the step due to the TFT using the flattening film 4409. Since an EL layer formed later is extremely thin, poor light emission may be caused by the presence of a step. Therefore, it is desirable that the EL layer be flattened before forming the pixel electrode so that the EL layer can be formed as flat as possible.

Reference numeral 4410 denotes a pixel electrode (anode of an EL element) made of a transparent conductive film.
06 is electrically connected to the drain wiring 4417. As the transparent conductive film, a compound of indium oxide and tin oxide, a compound of indium oxide and zinc oxide, zinc oxide,
Tin oxide or indium oxide can be used.
Further, a material obtained by adding gallium to the transparent conductive film may be used.

On the pixel electrode 4410, an EL layer 4411 is provided.
Is formed. Although only one pixel is shown in FIG. 14, in this embodiment, EL layers corresponding to R (red), G (green), and B (blue) are separately formed. In this embodiment, a low-molecular organic EL material is formed by an evaporation method. Specifically, a 20 nm thick copper phthalocyanine (CuPc) film is provided as a hole injection layer, and a 70 nm thick tris-8-quinolinolato aluminum complex (Alq3) film is provided thereon as a light emitting layer. I have. Al
The emission color can be controlled by adding a fluorescent dye such as quinacridone, perylene or DCM1 to q3.

However, the above example is an example of the organic EL material that can be used for the EL layer, and it is not necessary to limit the invention to this. An EL layer (a layer for performing light emission and carrier movement therefor) may be formed by freely combining a light emitting layer, a charge transport layer, or a charge injection layer. For example, in this embodiment, a low molecular organic EL material is
Although an example in which the layer is used as a layer has been described, a polymer organic EL material may be used. It is also possible to use an inorganic material such as silicon carbide for the charge transport layer and the charge injection layer. Known materials can be used for these organic EL materials and inorganic materials.

Next, a cathode 4412 made of a conductive film is provided on the EL layer 4411. In this embodiment, an alloy film of aluminum and lithium is used as the conductive film.
Of course, a known MgAg film (an alloy film of magnesium and silver) may be used. As the cathode material, a conductive film made of an element belonging to Group 1 or 2 of the periodic table or a conductive film to which those elements are added may be used.

At the time when the cathode 4412 is formed, E
The L element 4413 is completed. Note that the EL element 4413 here includes a pixel electrode (anode) 4410 and an EL layer 441.
1 and a capacitor formed by the cathode 4412.

Next, the top structure of the pixel in this embodiment will be described with reference to FIG. Switching TFT
The source region 4402 is connected to the source wiring 4415, and the drain is connected to the drain wiring 4405. Further, the drain wiring 4405 is connected to the current control TFT 4406.
Electrically connected to the gate electrode 4407 of The source region of the current control TFT 4406 is connected to the current supply line 44.
16 and the drain is a drain wiring 44
17 is electrically connected. Also, the drain wiring 441
Reference numeral 7 is electrically connected to a pixel electrode (anode) 4418 indicated by a dotted line.

At this time, a storage capacitor is formed in a region indicated by 4419. The storage capacitor 4419 is formed between the semiconductor film 4420 electrically connected to the current supply line 4416, an insulating film (not shown) in the same layer as the gate insulating film, and the gate electrode 4407. In addition, the gate electrode 440
7. A capacitor formed by the same layer (not shown) as the first interlayer insulating film and the current supply line 4416 can also be used as a storage capacitor.

[Embodiment 11] In this embodiment, the tenth embodiment will be described.
An EL display device having a pixel structure different from that described above will be described. FIG. 16 is used for the description. Note that the description of the tenth embodiment may be referred to for the portions denoted by the same reference numerals as in FIG.

In FIG. 16, a TFT having the same structure as the n-channel TFT of FIG. 9 is used as the current control TFT 4501. Of course, the gate electrode 45 of the current control TFT 4501
02 is the drain wiring 4 of the switching TFT 4402
405 is electrically connected. Also, the current control T
The drain wiring 4503 of the FT 4501 is connected to the pixel electrode 450
4 is electrically connected.

In this embodiment, the pixel electrode 4 made of a conductive film is used.
504 functions as a cathode of the EL element. In particular,
Although an alloy film of aluminum and lithium is used, a conductive film made of an element belonging to Group 1 or 2 of the periodic table or a conductive film to which those elements are added may be used.

On the pixel electrode 4504, an EL layer 4505 is provided.
Is formed. Although only one pixel is shown in FIG. 16, in this embodiment, an EL layer corresponding to G (green) is formed by an evaporation method and a coating method (preferably a spin coating method). Specifically, 20n is used as the electron injection layer.
It has a laminated structure in which a m-thick lithium fluoride (LiF) film is provided, and a 70-nm-thick PPV (polyparaphenylene vinylene) film is provided thereon as a light emitting layer.

Next, an anode 4506 made of a transparent conductive film is provided on the EL layer 4505. In the case of this embodiment,
As the transparent conductive film, a conductive film including a compound of indium oxide and tin oxide or a compound of indium oxide and zinc oxide is used.

When this anode 4506 is formed, E
The L element 4507 is completed. Note that the EL element 4507 used here includes a pixel electrode (cathode) 4504 and an EL layer 450.
5 and the anode 4506.

When the voltage applied to the EL element is as high as 10 V or more, deterioration of the current control TFT 4501 due to the hot carrier effect becomes apparent. In such a case, it is effective to use an n-channel TFT having the structure of the present invention as the current control TFT 4501. Thus, a function equivalent to that of the storage capacitor 4418 illustrated in FIGS. 15A and 15B can be provided. In particular, when the EL display device is operated by the digital driving method, the capacitance of the storage capacitor can be smaller than that when the EL display device is operated by the analog driving method.

When the voltage applied to the EL element is 10 V or less, preferably 5 V or less, the deterioration due to the hot carrier effect does not cause much problem.
In FIG. 16, n has a structure in which the LDD region 4509 is omitted.
A channel type TFT may be used.

[Embodiment 12] In this embodiment, Embodiment 10 will be described.
Alternatively, FIGS. 17A to 17C illustrate examples of a pixel structure that can be used for a pixel portion of the EL display device described in Embodiment 11.
Shown in In this embodiment, reference numeral 4601 denotes a source wiring of the switching TFT 4602, 4603 denotes a gate wiring of the switching TFT 4602, 4604 denotes a current controlling TFT, 4605 denotes a capacitor, 4606 and 46.
08 is a current supply line, and 4607 is an EL element.

FIG. 17A shows an example in which a current supply line 4606 is shared between two pixels. That is, it is characterized in that the two pixels are formed to be line-symmetric with respect to the current supply line 4606. In this case, the number of power supply lines can be reduced, so that the pixel portion can have higher definition.

FIG. 17B shows a current supply line 460.
8 is provided in parallel with the gate wiring 4603. Note that FIG. 17B illustrates a structure in which the current supply line 4608 and the gate wiring 4603 are provided so as not to overlap with each other.
They can be provided so as to overlap with each other via an insulating film. In this case, since the power supply line 4608 and the gate wiring 4603 can share an occupied area, the pixel portion can have higher definition.

FIG. 17C shows that the current supply line 4608 is provided in parallel with the gate wiring 4603 and two pixels are connected to the current supply line 4608 in the same manner as in the structure of FIG. 17B.
It is characterized in that it is formed so as to be line-symmetric with respect to.
It is also effective to provide the current supply line 4608 so as to overlap with one of the gate wirings 4603. In this case, the number of power supply lines can be reduced, so that the pixel portion can have higher definition.

Embodiment 13 The EL display device according to any one of Embodiments 9 to 12 may have a structure in which any number of TFTs are provided in one pixel. For example, three to six or more TFTs may be provided. The present invention can be implemented without being limited to the pixel structure of the EL display device.

[Embodiment 14] A CMOS circuit and a pixel portion formed by carrying out the invention of the present application may be implemented by various electro-optical devices (active matrix liquid crystal display, active matrix EL display, active matrix E).
C display). That is, the invention of the present application can be applied to all electronic devices in which these electro-optical devices are incorporated in a display unit.

Such electronic devices include a video camera, digital camera, projector (rear or front type), head mounted display (goggle type display), car navigation, car stereo,
Examples include a personal computer and a portable information terminal (a mobile computer, a mobile phone, an electronic book, or the like). Examples of these are shown in FIGS. 18, 19 and 20.

FIG. 18A shows a personal computer, which includes a main body 2001, an image input section 2002, and a display section 20.
03, a keyboard 2004 and the like. The present invention can be applied to the image input unit 2002, the display unit 2003, and other driving circuits.

FIG. 18B shows a video camera, which includes a main body 2101, a display portion 2102, an audio input portion 2103, operation switches 2104, a battery 2105, and an image receiving portion 210.
6 and so on. The present invention can be applied to the display portion 2102 and other driver circuits.

FIG. 18C shows a mobile computer (mobile computer), which includes a main body 2201, a camera section 2202, an image receiving section 2203, operation switches 2204, a display section 2205, and the like. The present invention can be applied to the display portion 2205 and other driving circuits.

FIG. 18D shows a goggle type display, which includes a main body 2301, a display portion 2302, and an arm portion 230.
3 and so on. The present invention can be applied to the display portion 2302 and other driving circuits.

FIG. 18E shows a player using a recording medium on which a program is recorded (hereinafter, referred to as a recording medium), and includes a main body 2401, a display section 2402, and a speaker section 240.
3, a recording medium 2404, an operation switch 2405, and the like. This player uses a DVD (D
digital Versatile Disc), CD
And the like, it is possible to perform music appreciation, movie appreciation, games, and the Internet. The present invention can be applied to the display portion 2402 and other driving circuits.

FIG. 18F shows a digital camera, which includes a main body 2501, a display section 2502, an eyepiece section 2503, operation switches 2504, an image receiving section (not shown), and the like. The present invention can be applied to the display portion 2502 and other driving circuits.

FIG. 19A shows a front type projector, which includes a projection device 2601, a screen 2602, and the like. The present invention can be applied to the liquid crystal display device 2808 forming a part of the projection device 2601 and other driving circuits.

FIG. 19B shows a rear type projector, which includes a main body 2701, a projection device 2702, and a mirror 270.
3, including a screen 2704 and the like. The present invention relates to a projection device 2
The present invention can be applied to a liquid crystal display device 2808 forming a part of the LCD 702 and other driving circuits.

FIG. 19C is a diagram showing an example of the structure of the projection devices 2601 and 2702 in FIGS. 19A and 19B. Projection devices 2601, 27
02 denotes a light source optical system 2801, mirrors 2802, 280
4 to 2806, dichroic mirror 2803, prism 2807, liquid crystal display device 2808, retardation plate 280
9. The projection optical system 2810. Projection optical system 28
Reference numeral 10 denotes an optical system including a projection lens. In the present embodiment, an example of a three-plate type is shown, but there is no particular limitation, and for example, a single-plate type may be used. Further, the practitioner may appropriately provide an optical system such as an optical lens, a film having a polarizing function, a film for adjusting a phase difference, and an IR film in an optical path indicated by an arrow in FIG. Good.

FIG. 19D shows an example of the structure of the light source optical system 2801 in FIG. 19C. In this embodiment, the light source optical system 2801 includes a reflector 2811, a light source 2812, a lens array 2813,
814, a polarization conversion element 2815, and a condenser lens 2816. Note that the light source optical system shown in FIG. 19D is an example and is not particularly limited. For example, a practitioner may appropriately provide an optical system such as an optical lens, a film having a polarizing function, a film for adjusting a phase difference, and an IR film in the light source optical system.

However, in the projector shown in FIG. 19, a case where a transmissive electro-optical device is used is shown, and examples of application to a reflective electro-optical device and an EL display device are not shown.

FIG. 20A shows a mobile phone,
01, audio output unit 2902, audio input unit 2903, display unit 2904, operation switch 2905, antenna 2906
And so on. The present invention can be applied to the audio output unit 2902, the audio input unit 2903, the display unit 2904, and other driving circuits.

FIG. 20B shows a portable book (electronic book), which includes a main body 3001, display portions 3002 and 3003, a storage medium 3004, operation switches 3005, and an antenna 3006.
And so on. The present invention can be applied to the display units 3002 and 3003 and other signal circuits.

FIG. 20C shows a display, which includes a main body 3101, a support 3102, a display portion 3103, and the like.
The present invention can be applied to the display portion 3103. The display of the present invention is particularly advantageous when the screen is enlarged, and is advantageous for a display having a diagonal of 10 inches or more (particularly 30 inches or more).

As described above, the applicable range of the present invention is extremely wide, and the present invention can be applied to electronic devices in various fields. Further, the electronic apparatus of the present embodiment can be realized by using a configuration composed of any combination of Embodiments 1 to 13.

[0221]

As described above, by using an organic material for the interlayer insulating film and using the first metal film as a mask in the dry etching step, a contact hole (having a diameter of 3 μm or less, preferably, less than the conventional one) can be obtained. , 2 μm to 0.
(Having 1 μm) can be realized.

In the present invention, since the first interlayer insulating film is formed of an organic material, the first interlayer insulating film can be sufficiently flattened as compared with a case where an inorganic material is used. Furthermore, when the second and third interlayer insulating films are formed of an organic material, a pixel electrode can be formed in a sufficiently flattened region, so that a rubbing treatment can be reliably performed, and disturbance of liquid crystal alignment can be prevented. Can be suppressed.

Further, by using a metal material having a lower resistance than the second metal layer as the first metal film, the resistance of the wiring can be reduced. In addition, by using a metal material capable of forming a favorable contact interface with a semiconductor layer (for example, silicon) as the second metal film, contact failure can be reduced.

Further, since a sufficient selection ratio between the organic material and the semiconductor layer containing silicon as a main component can be obtained, a minute contact hole can be formed, and the size of the display element can be reduced. As a result, it is possible to increase the aperture ratio.

[Brief description of the drawings]

FIG. 1 is a diagram showing an example of the structure of the present invention (Example 1).

FIG. 2 shows an example of a manufacturing process of the present invention (Example 2).

FIG. 3 is a view showing one example of a manufacturing process of the present invention (Example 2).

FIG. 4 is a view showing an example of the structure of the present invention (Example 3).

FIG. 5 is a view showing an example of the structure of the present invention (Example 4).

FIG. 6 shows an example of a manufacturing process of the present invention (Example 5).

FIG. 7 illustrates an example of a manufacturing process of the present invention (Example 5).

FIG. 8 shows an example of a manufacturing process of the present invention (Example 5).

FIG. 9 illustrates an example of a manufacturing process of the present invention (Example 5).

FIG. 10 shows an example of the structure of the present invention (Example 5).

FIG. 11 shows an example of the structure of the present invention (Example 5).

FIG. 12 shows an example of the structure of the present invention (Embodiment 7).

13A and 13B are a cross-sectional view and a top view of an active matrix EL display device (Example 9).

FIG. 14 is a cross-sectional view of an active matrix EL display device (Example 10).

FIG. 15 is a diagram showing a top view of an active matrix EL display device (Example 10).

FIG. 16 is a diagram showing a cross-sectional view of an active matrix EL display device (Example 11).

FIG. 17 shows a structure of an active matrix EL display device (Example 12).

FIG. 18 illustrates an example of an electronic apparatus (Example 14).

FIG. 19 illustrates an example of an electronic apparatus (Example 14).

FIG. 20 illustrates an example of an electronic apparatus (Example 14).

Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat II (Reference) H01L 21/336 H01L 21/90 S 29/78 612C 616U 616K (72) Inventor Etsuko Fujimoto 398 Hase, Atsugi-shi, Kanagawa Stock Company Semiconductor Energy Laboratory

Claims (11)

[Claims] An interlayer insulating film made of an organic material on a material layer having conductivity; a first metal layer on the interlayer insulating film;
A second metal layer on the first metal layer, wherein the conductive material layer and the second metal layer are connected at a bottom of a contact hole provided in the interlayer insulating film; A semiconductor device characterized by the above-mentioned. 2. An interlayer insulating film made of an organic material on a thin film transistor; a first metal layer on the interlayer insulating film; a second metal layer on the first metal layer; A semiconductor device, wherein a source region or a drain region of the thin film transistor is connected to the second metal layer at a bottom of the provided contact hole. 3. The semiconductor device according to claim 1, wherein the first metal layer is made of aluminum or a material containing aluminum as a main component. 4. The semiconductor device according to claim 1, wherein said second metal layer is made of titanium or a material containing titanium as a main component. 5. An interlayer insulating film according to claim 1, wherein said interlayer insulating film is made of polyimide, polyimide amide, polyamide, acrylic, or BCB (benzocyclobutene).
1. A semiconductor device comprising an organic resin material containing as a main component. 6. The semiconductor device according to claim 1, wherein the semiconductor device is an active matrix type liquid crystal display device, an active matrix type EL display device or an active matrix type EC display device. Semiconductor device. 7. The semiconductor device according to claim 1, wherein the semiconductor device is a video camera, a digital camera, a projector, a goggle type display, a car navigation, a personal computer, or a portable information terminal. Semiconductor device. 8. A step of forming a thin film transistor on an insulating surface, a step of forming an interlayer insulating film made of an organic material over the thin film transistor, and forming a first metal film over the interlayer insulating film. Forming a first metal layer by patterning the first metal film, etching the interlayer insulating film using the first metal layer as a mask, and forming a contact hole. , The first
Forming a second metal film covering the first metal layer and the contact hole, and patterning the first metal layer and the second metal film to form a wiring partially having a laminated structure And a method for manufacturing a semiconductor device. 9. A step of forming a first material layer having conductivity on an insulating surface; a step of forming an interlayer insulating film made of an organic material over the first material layer; Forming a first metal film over the film, patterning the first metal film to form a first metal layer, and using the first metal layer as a mask, Etching the film to form a contact hole;
Forming a second metal film over the first metal layer and the contact hole, forming an inorganic insulating film over the second metal film, and forming the first metal film over the second metal film; Patterning a layer, the second metal film, and the inorganic insulating film to form a wiring having an inorganic insulating layer on an upper surface;
Forming a conductive second material layer in contact with the wiring, and forming a capacitor between the wiring and the second material layer using the inorganic insulating layer as a dielectric. A method for manufacturing a semiconductor device. 10. The inorganic insulating film according to claim 9, wherein:
A method for manufacturing a semiconductor device, which is formed by a CVD method. 11. The method for manufacturing a semiconductor device according to claim 8, wherein the first metal film and the second metal film are formed by a sputtering method.