JP2004241750A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device and its manufacturing method solving the problem of crack of a semiconductor film, a capacitive electrode, etc., caused by a stress generated in forming a source electrode and a drain electrode in a semiconductor device having a thin-film transistor and more than two capacitive elements. <P>SOLUTION: Before a source electrode and a drain electrode are formed, a crystalline silicon film reducing stress is formed. After that, a contact hole connecting with the semiconductor film of a thin-film transistor is opened to form a metal film that becomes the source electrode and the drain electrode. By this invention, a semiconductor device having a TFT and a plurality of capacitive elements while inhibiting the stress crack of the semiconductor film, the capacitive electrode, etc. can be formed. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device including a thin film transistor (hereinafter, referred to as a TFT) and a capacitor (capacitor) and a manufacturing method thereof. In addition, the present invention relates to a display device including a semiconductor device including a TFT and a capacitor, particularly to an electronic device in which a liquid crystal display device, an EL display device, and a projector are mounted as components, and a method for manufacturing the electronic device. Note that in this specification, a semiconductor device generally means a device that can function by utilizing semiconductor characteristics, and a display device, a semiconductor circuit, and an electronic device are all semiconductor devices.
[0002]
[Prior art]
2. Description of the Related Art In recent years, a TFT is formed using a thin film (having a thickness of about several to several hundred nm) formed on a substrate having an insulating surface, and a semiconductor device having an integrated circuit formed by the TFT has been developed. As a typical example, an active matrix type liquid crystal display device is known. In particular, since a TFT using a crystalline silicon film as an active region has high field-effect mobility, various functional circuits can be formed.
[0003]
For example, in an active matrix type liquid crystal display device, a pixel circuit for displaying an image for each functional block and a pixel circuit such as a shift register circuit, a level shifter circuit, a buffer circuit, and a sampling circuit based on a CMOS circuit are controlled. Can be formed on one substrate, and the circuit can be formed by TFT.
[0004]
In addition, the use of semiconductor devices typified by active matrix type liquid crystal display devices has been expanding more and more, and accordingly, convenience has been demanded, and miniaturization, high brightness, high definition, and low price have been achieved. Development to advance such things is continuing.
[0005]
For example, a pixel portion of an active matrix type liquid crystal display device used for a display portion of a liquid crystal projector or an electronic device is composed of millions of pixels, and each pixel is provided with a TFT. A counter electrode is provided on the counter substrate side sandwiching the liquid crystal, and forms a kind of capacitor using the liquid crystal as a dielectric. Next, the charge stored in this capacitor is controlled by the switching function of the TFT. Thus, the liquid crystal is driven by controlling the potential applied to each pixel, and the amount of transmitted or reflected light is controlled to display an image.
[0006]
In particular, in a small, high-definition transmissive liquid crystal display device used for a liquid crystal projector, as long as miniaturization and high definition are required, it is expected that the pixel size will continue to be reduced. For example, in order to realize a high-definition display of XGA (1024 × 768 pixels) with a 0.7-inch diagonal liquid crystal display device, each pixel has an extremely small area of 14 μm × 14 μm. ing.
[0007]
In a transmissive liquid crystal display device, when a capacitor is formed using a capacitor wiring in a pixel portion to secure a sufficient capacitance, the aperture ratio must be sacrificed. At present, these problems have been addressed by increasing the aperture ratio for higher brightness and increasing the number of pixels for higher definition. It is extremely difficult to design a pixel structure capable of simultaneously satisfying the increase in the rate and the increase in the number of pixels and securing a sufficient capacity.
[0008]
As a solution to the above problem, in order to increase the aperture ratio, the area of the TFT and the area of the capacitor which are dead spaces are reduced, the width of the gate electrode and the width of the source wiring are reduced, and the bonding margin between the TFT substrate and the counter substrate is reduced. Improvements such as miniaturization have been made. In particular, using a stacked capacitor to reduce the area of the capacitor is effective as the above solution. (Patent Document 1)
[0009]
The stack capacitor is a capacitive element having a structure in which three or more capacitance electrodes are stacked via two or more dielectrics. In this specification, only the case where the capacitance electrode has three layers will be described. However, the present invention is not limited to this structure, and a plurality of capacitance electrodes may be provided. In this specification, a case where the first capacitor electrode is formed simultaneously with the semiconductor layer of the TFT and the second capacitor electrode is formed simultaneously with the gate electrode, and the dielectric layer separating the two is a gate insulating film is mainly described. Although described, it is not necessarily limited to only this configuration.
[0010]
FIG. 2 shows a method for manufacturing a conventional stack capacitor. The semiconductor film formed on the substrate is selectively etched using a known technique related to patterning and etching to form the semiconductor film 14 of the TFT and the first capacitance electrode 15 of the stack capacitor, and then the first An insulating film 13 serving as a dielectric is formed. Next, a gate electrode 32 and a second capacitance electrode 33 are formed. The second capacitance electrode 33 is a capacitance wiring whose potential is fixed to a ground potential or the like. After that, a second insulating film 34 serving as a second dielectric is formed. (FIG. 2 (A)).
[0011]
After a part of the first insulating film and the second insulating film is etched to form a contact hole 40, a source electrode, a drain electrode, which is a connection wiring, and a second conductive film 35 which becomes a third capacitance electrode are formed. It is formed so as to be connected to the semiconductor film 14 of the TFT. (FIG. 2 (C)).
[0012]
Subsequently, after the second conductive film is etched to form the source electrode, the drain electrode 41, and the third capacitor electrode 42, the source electrode and the drain electrode, the second insulating film, and the third capacitor electrode are covered. A third insulating film 36 is formed. (FIG. 2 (D)). Thereafter, a part of the third insulating film is etched to form a contact hole reaching the source electrode and the drain electrode, and then a third conductive film is formed and selectively etched to form the connection wiring 38. I do. (FIG. 2E). Although not shown in FIG. 1, the first capacitance electrode 15 and the third capacitance electrode 42 are electrically connected, and are connected to another wiring or TFT so as to apply a predetermined voltage.
[0013]
In the capacitance element, it is possible to hold more capacitance charge by reducing the thickness of the dielectric.
[0014]
However, when the thickness of the dielectric is reduced, when the subsequent conductive film is formed by a sputtering method, the dielectric is likely to be damaged due to the impact of sputtering. Specifically, when forming the second capacitance electrode 33 and the third capacitance electrode 42, a defect occurs in the first dielectric 13 and the second dielectric 34 that are in contact with those electrodes, As a result, a short circuit may occur between the first capacitance electrode 15 and the second capacitance electrode 33 or between the second capacitance electrode 33 and the third capacitance electrode 42.
[0015]
Further, when the second conductive film 35 is formed on the insulating film 34 which is a dielectric, the stress of the conductive film 35 causes a problem that the semiconductor film 14 and the first capacitor electrode 15 of the TFT are cracked and cracked. .
[0016]
As a countermeasure against this problem, when forming the second conductive film, use of a material that does not apply excessive stress to the lower structure can be cited. However, in this case, the material of the second conductive film is limited. For example, a case where a semiconductor film in which phosphorus is introduced into an impurity element is used as the second conductive film 35 is described. Although the semiconductor film into which phosphorus is introduced and the semiconductor film forming the n-channel TFT can be electrically connected, a pn junction is formed in the semiconductor film forming the p-channel TFT, and conduction cannot be achieved. I will. For this reason, it is necessary to form conductive films made of different materials on the capacitance electrode of the n-channel TFT and the capacitance electrode of the p-channel TFT. This causes a problem that the number of steps increases.
[0017]
[Patent Document 1]
JP-A-5-243519 (pages 2 to 3, FIG. 1)
[0018]
[Problems to be solved by the invention]
The present invention has been made in view of the above problems, and relates to a semiconductor device having a TFT and a plurality of capacitive elements. It is an object to manufacture.
[0019]
[Means for Solving the Problems]
The present invention is a semiconductor device including a plurality of capacitor elements and a thin film transistor which are vertically stacked on an insulating surface, wherein a buffer layer is provided between a dielectric of the capacitor element and a capacitor electrode.
[0020]
That is, a semiconductor device including a thin film transistor, a first capacitor, and a second capacitor formed over an insulating surface, wherein the first capacitor and the second capacitor are formed on the insulating surface. The first capacitive element has a first capacitive electrode and a second capacitive electrode formed with a first dielectric interposed therebetween, and the second capacitive element has: The thin film transistor has the second capacitance electrode and the third capacitance electrode formed through a second dielectric, and the thin film transistor has an active region formed of a semiconductor film, a gate electrode, and a connection connected to the active region. A wiring, and a first insulating film formed between the gate electrode and the connection wiring, between the second dielectric and the third capacitor electrode, and between the first insulating film and the Buffer layer must be formed between connection wiring And it features.
[0021]
Note that the buffer layer is a film that relieves stress generated when the third capacitance electrode and the connection wiring are formed. Typically, it is formed of a crystalline semiconductor film, an amorphous semiconductor film, or the like, and has a thickness of 10 to 100 nm.
[0022]
Further, the buffer layer is not in contact with the active region of the thin film transistor. The connection wiring is a source electrode and a drain electrode, and is connected to the active region of the thin film transistor.
[0023]
In addition, the present invention provides a first capacitor having a first capacitor electrode and a second capacitor electrode formed on an insulating surface, and a second capacitor having the second capacitor electrode and a third capacitor electrode. A method for manufacturing a semiconductor device including a capacitor and a thin film transistor, wherein a semiconductor film is formed over an insulating surface, and the semiconductor film is etched to form an active region of the thin film transistor and the first capacitor electrode. Forming a first insulating film and a first conductive film in order on the active region and the first capacitor electrode, etching the first conductive film to form a gate electrode of the thin film transistor and the second capacitor; After forming the electrodes, a third insulating film and a second conductive film are formed, and the second conductive film, the third insulating film, and the second insulating film are etched to activate the thin film transistor. Expose part of the area Forming a third conductive film, connecting the third conductive film with the active region of the thin film transistor, etching the second conductive film and the third conductive film, and connecting wiring; The method is characterized in that the third capacitance electrode is formed.
[0024]
BEST MODE FOR CARRYING OUT THE INVENTION
A manufacturing process of a semiconductor device which can be manufactured according to the present invention will be described with reference to FIGS.
[0025]
A base insulating film 11 is formed on a substrate 10. The substrate 10 may be a glass substrate, a synthetic quartz glass substrate, a silicon substrate, a metal substrate, or a stainless steel substrate on which an insulating film is formed. Alternatively, a plastic substrate that can withstand the processing temperature may be used. As the base insulating film 11, an insulating film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film is used. Although an example in which a single-layer structure is used as the base insulating film 11 is described here, a structure in which two or more insulating films are stacked may be used. Note that since the base insulating film suppresses diffusion of an impurity element from the substrate, the base insulating film need not be formed when a quartz glass substrate or the like is used as the substrate.
[0026]
Next, a semiconductor film is formed over the base insulating film. After forming a semiconductor film with a thickness of 25 to 200 nm (preferably 30 to 100 nm) by a known means (such as a sputtering method, an LPCVD method, or a plasma CVD method), the semiconductor film is etched into a desired shape. A semiconductor film 15 to be an active region 14 of the TFT and a first capacitor electrode of the capacitor is formed. Although the semiconductor film in the active region of the TFT and the semiconductor film of the capacitor are formed separately in FIG. 1, they may be connected without being separated. In FIG. 1A, the first capacitor is formed as a conductive film by adding impurities to a semiconductor film; however, the present invention is not limited to this. That is, any film having conductivity may be used.
[0027]
In the case where a semiconductor film formed by a known means has an amorphous structure, a known crystallization treatment (laser crystallization method, thermal crystallization method, or thermal crystallization using a catalyst such as nickel) is used. Method, etc. to form a crystalline semiconductor film, and then it is desirable to etch it into a desired shape. Note that there is no limitation on the material of the semiconductor film, but it is preferable that the semiconductor film be formed using silicon or a silicon germanium (SiGe) alloy.
[0028]
Next, a first insulating film 13 covering the semiconductor films 14 and 15 is formed. The first insulating film functions as a gate insulating film. The first insulating film is formed to have a thickness of 40 to 150 nm by a known means (a plasma CVD method, a sputtering method, or the like) to have a single-layer or stacked-layer structure of the insulating film.
[0029]
Next, a first conductive film is formed, and the gate electrode 32 and the second capacitor electrode 33 are formed by selectively etching the first conductive film using a known technique. The second capacitor electrode is a capacitor wire whose potential is fixed to a ground potential or the like. The first conductive film is formed of an element selected from Ta, W, Ti, Mo, Al, and Cu, or an alloy or compound material containing these elements as main components. Alternatively, a semiconductor film typified by a crystalline silicon film doped with an impurity element such as phosphorus may be used. Here, the first conductive film has a single-layer structure; however, two or more layers may be stacked.
[0030]
Next, a second insulating film 34 is formed so as to cover the gate electrode 32 and the first capacitor electrode 33. The second insulating film 34 is formed to have a thickness of 40 to 150 nm by a known means (a plasma CVD method, a sputtering method, or the like) and has a single-layer or stacked-layer structure of the insulating film.
[0031]
Next, using the gate electrode 32 as a mask, an impurity element is selectively introduced into the semiconductor film 14 to form the impurity region 16. As the impurity element, an impurity element imparting n-type or an impurity element imparting p-type is introduced. FIG. 1 shows an example in which a p-type impurity is introduced. Subsequently, heat treatment is performed to activate the impurity element. (Fig. 1 (A))
[0032]
Next, the second conductive film 20 is formed over the second insulating film 34 (FIG. 1B). FIG. 1 illustrates a case where two conductive films are stacked. The buffer layer (the second conductive film 20 formed over the second insulating film 34 in FIG. 1B) is formed to reduce stress applied from an upper conductive film 21 which is formed later. I do. Therefore, the second conductive film is formed using a material capable of relaxing stress. For example, a crystalline silicon film to which phosphorus is added has conductivity, can be formed by an LPCVD method with good step coverage, and is more flexible than a metal element film; The stress applied to the film 34 can be reduced. In FIG. 1, the crystalline silicon film to which phosphorus is added is used as the second conductive film; however, the present invention is not limited to this, and an amorphous silicon film can be used. Further, an organic conductive material (for example, polyphenylenevinylene derivative, polyfluorene derivative, polythiophene derivative, polyphenylene derivative and a copolymer thereof, oligophenylene, oligothiophene, pentacene, tetracene, copper phthalocyanine, fluorine-substituted phthalocyanine, perylene derivative, etc.) may be used. It can also be used. In FIG. 1, the impurity-added regions (source region and drain region) of the TFT are p-type, but the second conductive film 20 is a crystalline silicon film to which phosphorus is added, and is an n-type semiconductor. In addition, the second conductive film cannot be directly connected to the impurity-added region of the TFT. Therefore, the second conductive film is formed before opening a contact hole that directly connects the second conductive film to the semiconductor film of the TFT.
[0033]
Next, an etching process for forming a contact hole reaching the semiconductor film 14 is performed. The etching treatment is performed under the following first to third etching conditions. Of course, in the case where the layers are stacked using the same material, etching can be performed under the same conditions. Even when different materials are used, etching can be performed under the same conditions. Note that it is preferable that any of the etching conditions is performed by a dry etching method typified by a reactive ion etching (RIE) method or an electron cyclotron resonance (ECR) method. This is because dry etching is easier to perform anisotropic etching than wet etching.
[0034]
First, the second conductive film 20 is partially etched under the first etching condition to partially expose the second insulating film 34. Next, the mask made of resist is left as it is, and the second insulating film 34 is etched under the second etching condition to partially expose the first insulating film 13. Further, the first insulating film 13 is etched under the third etching condition, and a part of the semiconductor film 14 is exposed. By the above processing, a contact hole reaching the semiconductor film 14 is formed.
[0035]
Next, a third conductive film 21 is formed over the second conductive film 20. The third conductive film 21 is desirably a metal element film so as to be connectable to both the p-type impurity region and the n-type impurity region of the TFT. Further, it is desirable that the film be made of a material that does not easily react with the semiconductor film of the TFT. Typically, a metal element film containing an element such as Ta, W, Ti, Mo, Al, Cu, Cr, or Nd can be used. In this embodiment mode, a tungsten film is formed. (FIG. 1 (C)).
[0036]
Next, the second conductive film 20 and the third conductive film 30 are selectively etched to form a source electrode / drain electrode 22 and a third capacitance electrode 23 which are connection wirings of the TFT. Is formed. Note that the etching for forming the source electrode, the drain electrode 22, and the third capacitor electrode is etching before flattening the step of the gate electrode, and isotropic etching is preferable. A crystalline silicon film to which tungsten and phosphorus are added is a material that enables isotropic etching. Further, the source electrode and the drain electrode are preferably formed so as to cover part of the gate electrode. With this structure, stray light (light that is not blocked by a light-blocking film formed above the TFT) can be suppressed from entering the semiconductor film of the TFT, and off current of the TFT can be suppressed. (FIG. 1 (D)). In addition, the second conductive film is provided as a buffer layer, but since it has conductivity, it functions as a capacitor electrode similarly to the third capacitor electrode 23.
[0037]
After the formation of the third insulating film 24, the third insulating film 24 is partially etched to expose the source electrode and the drain electrode 22 of the TFT to form a contact hole. Thereafter, a fourth conductive film 26 is formed. As a material of the fourth conductive film, aluminum (Al), titanium (Ti), tungsten (W), copper (Cu), or the like can be used. Further, a laminated structure in which Al or Cu is formed on the TaN film and a Ti film is further formed may be used.
[0038]
Although not shown, the semiconductor film 15 of the stack capacitor and the third capacitance electrode 23 are electrically connected and have a structure in which a predetermined potential is applied.
[0039]
Through the above steps, a TFT and a stack capacitor can be simultaneously formed. Note that the stack capacitor includes a first capacitor and a second capacitor, and the second capacitor is stacked on the first capacitor. That is, the first capacitance element includes a first capacitance electrode and a second capacitance electrode formed via the first dielectric, and the second capacitance element is formed via the second dielectric. Composed of the second capacitance electrode and the third capacitance electrode. In this embodiment mode, since the first capacitor and the second capacitor are stacked, a sufficient capacitance charge can be secured while reducing the area of the capacitor.
[0040]
In addition, since the second conductive film 20 is formed as a buffer layer between the second insulating film 34 and the third conductive film 21, the second conductive film 20 is subjected to the second impact from the sputtering impact generated when forming the third conductive film 21. Can be protected, and the second insulating film 34 can be made thinner. As a result, sufficient capacitance charge can be maintained without increasing the surface area of the dielectric.
[0041]
In addition, by including the second conductive film, stress generated when the third conductive film 21 is formed can be reduced. For this reason, it is possible to suppress the phenomenon of semiconductor film cracking due to stress, and it is possible to improve the yield.
[0042]
Further, the second conductive film is not directly connected to the semiconductor film of the TFT. Therefore, an n-type semiconductor film and a p-type semiconductor film can be used for the second conductive film. That is, it is not necessary to match the polarity of the second conductive film in accordance with the n-channel TFT and the p-channel TFT, and the buffer layer can be formed with a minimum number of steps.
[0043]
When the present invention is applied to a projection-type liquid crystal display device such as a projector, the aperture ratio of pixels can be increased, and as a result, a display device capable of obtaining high-brightness and high-definition display can be manufactured with high yield. Can be.
[0044]
The present invention having the above configuration will be described in more detail with reference to the following examples.
[0045]
【Example】
[Example 1]
In this embodiment, a method for manufacturing an active matrix substrate will be described with reference to FIGS. Note that in this specification, a substrate in which a driver circuit which is a CMOS circuit and a pixel portion including a pixel TFT and a capacitor are formed over the same substrate is referred to as an active matrix substrate for convenience.
[0046]
First, a first base film (not illustrated) with a thickness of 10 to 150 nm (preferably 50 to 100 nm) including an insulating film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film is formed over the substrate 500. The base film may have a laminated structure of two or more layers, or may not be formed. Next, a conductive film made of a conductive material such as Ta, W, Cr, Mo, or Si that can withstand the processing temperature of this embodiment is formed, the conductive film is formed into a desired shape, and a lower light-shielding film is formed. I do. The lower light-shielding film also has a function as a gate wiring. In this embodiment, an 85 nm-thick crystalline silicon film is formed, and then a 170 nm-thick tungsten silicide (WSi _x After forming (x = 2.0 to 2.8), unnecessary portions are etched to form lower light shielding films 501 and 502. In this embodiment, a two-layer laminated film is used as the lower light-shielding film, but may be formed as a single-layer film.
[0047]
In this embodiment, a synthetic quartz glass substrate is used as the substrate 500. In addition, an insulating film is formed on the surface of a glass substrate such as barium borosilicate glass or aluminoborosilicate glass represented by Corning # 7059 glass or # 1737 glass, a silicon substrate, a metal element substrate, or a stainless steel substrate. You may use what was done. Further, a plastic substrate having heat resistance enough to withstand the processing temperature of this embodiment may be used.
[0048]
Next, a second base film having a thickness of 10 to 650 nm (preferably 50 to 600 nm) made of an insulating film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film is formed over the substrate 500 and the lower light-shielding films 501 and 502. 503 is formed. Although a single-layer structure is used as the second base film 503 in this embodiment, a structure in which two or more insulating films are stacked may be used. In the present embodiment, a plasma CVD method is used for the second ₄ And N ₂ A 100-nm-thick silicon oxynitride film (composition ratio: Si = 32%, O = 27%, N = 24%, H = 17%) is formed using O as a reaction gas.
[0049]
Next, a semiconductor film 504 is formed over the second base film 503. As the semiconductor film 504, a semiconductor film having an amorphous structure is formed with a thickness of 25 to 200 nm (preferably 30 to 100 nm) by a known means (such as a sputtering method, an LPCVD method, or a plasma CVD method). The material of the semiconductor film is not limited, but is preferably formed using silicon or a silicon germanium (SiGe) alloy. (FIG. 3 (A))
[0050]
Next, the semiconductor film is crystallized by a known crystallization treatment (eg, a laser crystallization method, a thermal crystallization method, or a thermal crystallization method using a catalyst such as nickel). In this embodiment, a nickel acetate solution (concentration in terms of weight: 5 ppm) is applied over the entire surface of the film by spin coating, and is exposed to a nitrogen atmosphere at a temperature of 600 ° C. for 12 hours. (FIG. 3 (B))
[0051]
In the case where a laser crystallization method is also applied to the crystallization method of the amorphous semiconductor film, a pulse oscillation type or continuous emission type excimer laser, a YAG laser, a YLF laser, a YVO laser, ₄ Laser or YAlO ₃ A laser or the like can be used. In the case of using these lasers, a method in which a laser beam emitted from a laser oscillator is linearly condensed by an optical system and irradiated to a semiconductor film is preferably used. The crystallization conditions are appropriately selected by the practitioner. When an excimer laser is used, the pulse oscillation frequency is set to 300 Hz, and the laser energy density is set to 100 to 800 mJ / cm. ² (Typically 200 to 700 mJ / cm ² ). When a YAG laser is used, its second harmonic is used, the pulse oscillation frequency is set to 1 to 300 Hz, and the laser energy density is set to 300 to 1000 mJ / cm. ² (Typically 350 to 800 mJ / cm ² ). Next, a laser beam condensed linearly with a width of 100 to 1000 μm, for example 400 μm, is irradiated over the entire surface of the substrate, and the superposition rate (overlap rate) of the linear laser beam is set to 50 to 98%. You may.
[0052]
Subsequently, gettering is performed to remove or reduce a metal element used for promoting crystallization from the semiconductor film to be an active region. For gettering, a method disclosed in Japanese Patent Application Laid-Open No. 10-270363 may be applied. In this embodiment, a silicon oxide film having a thickness of 70 nm is formed as a mask, and etching is performed to obtain silicon oxide films 508a to 508d having desired shapes. Next, impurity regions 510a to 510f are formed by selectively implanting Ar (argon) into the semiconductor film, and heat treatment is performed to remove metal elements from the semiconductor films 511a to 511d to be active regions or to improve semiconductor characteristics. It can be reduced to such an extent that it does not affect. The metal element removed from 511a to 511d is etched and removed together with 510a to 510f in a later step. A TFT having an active region manufactured in this manner has a low off-current value and high field-effect mobility due to good crystallinity, so that good current-voltage characteristics can be achieved. (FIG. 3 (C))
[0053]
Next, the crystalline semiconductor film is etched to form 511a to 511d in a desired shape. The details of this step are not shown. Note that after the semiconductor films 511a to 511d are formed, a small amount of an impurity element (boron or phosphorus) may be doped in order to control the threshold value of the TFT.
[0054]
Next, a first gate insulating film 512 which covers the semiconductor films 511a to 511d is formed. (FIG. 4 (A)). As the first gate insulating film 512, an insulating film with a thickness of 20 to 150 nm is formed by a plasma CVD method or a sputtering method. In this embodiment, a 35-nm-thick silicon oxynitride film (composition ratio: Si = 32%, O = 59%, N = 7%, H = 2%) is formed by a plasma CVD method. Note that the gate insulating film is not limited to the silicon oxynitride film, and another insulating film may be used.
[0055]
In the case where a silicon oxide film is used for the first gate insulating film 512, TEOS (Tetraethyl Orthosilicate) and O ₂ At a reaction pressure of 40 Pa, a substrate temperature of 300 to 400 ° C., and a high frequency (13.56 MHz) power density of 0.5 to 0.8 W / cm. ² And can be formed by discharging. The silicon oxide film thus manufactured can obtain good characteristics as a gate insulating film by subsequent thermal annealing at 400 to 500 ° C.
[0056]
Next, the gate insulating film is partially etched to expose the semiconductor film 511d to be one of the electrodes of the capacitor, and an impurity element is introduced into the semiconductor film 511d to form a first capacitor electrode. (FIG. 4 (B)). At this time, since the other region is covered with the resist 513, no impurity element is introduced. In this embodiment, P (phosphorus) is used as the impurity element, the acceleration voltage is 10 keV, and the dose of the impurity atoms is 5 × 10 5. ¹⁴ / Cm ² As a doping process.
[0057]
Subsequently, a second gate insulating film 515 is formed. The second gate insulating film 515 is formed using a 20 to 150 nm-thick insulating film by a plasma CVD method or a sputtering method. In this embodiment, a silicon oxynitride film (composition ratio: Si = 32%, O = 59%, N = 7%, H = 2%) is formed with a thickness of 50 nm by a plasma CVD method. Note that the second gate insulating film is not limited to the silicon oxynitride film, and another insulating film may be used.
[0058]
In this embodiment, in order to make the insulating film functioning as a dielectric in the capacitor element thinner than the gate insulating film of the TFT, the gate insulating film is formed in two steps. good.
[0059]
Next, after a contact hole connected to the lower light-shielding film is formed, a first conductive film 516a having a thickness of 20 to 100 nm and a second conductive film 516b having a thickness of 100 to 400 nm are stacked. (FIG. 4 (C)). In this embodiment, a first conductive film 516a made of an n-type crystalline silicon film having a thickness of 150 nm and a tungsten silicide (WSi _x ) A second conductive film 516b made of a film is stacked. The n-type crystalline silicon film is formed by a plasma CVD method. In addition, tungsten silicide (WSi _x ) Film is made of tungsten silicide (WSi _x The target is formed by a sputtering method.
[0060]
In this embodiment, the first conductive film 516a is formed of an n-type crystalline silicon film, and the second conductive film 516b is formed of WSi. _x However, the material is not particularly limited, and may be formed of an element selected from Ta, W, Ti, Mo, Al, Cu, Cr, and Nd, or an alloy material or a compound material containing the element as a main component. . Further, an AgPdCu alloy may be used.
[0061]
Next, an etching process for forming a gate electrode and a second capacitor electrode is performed. (FIG. 5A). In this embodiment, as an etching condition, an inductively coupled plasma (ICP) etching method is used, and CF is used as an etching gas. ₄ And Cl ₂ And O ₂ And a gas flow ratio of 25:25:10 (sccm), and a 500 W RF (13.56 MHz) power is applied to the coil-type electrode at a pressure of 1 Pa to generate plasma and perform etching. Then, conductive films 517 to 521 are formed. Note that other known etching methods such as an RIE method and an ECR method can be applied to the step.
[0062]
Next, a second doping process is performed to introduce an n-type impurity element into the semiconductor film. The doping treatment may be performed by an ion doping method or an ion implantation method. The condition of the ion doping method is that the dose of impurity atoms is 1 × 10 ^Thirteen ~ 5 × 10 ¹⁴ / Cm ² And an acceleration voltage of 30 to 80 keV. In this embodiment, the dose of impurity atoms is set to 1.5 × 10 ^Thirteen / Cm ² And the acceleration voltage is set to 70 keV. As an impurity element imparting n-type, an element belonging to Group 15 of the periodic table, typically, phosphorus (P) or arsenic (As) is used. Here, phosphorus (P) is used. In this case, the conductive films 517 to 521 serve as a mask for the impurity element imparting n-type, and the low-concentration impurity regions 523 and 524 are formed in a self-aligned manner. 1 × 10 in the low concentration impurity regions 523 and 524 ¹⁸ ~ 1 × 10 ²⁰ / Cm ³ The impurity element imparting the n-type in the concentration range is introduced. Here, a mask 522 made of a resist is formed in the semiconductor film forming the p-channel TFT, and an impurity element imparting n-type conductivity is not introduced.
[0063]
Next, as shown in FIG. 5B, a third doping process is performed. The condition of the ion doping method is that the dose of impurity atoms is 1 × 10 ^Thirteen ~ 1 × 10 ^Fifteen / Cm ² And an acceleration voltage of 30 to 120 keV. At this time, a mask 525b is formed so as not to introduce an impurity element imparting n-type into the semiconductor film forming the p-channel TFT, and the semiconductor film for forming the n-channel TFT selectively has a high concentration. Masks 525a and 525c are formed to form impurity regions. In this embodiment, the dose of impurity atoms is set to 1 × 10 ^Fifteen / Cm ² And the acceleration voltage was set to 40 keV. Thus, high concentration impurity regions 526 and 529 are formed.
[0064]
Next, after removing the resist mask, the resist masks 532a and 532b are newly patterned, and a fourth doping process is performed as shown in FIG. 5C. By the fourth doping process, an impurity region 533 in which an impurity element imparting p-type conductivity is introduced is formed in a semiconductor film to be an active layer of a p-channel TFT. Using the second conductive film 518 as a mask for the impurity element, an impurity element imparting p-type conductivity is introduced to form an impurity region in a self-aligned manner. In this embodiment, diborane (B ₂ H ₆ ) Is added to the semiconductor film to form an impurity region 533. The condition of the ion doping method is that the dose of impurity atoms is 1 × 10 ^Thirteen ~ 1 × 10 ¹⁴ / Cm ² And an acceleration voltage of 30 to 120 keV. In the fourth doping process, the semiconductor film forming the n-channel TFT is covered with resist masks 532a and 532b.
[0065]
Next, as shown in FIG. 6A, a fifth doping process is performed. The condition of the ion doping method is that the dose of impurity atoms is 1 × 10 ^Thirteen ~ 1 × 10 ^Fifteen / Cm ² And an acceleration voltage of 20 to 120 keV. At this time, masks 534a and 534c are formed so as not to introduce an impurity element imparting p-type into the semiconductor layer forming the n-channel TFT, and selectively formed in the semiconductor layer for forming the p-channel TFT. A mask 534b is formed to form a high-concentration impurity region. In this embodiment, the dose of impurity atoms is set to 1 × 10 ^Fifteen / Cm ² And the acceleration voltage is set to 40 keV. Thus, a high concentration impurity region 535 and a low concentration impurity region 536 are formed.
[0066]
Through the above steps, a high-concentration impurity region and a low-concentration impurity region are formed in each semiconductor film.
[0067]
Next, as shown in FIG. 6B, the masks 534a to 534c made of resist are removed to form a first interlayer insulating film 538. As the first interlayer insulating film 538, an insulating film with a thickness of 100 to 200 nm is formed by a plasma CVD method or a sputtering method. In this embodiment, a 150-nm-thick silicon oxynitride film is formed by a plasma CVD method. Of course, the first interlayer insulating film 538 is not limited to a silicon oxynitride film, and another insulating film such as a silicon nitride film may be used as a single layer or a stacked structure.
[0068]
Next, a third heat treatment is performed to recover the crystallinity of the semiconductor film and to activate the impurity element introduced into each semiconductor film. Here, heat treatment is performed at 950 ° C. for 30 minutes in a nitrogen atmosphere having an oxygen concentration of 1 ppm or less, preferably 0.1 ppm or less using an electric furnace. Note that, other than the heat treatment, a laser annealing method or a rapid thermal annealing method (RTA method) can be applied. In this embodiment, the third heat treatment can be performed at a high temperature because synthetic quartz is used for the substrate. However, when glass or plastic having a low heat-resistant temperature is used for the substrate, the third heat treatment is performed at a temperature lower than the heat-resistant temperature of the substrate. Need to be heat-treated.
[0069]
Further, heat treatment may be performed before forming the first interlayer insulating film 538. However, when the first conductive film and the second conductive film are weak to heat, the first interlayer insulating film is used to protect the first conductive film and the second conductive film as in this embodiment. It is preferable to perform heat treatment after forming an insulating film containing silicon as a main component, for example, a silicon nitride film.
[0070]
Next, hydrogenation can be performed by performing heat treatment (heat treatment at 300 to 550 ° C. for 1 to 12 hours). In this step, dangling bonds in the semiconductor film are terminated by hydrogen contained in the first interlayer insulating film 538. Note that the semiconductor film can be hydrogenated regardless of the presence of the first interlayer insulating film. As another means of hydrogenation, plasma hydrogenation (using hydrogen excited by plasma) or heat treatment at 300 to 450 ° C. for 1 to 12 hours in an atmosphere containing 3 to 100% hydrogen may be performed. good.
[0071]
Next, as shown in FIG. 6C, a third conductive film 600 is formed over the first interlayer insulating film 538. As a material of the third conductive film 600, a conductive film typified by a crystalline silicon film doped with an n-type impurity element such as phosphorus having a thickness of 10 to 100 nm is preferable. When the thickness of the third conductive film is less than 10 nm, the effect of relieving stress generated when forming a tungsten film as a third conductive film to be formed later is low. When the thickness of the third conductive film is 100 nm or more, it is difficult to uniformly control the width of each line when forming a source electrode and a drain electrode and a second capacitor electrode to be formed later. In this embodiment, a 50 nm-thick n-type crystalline silicon film is formed as the third conductive film 600 by an LPCVD method.
[0072]
Next, as shown in FIG. 6C, a contact hole reaching each high-concentration impurity region of the semiconductor film of the TFT is formed. In this embodiment, as an etching condition, CF is used as an etching gas by an RIE etching method. ₄ And Cl ₂ And O ₂ The etching is performed by setting the respective gas flow ratios to 25:25:10 (sccm) and applying 500 W RF (13.56 MHz) power to the electrodes at a pressure of 106.4 Pa.
[0073]
Next, a tungsten film which is the fourth conductive film 607 is formed over the third conductive film 600 and the semiconductor film by a sputtering method. The thickness of the fourth conductive film 607 is preferably 50 to 150 nm. This is because if the thickness of the fourth conductive film is less than 50 nm, the contact hole formed later does not function as an etching stopper, and if the thickness is 150 nm or more, the source electrode, the drain electrode and This is because it is difficult to uniformly control the width of each line because isotropic etching is performed when forming the third capacitance electrode. In this embodiment, a 100-nm-thick tungsten film is formed. Note that the material of the fourth conductive film 607 is not limited to tungsten. For example, a wiring may be formed by forming an aluminum (Al) film or a copper (Cu) film on a tantalum nitride (TaN) film, and further etching a laminated film in which a titanium (Ti) film is formed.
[0074]
Next, as shown in FIG. 7A, the third conductive film and the fourth conductive film are selectively etched to form source and drain electrodes 608 to 613 serving as connection wirings and a third capacitor electrode 614a. To form First, as a first etching condition, SF is added to an etching gas by an RIE etching method. ₆ Using He and He, the respective gas flow ratios are set to 20:20 (sccm), RF power (13.56 MHz) of 300 W is applied to the electrodes, and the fourth conductive film 607 is partially etched. Subsequently, as a second etching condition, SF was added to the etching gas by RIE etching. ₆ Using He and He, the respective gas flow ratios are set to 20:20 (sccm), RF power (13.56 MHz) of 300 W is applied to the electrodes, and the third conductive film is partially etched. Note that the etched third conductive film 614b is provided as a buffer layer; however, since it is conductive, it functions as a capacitor electrode together with the fourth conductive film.
[0075]
Next, as shown in FIG. 7B, a second interlayer insulating film 615 is formed. The second interlayer insulating film 615 is formed with a thickness of 100 to 200 nm by a plasma CVD method or a sputtering method. In this embodiment, a silicon nitride film having a thickness of 120 nm is formed by a plasma CVD method.
[0076]
Next, a third interlayer insulating film 539 made of an inorganic insulating material or an organic insulating material is formed over the second interlayer insulating film 615. In this embodiment, a silicon nitride oxide film having a thickness of 0.45 μm is formed.
[0077]
Next, contact holes reaching the source and drain electrodes 608 to 613 are formed, and wirings 540 to 544 electrically connected to the source and drain electrodes 608 to 613 are formed.
[0078]
These wirings are a titanium (Ti) film having a thickness of 60 nm, a titanium nitride (TiN) film having a thickness of 40 nm, an alloy film having a thickness of 300 (alloy film of Al and Si), and a tungsten (W) film having a thickness of 100 nm. The stacked film is formed by etching.
[0079]
Next, as shown in FIG. 8A, a fourth interlayer insulating film 560 made of an inorganic insulating material or an organic insulating material is formed over the third interlayer insulating film 539 and the wirings 540 to 544. In this embodiment, a silicon nitride oxide film having a thickness of 0.45 μm is formed.
[0080]
Next, a film having a high light-shielding property such as Al, Ti, W, Cr, or a black resin is etched into a desired shape on the fourth interlayer insulating film 560 to form light-shielding films 561 and 562. The light-shielding films 561 and 562 are arranged in a mesh shape so as to shield light other than the openings of the pixels.
[0081]
Next, as shown in FIG. 8B, a fifth interlayer insulating film 563 is formed so as to cover the light shielding films 561 and 562. After that, a contact hole leading to the connection wiring 544 is formed, a conductive film is formed to a thickness of 100 nm, and the resultant is etched into a desired shape to form pixel electrodes 564 and 565. In this embodiment, a pixel electrode is formed using a film made of ITO. A liquid crystal display device to be formed later using this substrate is a transmissive liquid crystal display device. On the other hand, when a film made of a highly reflective element such as silver or aluminum is used for a pixel electrode, a substrate for a reflective liquid crystal display device can be formed.
[0082]
As described above, the pixel portion 556 including the driver circuit 555 including the n-channel TFT 551 and the p-channel TFT 552, the pixel TFT 553, and the capacitor 554 can be formed over the same substrate. Thus, the active matrix substrate is completed.
[0083]
[Example 2]
In this embodiment, a process for manufacturing a reflective liquid crystal display device from the active matrix substrate manufactured in Embodiment 1 will be described below. FIG. 9 is used for the description.
[0084]
First, according to the first embodiment, after obtaining the active matrix substrate in the state of FIG. 8B, an alignment film 567 is formed on at least the pixel electrodes 564 and 565 on the active matrix substrate of FIG. I do. Note that in this embodiment, before forming the alignment film 567, a columnar spacer for maintaining a substrate interval may be formed at a desired position by etching an organic resin film such as an acrylic resin film. In this embodiment, a pixel electrode is formed of an aluminum film in order to form a reflective liquid crystal display device.
[0085]
Next, a counter substrate 569 is prepared. Next, a coloring layer 570 and a planarization film 573 are formed over the counter substrate 569.
[0086]
Next, a counter electrode 576 made of a transparent conductive film is formed at least in the pixel portion over the planarization film 573, an alignment film 577 is formed over the entire surface of the counter substrate, and rubbing treatment is performed.
[0087]
Next, the active matrix substrate on which the pixel portion and the driver circuit are formed and the counter substrate are attached with a sealant 568. A filler is mixed in the sealant 568, and the two substrates can be bonded to each other with the filler and the columnar spacer while maintaining a uniform interval between the two substrates. Thereafter, a liquid crystal material 575 is injected between the two substrates, and completely sealed with a sealing agent (not shown). A known liquid crystal material may be used for the liquid crystal material 575. Thus, the reflection type liquid crystal display device shown in FIG. 9 is completed. Next, if necessary, the active matrix substrate and the counter substrate are cut into desired shapes. Further, a polarizing plate (not shown) is attached only to the opposite substrate 569. Next, an FPC is attached using a known technique (not shown).
[0088]
The liquid crystal display device manufactured as described above is formed by vertically stacking a plurality of capacitive elements, and can increase the aperture ratio while securing sufficient capacitance. For this reason, it is possible to realize high-brightness and high-definition display.
[0089]
Further, since the buffer layer is formed between the conductive film serving as the capacitor electrode and the dielectric, stress generated when the conductive film serving as the capacitor electrode is formed can be reduced. For this reason, it is possible to suppress the phenomenon of semiconductor film cracking due to stress, and it is also possible to manufacture a liquid crystal display device with improved operation characteristics and reliability with a high yield.
[0090]
That is, a liquid crystal display device capable of obtaining high-luminance and high-definition display can be manufactured with high yield. In particular, when the liquid crystal display device of the present invention is used for a projection display device such as a projector, luminance can be increased, and high-luminance and high-definition display can be performed.
[0091]
Further, such a liquid crystal display device can be used as a display portion of various electronic devices.
[0092]
[Example 3]
Example 1 In this example, an example in which a light-emitting device is manufactured using the present invention will be described. In this specification, a light emitting device is a general term for a display panel in which a light emitting element formed on a substrate is sealed between the substrate and a cover material, and a display module in which an IC is mounted on the display panel. is there. Note that the light-emitting element includes a layer containing a compound capable of obtaining luminescence (Electro Luminescence) generated by application of an electric field (hereinafter, referred to as an EL layer), an anode layer, and a cathode layer. In addition, luminescence includes light emission (fluorescence) when returning from the singlet excited state to the ground state and light emission (phosphorescence) when returning from the triplet excited state to the ground state. Including luminescence.
[0093]
Note that in this specification, all layers formed between an anode and a cathode in a light-emitting element are defined as EL layers. The EL layer specifically includes a light emitting layer, a hole injection layer, an electron injection layer, a hole transport layer, an electron transport layer, and the like. Basically, a light-emitting element has a structure in which an anode layer, a light-emitting layer, and a cathode layer are sequentially stacked. In addition to this structure, an anode layer, a hole injection layer, a light-emitting layer, a cathode layer, and an anode layer , A hole injection layer, a light emitting layer, an electron transport layer, and a cathode layer.
[0094]
FIG. 10 is a sectional view of the light emitting device of the present embodiment. A driver circuit provided over the substrate 700 is formed using the driver circuit 555 in FIG. Therefore, for the description of the structure, the description of the n-channel TFT 551 and the p-channel TFT 552 in Embodiment 1 may be referred to. In this embodiment, the TFT has a single gate structure, but may have a double gate structure or a triple gate structure.
[0095]
The wirings 701 to 703 function as a source wiring and a drain wiring of the CMOS circuit. Further, the wirings 704 and 705 function as wirings for electrically connecting the source wiring and the source region of the switching TFT and the drain wiring and the drain region of the switching TFT, respectively. In FIG. 10, a switching TFT 603 provided over a substrate is formed using the n-channel TFT 551 in FIG. 7B. Therefore, for the description of the structure, the description of the n-channel TFT 551 described in Embodiment 1 may be referred to.
[0096]
In this embodiment, the switching TFT 603 has a double gate structure in which two channel formation regions are formed, but has a single gate structure in which one channel formation region is formed or a triple gate structure in which three channel formation regions are formed. Is also good.
[0097]
The capacitor 605 is formed using the capacitor 554 in FIG. Therefore, for the description of the structure, the description of the capacitor 554 in Embodiment 1 may be referred to.
[0098]
The current control TFT 604 is formed using the p-channel TFT 552 in FIG. Therefore, the description of the structure may be referred to the description of the p-channel TFT 552 in Embodiment 1. In this embodiment, a single gate structure is used, but a double gate structure or a triple gate structure may be used.
[0099]
A wiring 706 is a source wiring (corresponding to a power supply line) of the current control TFT, and a wiring 707 electrically connects the pixel electrode 711 and the current control TFT 604 by overlapping the pixel electrode 711 of the current control TFT. Electrode.
[0100]
Note that the pixel electrode 711 is a pixel electrode (anode of a light emitting element) made of a transparent conductive film. As the transparent conductive film, a compound of indium oxide and tin oxide, a compound of indium oxide and zinc oxide, zinc oxide, tin oxide, or indium oxide can be used. Alternatively, a transparent conductive film into which gallium is introduced may be used. The pixel electrode 711 is formed over the flat interlayer insulating film 710 before forming the wiring. Since a light-emitting layer formed later has a very small thickness, light emission failure may occur due to the presence of a step. For this reason, it is desirable to planarize the interlayer insulating film before forming the pixel electrode.
[0101]
After forming the wirings 701 to 708, a bank 712 is formed as shown in FIG. The bank 712 may be formed by etching an inorganic insulating film or an organic resin film having a thickness of 100 to 400 nm.
[0102]
Note that since the bank 712 is an insulating film, attention must be paid to electrostatic breakdown of elements during film formation. In this embodiment, carbon particles and metal element particles are introduced into the insulating film that is the material of the bank 712 to reduce the resistivity and suppress the generation of static electricity. At this time, the resistivity is 1 × 10 ⁶ ~ 1 × 10 ¹² Ωm (preferably 1 × 10 ⁸ ~ 1 × 10 ¹⁰ Ωm) may be adjusted by adjusting the amount of carbon particles or metal element particles introduced.
[0103]
An EL layer 713 is formed over the pixel electrode 711. In this embodiment, an organic light emitting material is used. Although only one pixel is shown in FIG. 10, in this embodiment, EL layers corresponding to R (red), G (green), and B (blue) are separately formed. In this embodiment, the EL layer is formed using a low molecular weight organic light emitting material by a vapor deposition method. Specifically, a 20 nm thick copper phthalocyanine (CuPc) film is provided as a hole injection layer, and a 70 nm thick tris-8-quinolinolato aluminum complex (Alq ₃ ) It has a laminated structure provided with a film. Alq ₃ The emission color can be controlled by introducing a fluorescent dye such as quinacridone, perylene, or DCM1 into the dye.
[0104]
Note that the above example is an example of a light-emitting material that can be used as an EL layer, and there is no need to be limited to this. The light-emitting layer may be formed using an organic material and an inorganic material. In addition, an EL layer (a layer for performing light emission and carrier movement therefor) may be formed by freely combining a light emitting layer, a charge transport layer, or a charge injection layer. For example, in this embodiment, an example in which a low molecular weight organic light emitting material is used as the EL layer is shown, but a medium molecular weight organic light emitting material or a high molecular weight organic light emitting material may be used. Note that in this specification, an organic light-emitting material having no sublimability and having a number of molecules of 20 or less or a chain of molecules having a length of 10 μm or less is defined as a medium-molecular-weight organic light-emitting material. As an example of using a high molecular weight organic light emitting material, a 20 nm polythiophene (PEDOT) film is provided as a hole injection layer by spin coating, and a 100 nm paraphenylene vinylene (PPV) film is provided thereon as a light emitting layer. A stacked structure may be used. When a π-conjugated polymer of PPV is used, the emission wavelength can be selected from red to blue. Further, an inorganic material such as silicon carbide can be used for the charge transport layer and the charge injection layer. Known materials can be used for these organic light emitting materials and inorganic materials.
[0105]
Next, a cathode 714 including a conductive film is provided over the EL layer 713. In this embodiment, an alloy film of aluminum and lithium is used as the conductive film. Of course, a known MgAg film (an alloy film of magnesium and silver) may be used. As the cathode material, a conductive film made of an element belonging to Group 1 or 2 of the periodic table or a conductive film into which these elements are introduced may be used.
[0106]
The light emitting element 715 is completed at the time when the cathode 714 is formed. Note that the light-emitting element 715 here refers to a diode formed by the pixel electrode (anode) 711, the EL layer 713, and the cathode 714.
[0107]
It is effective to provide the passivation film 716 so as to completely cover the light emitting element 715. As the passivation film 716, an insulating film including a carbon film, a silicon nitride film, or a silicon nitride oxide film is used, and the insulating film is used as a single layer or as a stacked layer. At this time, it is preferable to use a film having good coverage as the passivation film, and it is effective to use a carbon film, particularly a DLC (diamond-like carbon) film. Since the DLC film can be formed in a temperature range from room temperature to 100 ° C. or less, it can be easily formed above the light-emitting layer 713 having low heat resistance. In addition, the DLC film has a high blocking effect against oxygen, and can suppress oxidation of the organic light-emitting layer 713. Therefore, the problem that the EL layer 713 is oxidized during the subsequent sealing step can be prevented.
[0108]
Further, a sealing material 717 is provided over the passivation film 716, and a cover material 718 is attached. As the sealing material 717, an ultraviolet curable resin may be used, and it is effective to provide a substance having a moisture absorbing effect or a substance having an antioxidant effect inside. In this embodiment, as the cover material 718, a glass substrate, a synthetic quartz glass substrate, a plastic substrate (including a plastic film), and a carbon film (preferably a diamond-like carbon film) formed on both surfaces is used.
[0109]
Thus, a light emitting device having a structure as shown in FIG. 10 is completed. Note that it is effective to continuously process the steps from the formation of the bank 712 to the formation of the passivation film 716 without opening to the atmosphere using a multi-chamber (or in-line) film forming apparatus. . Further, by further developing, it is also possible to continuously process up to the step of bonding the cover material 718 without releasing it to the atmosphere.
[0110]
Thus, an n-channel TFT 601, a p-channel TFT 602, a switching TFT (n-channel TFT) 603, a current control TFT (p-channel TFT) 604, and a capacitor 605 are formed on the substrate.
[0111]
In this embodiment, only the configuration of the pixel portion and the driving circuit is shown. However, according to the manufacturing process of this embodiment, other logic circuits such as a signal division circuit, a D / A converter, an operational amplifier, and a γ correction circuit are also provided. Can be formed on the same insulator, and further, a memory or a microprocessor can be formed.
[0112]
Further, the light emitting device of this embodiment after performing a sealing (or enclosing) step for protecting the light emitting element will be described with reference to FIG. Note that the reference numerals used in FIG.
[0113]
FIG. 11A is a top view showing a state in which light-emitting elements have been sealed, and FIG. 11B is a cross-sectional view of FIG. 11A taken along the line CC ′. In FIG. 11A, reference numeral 801 indicated by a dotted line denotes a source side driver circuit, 806 denotes a pixel portion, and 807 denotes a gate side driver circuit. Reference numeral 901 denotes a cover material, 902 denotes a first seal material, and 903 denotes a second seal material. A sealing material 907 is provided inside the first seal material 902.
[0114]
Reference numeral 904 denotes a wiring for transmitting a signal input to the source side driving circuit 801 and the gate side driving circuit 807, and receives a video signal and a clock signal from an FPC (flexible print circuit) 905 serving as an external input terminal. Although only the FPC is shown here, a printed wiring board (PWB) may be attached to the FPC. The light-emitting device in this specification includes not only the light-emitting device main body but also a state in which an FPC or a PWB is attached thereto.
[0115]
Next, a cross-sectional structure taken along CC ′ in FIG. 11A is described with reference to FIG. A pixel portion 806 and a gate side driver circuit 807 are formed above the substrate 700. The pixel portion 806 is formed by a plurality of pixels including a current control TFT 604 and a pixel electrode 711 electrically connected to a drain thereof. . The gate driver circuit 807 is formed using a CMOS circuit (see Embodiment 1 and FIG. 10) in which an n-channel TFT 601 and a p-channel TFT 602 are combined.
[0116]
The pixel electrode 711 functions as an anode of the light emitting element. Further, banks 712 are formed at both ends of the pixel electrode 711, and an EL layer 713 and a cathode 714 of a light emitting element are formed on the pixel electrode 711.
[0117]
The cathode 714 also functions as a wiring common to all pixels, and is electrically connected to the FPC 905 via the connection wiring 904. Further, the elements included in the pixel portion 806 and the gate side driver circuit 807 are all covered with the cathode 714 and the passivation film 716.
[0118]
Further, a cover member 901 is attached to the first seal member 902. Note that a spacer made of a resin film may be provided to secure an interval between the cover member 901 and the light emitting element. Next, a sealing material 907 is filled inside the first sealing material 902. Note that an epoxy resin is preferably used for the first sealant 902 and the sealant 907. Further, it is desirable that the first sealant 902 be a material that does not transmit moisture and oxygen as much as possible. Further, a substance having a moisture absorbing effect or a substance having an antioxidant effect may be contained in the sealing material 907.
[0119]
The sealing material 907 provided so as to cover the light-emitting element also functions as an adhesive for bonding the cover material 901. Further, in this embodiment, FRP (Fiberglass-Reinforced Plastics), PVF (polyvinyl fluoride), mylar, polyester, or acrylic can be used as the material of the plastic substrate 901 constituting the cover member 901.
[0120]
After the cover member 901 is bonded using the sealing member 907, a second sealing member 903 is provided so as to cover a side surface (exposed surface) of the sealing member 907. The same material as the first sealant 902 can be used for the second sealant 903.
[0121]
By enclosing the light-emitting element in the sealing material 907 with the above structure, the light-emitting element can be completely shut off from the outside, and a substance that promotes deterioration of the organic light-emitting layer due to oxidation, such as moisture or oxygen, from the outside can be obtained. Intrusion can be prevented. Therefore, a highly reliable light emitting device can be obtained.
[0122]
The wiring in the light-emitting device manufactured as described above has sufficient contact with the semiconductor film, and the operation characteristics and reliability of the light-emitting device can be sufficient. In addition, by using an active matrix substrate having the structure of the present invention for a light-emitting device, a light-emitting device can be manufactured with high yield. Next, such a light emitting device can be used as a display portion of various electronic devices.
[0123]
This embodiment can be freely combined with the first embodiment.
[Example 4]
Various display devices (an active matrix liquid crystal display device and an active matrix light emitting device) can be manufactured by applying the present invention. That is, the present invention can be applied to various electronic devices in which these display devices are incorporated in a display unit.
[0124]
Such electronic devices include video cameras, digital cameras, projectors, head-mounted displays (goggle-type displays), car navigation systems, car stereos, personal computers, personal digital assistants (mobile computers, mobile phones, electronic books, etc.) and the like. No. Examples of these are shown in FIGS. 12, 13 and 14.
[0125]
FIG. 12A illustrates a personal computer, which includes a main body 3001, an image input portion 3002, a display portion 3003, a keyboard 3004, and the like. By applying the present invention, a low-power-consumption personal computer capable of performing high-definition display with high yield can be manufactured.
[0126]
FIG. 12B illustrates a video camera, which includes a main body 3101, a display portion 3102, an audio input portion 3103, operation switches 3104, a battery 3105, an image receiving portion 3106, and the like. By applying the present invention, a video camera capable of displaying images with high yield and high definition can be manufactured.
[0127]
FIG. 12C illustrates a mobile computer (mobile computer), which includes a main body 3201, a camera portion 3202, an image receiving portion 3203, operation switches 3204, a display portion 3205, and the like. By applying the present invention, a low-power-consumption mobile computer (mobile computer) capable of high-yield display with high yield can be manufactured.
[0128]
FIG. 12D illustrates a goggle-type display, which includes a main body 3301, a display portion 3302, an arm portion 3303, and the like. By applying the present invention, a goggle-type display capable of performing high-definition display with high yield can be manufactured.
[0129]
FIG. 12E illustrates a player using a recording medium on which a program is recorded (hereinafter, referred to as a recording medium), and includes a main body 3401, a display portion 3402, a speaker portion 3403, a recording medium 3404, operation switches 3405, and the like. The player can use a DVD (Digital Versatile Disc), a CD, or the like as a recording medium, and can enjoy music, movies, games, and the Internet. By applying the present invention, a player capable of performing high-definition display with high yield can be manufactured.
[0130]
FIG. 12F illustrates a digital camera, which includes a main body 3501, a display portion 3502, an eyepiece portion 3503, operation switches 3504, an image receiving portion (not shown), and the like. By applying the present invention, a digital camera with low power consumption and high yield and high-definition display can be manufactured.
[0131]
FIG. 13A illustrates a front type projector, which includes a projection device 3601, a screen 3602, and the like. By applying the present invention, a high-luminance front-type projector with high yield can be manufactured.
[0132]
FIG. 13B illustrates a rear projector, which includes a main body 3701, a projection device 3702, a mirror 3703, a screen 3704, and the like. By applying the present invention, a high-brightness rear-type projector with a high yield can be manufactured.
[0133]
Note that FIG. 13C is a diagram illustrating an example of the structure of the projection devices 3601 and 3702 in FIGS. 13A and 13B. The projection devices 3601 and 3702 include a light source optical system 3801, mirrors 3802 and 3804 to 3806, a dichroic mirror 3803, a prism 3807, a liquid crystal display device 3808, a phase difference plate 3809, and a projection optical system 3810. The projection optical system 3810 is configured by an optical system including a projection lens. In this embodiment, an example of a three-plate type is shown, but there is no particular limitation, and for example, a single-plate type may be used. Further, the practitioner may appropriately provide an optical system such as an optical lens, a film having a polarizing function, a film for adjusting a phase difference, and an IR film in the optical path indicated by the arrow in FIG. Good.
[0134]
FIG. 13D illustrates an example of the structure of the light source optical system 3801 in FIG. In this embodiment, the light source optical system 3801 includes a reflector 3811, a light source 3812, lens arrays 3813 and 3814, a polarization conversion element 3815, and a condenser lens 3816. Note that the light source optical system shown in FIG. 13D is an example and is not particularly limited. For example, a practitioner may appropriately provide an optical system such as an optical lens, a film having a polarizing function, a film for adjusting a phase difference, and an IR film to the light source optical system.
[0135]
However, in the projector shown in FIG. 13, a case where a transmission type liquid crystal display device is used is shown, and an example of application to a reflection type liquid crystal display device is not shown.
[0136]
FIG. 14A illustrates a mobile phone, which includes a main body 3901, an audio output portion 3902, an audio input portion 3903, a display portion 3904, operation switches 3905, an antenna 3906, and the like. By applying the present invention, a low-power-consumption mobile phone capable of performing high-definition display with high yield can be manufactured.
[0137]
FIG. 14B illustrates a portable book (e-book) including a main body 4001, display portions 4002 and 4003, a storage medium 4004, operation switches 4005, an antenna 4006, and the like. By applying the present invention, a portable book with low power consumption and high yield and high-definition display can be manufactured.
[0138]
FIG. 14C illustrates a display, which includes a main body 4101, a support 4102, a display portion 4103, and the like. The display to which the present invention is applied is particularly advantageous when the screen is enlarged, and is advantageous for a display having a diagonal of 10 inches or more (particularly 30 inches or more).
[0139]
As described above, the applicable range of the present invention is extremely wide, and can be applied to electronic devices in various fields. Further, the electronic apparatus of the present embodiment can be realized by using a configuration composed of any combination of the first to fourth embodiments.
[0140]
【The invention's effect】
By employing the configuration of the present invention, the following significance can be obtained.
[0141]
In a semiconductor device in which a TFT and a plurality of capacitors are stacked vertically with respect to a substrate, a conductive film serving as a buffer layer for relaxing a stress of a conductive film to be formed later is formed over an insulating film serving as a dielectric of the capacitor. Then, a contact hole is formed in the buffer layer and a part of the insulating film. After that, a conductive film is formed and etched to form a source electrode and a drain electrode. With this structure, it is possible to form a semiconductor device having a TFT and a plurality of capacitive elements while suppressing stress cracks in a semiconductor film, a capacitor wiring, and the like.
[0142]
In a semiconductor device having a TFT and a capacitor vertically stacked on a substrate, it is possible to protect the dielectric insulating film from sputtering impact by forming a buffer layer on the dielectric insulating film. Become. For this reason, the capacitor electrode can be formed by the sputtering method, and the selection method of the forming method and the material for forming the capacitor electrode is increased.
[0143]
By forming a source electrode and a drain electrode so as to cover part of a gate electrode of a TFT, the electrodes function as a light-blocking film; thus, stray light can be blocked, and off current of the TFT can be suppressed. .
[0144]
That is, according to the present invention, a semiconductor device capable of holding high capacity can be manufactured with high yield. In particular, in the case where the semiconductor device is a display device, the aperture ratio can be increased. Therefore, a display device which can realize high-brightness and high-definition display while securing a sufficient capacity is manufactured with high yield. can do.
[Brief description of the drawings]
FIG. 1 is a diagram showing an example of the concept of the present invention.
FIG. 2 is a diagram showing a conventional example.
FIG. 3 is a cross-sectional view illustrating a manufacturing process of a pixel TFT and a TFT of a driver circuit.
FIG. 4 is a cross-sectional view illustrating a manufacturing process of a pixel TFT and a TFT of a driver circuit.
FIG. 5 is a cross-sectional view illustrating a manufacturing process of a pixel TFT and a TFT of a driver circuit.
FIG. 6 is a cross-sectional view illustrating a manufacturing process of a pixel TFT and a TFT of a driver circuit.
FIG. 7 is a cross-sectional view illustrating a manufacturing process of a pixel TFT and a TFT of a driver circuit.
FIG. 8 is a cross-sectional view illustrating a manufacturing process of a pixel TFT and a TFT of a driver circuit.
FIG. 9 is a cross-sectional view illustrating a manufacturing process of an active matrix liquid crystal display device.
FIG. 10 is a cross-sectional structural view of a driving circuit and a pixel portion of a light-emitting device.
FIG. 11A is a top view of a light-emitting device.
FIG. 2B is a cross-sectional structural view of a driving circuit and a pixel portion of a light-emitting device.
FIG. 12 illustrates an example of an electronic device.
FIG. 13 illustrates an example of an electronic device.
FIG. 14 illustrates an example of an electronic device.

Claims (12)

A semiconductor device including a thin film transistor, a first capacitor, and a second capacitor formed over an insulating surface,
The first capacitive element and the second capacitive element are vertically stacked on the insulating surface,
The first capacitor has a first capacitor electrode and a second capacitor electrode formed via a first dielectric,
The second capacitance element has the second capacitance electrode and the third capacitance electrode formed via a second dielectric,
The thin film transistor has an active region formed of a semiconductor film, a gate electrode, a connection wiring connected to the active region, and an insulating film formed between the gate electrode and the connection wiring,
A semiconductor device, wherein a buffer layer is formed between the second dielectric and the third capacitor electrode, and between the insulating film and the connection wiring. 2. The semiconductor device according to claim 1, wherein the buffer layer is a film that relieves stress generated when forming the third capacitance electrode and the connection wiring. 3. The semiconductor device according to claim 1, wherein the buffer layer is a crystalline semiconductor film or an amorphous semiconductor film. 4. The semiconductor device according to claim 1, wherein a thickness of the buffer layer is 10 to 100 nm. 5. 5. The semiconductor device according to claim 1, wherein the buffer layer is not in contact with an active region of the thin film transistor. The semiconductor device according to claim 1, wherein the connection wiring is a source electrode and a drain electrode. A liquid crystal display device comprising the semiconductor device according to claim 1. A light-emitting device comprising the semiconductor device according to claim 1. An electronic apparatus comprising the semiconductor device according to claim 1. A first capacitor having a first capacitor electrode and a second capacitor electrode formed on an insulating surface, a second capacitor having the second capacitor electrode and a third capacitor electrode, a thin film transistor, A method for manufacturing a semiconductor device having:
After forming a semiconductor film on an insulating surface, the semiconductor film is etched to form an active region of the thin film transistor and the first capacitor electrode,
Forming a first insulating film and a first conductive film on the active region and the first capacitor electrode in order,
After etching the first conductive film to form the gate electrode and the second capacitance electrode of the thin film transistor,
Forming a third insulating film and a second conductive film, etching the second conductive film, the third insulating film, and the second insulating film to expose a part of an active region of the thin film transistor; After doing
Forming a third conductive film, connecting the third conductive film to an active region of the thin film transistor,
A method for manufacturing a semiconductor device, wherein the second conductive film and the third conductive film are etched to form a connection wiring of the thin film transistor and the third capacitor electrode. 11. The method for manufacturing a semiconductor device according to claim 10, wherein the second conductive film is a crystalline semiconductor film or an amorphous semiconductor film. 12. The method for manufacturing a semiconductor device according to claim 10, wherein the connection wiring is a source electrode and a drain electrode.

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