JP2000269511A - Semiconductor device and its forming method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device having high reliability by arranging TFTs(thin film transistors) of suitable structure according to circuit function. SOLUTION: In a semiconductor device, having a drive circuit part and a pixel part on the same substrate, gate insulating films 115, 116 of a drive TFT are designed to be thinner than the gate insulating film 117 of a pixel element TFT. The gate insulating films 115, 116 of the drive TFT and dielectrics 118 of a holding capacitance are formed simultaneously, so that the dielectrics 118 is very thin and large capacity can be ensured.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a circuit composed of thin film transistors (hereinafter, referred to as TFTs). For example, the present invention relates to a configuration of an electro-optical device represented by a liquid crystal display device or an EL display device, a semiconductor circuit, and an electric appliance (electronic device) using the electro-optical device or the semiconductor circuit of the present invention.

[0002] In this specification, a semiconductor device generally means a device that can function by utilizing semiconductor characteristics, and an electro-optical device, a semiconductor circuit, and an electric appliance are all semiconductor devices.

[0003]

2. Description of the Related Art Since a thin film transistor (hereinafter, referred to as TFT) can be formed on a transparent substrate, an active matrix type liquid crystal display (hereinafter, referred to as AM-LC) is used.
D) has been actively promoted. Since a TFT using a crystalline semiconductor film (typically, a polysilicon film) has high mobility, it is possible to realize a high-definition image display by integrating functional circuits on the same substrate. I have.

Basically, an AM-LCD has a pixel portion for displaying an image (also referred to as a pixel matrix circuit), a gate drive circuit for driving a TFT of each pixel arranged in the pixel portion (also referred to as a gate driver circuit), A source driver circuit (also called a source driver circuit) or a data driver circuit (also called a data driver circuit) that sends an image signal to a TFT
Are formed on the same substrate.

In recent years, a system-on-panel has been proposed in which a signal processing circuit such as a signal dividing circuit or a γ correction circuit is provided on the same substrate in addition to the pixel portion and the driving circuit (also referred to as a driver circuit). ing.

However, since the performance required by the circuit differs between the pixel portion and the driving circuit, it is difficult to satisfy all the circuit specifications with the TFT having the same structure. That is, a driving circuit such as a shift register circuit that emphasizes high-speed operation,
TFTs (hereinafter referred to as “TFTs”) that constitute a pixel portion that emphasizes high breakdown voltage characteristics
At present, a TFT structure that simultaneously satisfies the requirement of “pixel TFT” has not been established.

Accordingly, the applicant of the present invention has proposed a TF constituting a drive circuit.
T (hereinafter referred to as driving TFT or driver TFT)
An application has been filed for making the thickness of the gate insulating film different between the pixel TFT and the pixel TFT (JP-A-10-056184, US Patent Application No. 08 / 862,895). Specifically, the gate insulating film of the driving TFT is made thinner than the gate insulating film of the pixel TFT.

[0008]

In the present invention, the pixel portion is further improved based on the configuration described in the above publication. Specifically, an object of the present invention is to provide a structure for forming a storage capacitor capable of securing a large capacity in a small area.

It is another object of the present invention to provide a highly reliable electro-optical device by forming each circuit of an electro-optical device represented by an AM-LCD with a TFT having an appropriate structure according to a function. In addition, it is an object to increase the reliability of a semiconductor device (electric appliance) having such an electro-optical device as a display portion.

[0010]

According to the invention disclosed in this specification, in a semiconductor device having a driving circuit portion and a pixel portion on the same substrate, a driving TFT of the driving circuit portion and a pixel of the pixel portion are provided. The thickness of the gate insulating film is different from that of the TFT, and the thickness of the dielectric of the storage capacitor formed in the pixel portion is the same as the thickness of the gate insulating film of the driving TFT.

Specifically, in a semiconductor device having a driving circuit portion and a pixel portion on the same substrate, the thickness of the gate insulating film of the driving TFT of the driving circuit portion is equal to the gate insulating film of the pixel TFT of the pixel portion. The thickness of the dielectric of the storage capacitor formed in the pixel portion is smaller than the thickness of the driving TFT.
The thickness of the gate insulating film is the same.

In another aspect of the invention, a first step of forming an amorphous semiconductor film on a substrate and the amorphous semiconductor film is selected from nickel, cobalt, palladium, germanium, platinum, iron and copper. A second step of forming a crystalline semiconductor film by solid-phase growth using the obtained element, a third step of patterning the crystalline semiconductor film to form an active layer, and forming an insulating film on the surface of the active layer. A fourth step of forming;
After the fourth step, a fifth step of oxidizing the active layer by a thermal oxidation treatment, and adding an element belonging to Group 15 of the periodic table or an element belonging to Group 13 of the periodic table to the active layer after the fifth step. A sixth step to be performed, and after the sixth step, 750 to 1
And performing a heat treatment at a temperature of 150 ° C.

Another aspect of the invention is a method of manufacturing a semiconductor device including a driving TFT and a pixel TFT on the same substrate, wherein a first step of forming an amorphous semiconductor film on the substrate, A second step of forming a crystalline semiconductor film by solid phase growth using an element selected from nickel, cobalt, palladium, germanium, platinum, iron or copper; and patterning the crystalline semiconductor film. Forming a first insulating film on the active layer of the driving TFT and the active layer of the pixel TFT; and A fifth step of etching the first insulating film to expose the entire active layer of the driving TFT and a part of the active layer of the pixel TFT, and a step of thermally oxidizing the active layer exposed in the fifth step. surface A sixth step of forming a second insulating film, a seventh step of forming a wiring on the first insulating film and the second insulating film, and belonging to Group 15 of the periodic table in the active layer using the wiring as a mask An eighth step of adding an element or an element belonging to Group 13 of the periodic table; and after the eighth step, 75
A ninth step of performing a heat treatment at a temperature of 0 to 1150 ° C.

In another aspect of the invention, a first step of forming an amorphous semiconductor film on a substrate and the amorphous semiconductor film is selected from nickel, cobalt, palladium, germanium, platinum, iron and copper. After the second step of forming a crystalline semiconductor film by solid phase growth using the obtained element, the third step of adding an element belonging to Group 15 of the periodic table to the crystalline semiconductor film, 500 to 6 for crystalline semiconductor film
A fourth step of performing a heat treatment at 50 ° C., a fifth step of patterning the crystalline semiconductor film having undergone the fourth step to form an active layer, and a sixth step of forming an insulating film on the surface of the active layer. And after the sixth step, a seventh step of oxidizing the active layer by a thermal oxidation treatment, and an element belonging to Group 15 of the periodic table or an element belonging to Group 13 of the periodic table is added to the active layer after the seventh step. An eighth step of adding, and after the eighth step, 75
A ninth step of performing a heat treatment at a temperature of 0 to 1150 ° C.

According to another aspect of the invention, there is provided a method of manufacturing a semiconductor device including a driving TFT and a pixel TFT on the same substrate, wherein a first step of forming an amorphous semiconductor film on the substrate, A second step of forming the crystalline semiconductor film by solid phase growth using an element selected from nickel, cobalt, palladium, germanium, platinum, iron or copper; and forming a periodic table on the crystalline semiconductor film. A third step of adding an element belonging to Group 15 of the following, a fourth step of performing a heat treatment at 500 to 650 ° C. on the crystalline semiconductor film after the third step, and removing the crystalline semiconductor film having passed through the fourth step. A fifth step of forming an active layer of the driving TFT and an active layer of the pixel TFT by patterning, and a sixth step of forming a first insulating film on the active layer of the driving TFT and the active layer of the pixel TFT And the first Etched Enmaku, the driving T
A seventh step of exposing the entirety of the active layer of the FT and a part of the active layer of the pixel TFT; and an eighth step of forming a second insulating film on the surface of the active layer exposed in the seventh step by a thermal oxidation treatment. A ninth step of forming a wiring on the first insulating film and the second insulating film; and an element belonging to Group 15 of the periodic table or belonging to Group 13 of the periodic table in the active layer using the wiring as a mask. A tenth step of adding an element, and an eleventh step of performing a heat treatment at a temperature of 750 to 1150 ° C. after the tenth step.
And a step.

Another aspect of the invention is a method for manufacturing a semiconductor device having a driving circuit portion and a pixel portion on the same substrate, wherein nickel, cobalt, palladium, germanium, platinum, iron or A first step of forming a semiconductor film using an element selected from copper, a second step of forming a gate insulating film on the semiconductor film, and removing a part of the gate insulating film to form the active layer A third step of exposing a part of the active layer, a fourth step of forming an oxide film on a part of the active layer exposed in the third step by thermal oxidation, and a step of forming an oxide film on the gate insulating film and the oxide film. Fifth forming gate wiring
A step of forming a sidewall on a side surface of the gate wiring, and a seventh step of adding an element belonging to Group 15 of the periodic table to the active layer using the gate wiring and the sidewall as a mask. An eighth step of removing the sidewalls, a ninth step of adding an element belonging to Group 15 of the periodic table to the active layer using the gate wiring as a mask, and forming a resist mask on a region that will later become an NTFT. Forming and adding a heat treatment at the same temperature as the fourth step or a temperature higher than the tenth step of adding an element belonging to Group 13 of the periodic table; An eleventh step of moving to a region to which an element belonging to Group 15 of the periodic table is added.

Another aspect of the present invention is a method for manufacturing a semiconductor device having a driving circuit portion and a pixel portion on the same substrate, wherein nickel, cobalt, palladium, germanium, platinum, iron or A first step of forming a semiconductor film using an element selected from copper, and a second step of selectively adding an element belonging to Group 15 of the periodic table to the semiconductor film.
Process and heat treatment to remove the catalyst element from
A third step of moving to a region to which an element belonging to group III is added, a fourth step of forming a gate insulating film on the semiconductor film, and removing a part of the gate insulating film to form a part of the active layer. A fifth step of exposing a portion, a sixth step of forming an oxide film on a part of the active layer exposed in the fifth step by a thermal oxidation treatment, and a gate wiring on the gate insulating film and the oxide film. A step of forming a sidewall, an eighth step of forming a sidewall on a side surface of the gate wiring, and adding an element belonging to Group 15 of the periodic table to the active layer using the gate wiring and the sidewall as a mask. A ninth step of removing the side wall, an eleventh step of adding an element belonging to Group 15 of the periodic table to the active layer using the gate wiring as a mask,
A twelfth step of forming a resist mask over a region to be a TFT and adding an element belonging to Group 13;

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to FIG. FIG. 1 is a cross-sectional view of an AM-LCD in which a drive circuit portion and a pixel portion are integrally formed on the same substrate. Here, a CMOS circuit is shown as a basic circuit constituting the drive circuit portion, and a TFT having a double gate structure is shown as a pixel TFT. Of course, not only the double gate structure but also a triple gate structure or a single gate structure may be used.

In FIG. 1, reference numeral 101 denotes a substrate having heat resistance, which may be a quartz substrate, a silicon substrate, a ceramic substrate, or a metal substrate (typically, a stainless steel substrate). Whichever substrate is used, a base film (preferably, an insulating film containing silicon as a main component) may be provided as necessary.

Reference numeral 102 denotes a silicon oxide film provided as a base film, on which an active layer of a driving TFT, an active layer of a pixel TFT, and a semiconductor film to be a lower electrode of a storage capacitor are formed. In this specification, “electrode” means “wiring”
And a portion where an electrical connection with another wiring is made or a portion that intersects with a semiconductor film. Therefore, for convenience of explanation, “wiring” and “electrode” are used properly, but “wiring”
"Electrode" is always included in the wording.

In FIG. 1, the active layer of the driving TFT is composed of N
Source region 103, drain region 104, LDD (lightly doped drain) region 105, and channel forming region 10 of a channel type TFT (hereinafter referred to as NTFT).
6, and a source region 107, a drain region 108, and a channel formation region 109 of a P-channel TFT (hereinafter referred to as PTFT).

The active layer of a pixel TFT (here, NTFT is used) is formed of a source region 110, a drain region 111, LDD regions 112a and 112b, and channel forming regions 113a and 113b. Further, a semiconductor film extended from the drain region 111 is used as the lower electrode 114 of the storage capacitor.

A gate insulating film is formed so as to cover the active layer and the lower electrode of the storage capacitor. In the present invention, the gate insulating films 115 (NTFT side) and 116 of the driving TFT are used.
(PTFT side) is formed thinner than the gate insulating film 117 of the pixel TFT. Typically, the gate insulating film 11
The thickness of 5, 116 is 5 to 50 nm (preferably 10 to 30 nm).
nm), and the thickness of the gate insulating film 117 is 50 to 200 nm.
(Preferably 100 to 150 nm).

The gate insulating film of the driving TFT does not need to have one kind of film thickness. That is, a driving TFT having an insulating film having a different thickness may exist in the driving circuit. In that case, at least three or more types of TFTs having gate insulating films of different thicknesses exist on the same substrate. Further, the thickness of the gate insulating film of the driving TFT and the thickness of the dielectric of the storage capacitor are different, and they are different from each other in the pixel TFT.
May differ from the thickness of the gate insulating film.
For example, drive TFTs (particularly circuits that require high-speed operation)
May be 5 to 10 nm, the pixel TFT may have a gate insulating film of 100 to 150 nm, and the dielectric of the storage capacitor may be 30 to 50 nm.

Another feature is that the dielectric 118 of the storage capacitor is formed of an insulating film formed simultaneously with the gate insulating films 115 and 116 of the driving TFT. That is,
The gate insulating film of the driving TFT and the dielectric of the storage capacitor are formed of the same insulating film having the same thickness.

By reducing the thickness of the dielectric of the storage capacitor, capacity can be increased without increasing the area for forming the capacitor. The configuration of the storage capacitor is not described in the above-mentioned Japanese Patent Application Laid-Open No. 10-056184. Also, T
The advantage is obtained that the number of steps for manufacturing the FT is not increased.

Next, the gate insulating films 115, 116, 11
7, gate wirings 119 and 120 of the driving TFT,
The gate wiring 121 of the pixel TFT is formed. At the same time, an upper electrode 122 of the storage capacitor is formed on the dielectric 118 of the storage capacitor. As a material for forming the gate wirings 119 to 121 and the upper electrode 122 of the storage capacitor, 80
A conductive film having heat resistance enough to withstand a temperature of 0 to 1150 ° C (preferably 900 to 1100 ° C) is used.

Typically, a conductive silicon film (for example, a phosphorus-doped silicon film, a boron-doped silicon film, etc.)
Or a metal film (for example, a tungsten film, a tantalum film, a molybdenum film, a titanium film, or the like), a silicide film obtained by silicidizing the metal film, or a nitrided film (a tantalum nitride film, a tungsten nitride film, a titanium nitride film, or the like). But it is good. Further, these may be freely combined and laminated.

When the metal film is used, it is preferable that the metal film has a laminated structure with a silicon film in order to prevent oxidation of the metal film. In terms of preventing oxidation, a structure in which a metal film is covered with a silicon nitride film is effective. In FIG. 1, a silicon nitride film 123 is provided to prevent oxidation of the gate wiring.

Next, reference numeral 124 denotes a first interlayer insulating film, which is formed of an insulating film containing silicon (single layer or multilayer). As the insulating film containing silicon, a silicon oxide film, a silicon nitride film, a silicon oxynitride film (having a higher nitrogen content than oxygen), and a silicon nitride oxide film (having a higher oxygen content than nitrogen) ) Can be used.

A contact hole is provided in the first interlayer insulating film 124, and the source wiring 12 of the driving TFT is formed.
5, 126, a drain wiring 127, and a source wiring 128 and a drain wiring 129 of the pixel TFT are formed.
A passivation film 130 and a second interlayer insulating film 131 are formed thereon, and a black mask (light shielding film) 132 is further formed thereon. Further, a third interlayer insulating film 133 is formed on the black mask 132, and a pixel electrode 134 is formed after providing a contact hole.

The second interlayer insulating film 131 and the third interlayer insulating film 1
As 33, a resin film having a small relative dielectric constant is preferable. As the resin film, a polyimide film, an acrylic film, a polyamide film, a BCB (benzocyclobutene) film, or the like can be used.

The pixel electrode 134 is a transmission type A
To manufacture an M-LCD, a transparent conductive film typified by an ITO film may be used, and to manufacture a reflective AM-LCD, a metal film having a high reflectivity typified by an aluminum film may be used.

Although the pixel electrode 134 is electrically connected to the drain region 107 of the pixel TFT via the drain electrode 129 in FIG. 1, the pixel electrode 134 and the drain region 107 may be directly connected. It is good also as a structure.

The AM-LCD having the above structure is
The point that the gate insulating film of the driving TFT is thinner than the gate insulating film of the pixel TFT, and that the dielectric of the storage capacitor and the gate insulating film of the driving TFT are formed of the same thickness of insulating film formed simultaneously. There are features. By doing so, it is possible to arrange an optimal TFT according to the performance of the circuit, and it is possible to realize a storage capacitor that can secure a large capacity in a small area.

The present invention having the above configuration will be described in more detail with reference to the following embodiments.

[0037]

[Embodiment 1] In this embodiment, a manufacturing process for realizing the structure of FIG. 1 described in "Embodiment of the Invention" will be described. 2 and 3 are used for the description.

First, a quartz substrate 201 is prepared as a substrate, and a 20-nm-thick silicon oxide film 202 and an amorphous silicon film (not shown) are continuously formed thereon without exposing to the atmosphere. This prevents impurities such as boron contained in the air from adsorbing to the lower surface of the amorphous silicon film.

In this embodiment, an amorphous silicon (amorphous silicon) film is used, but another semiconductor film may be used. A microcrystalline silicon (microcrystalline silicon) film or an amorphous silicon germanium film may be used.

Next, the amorphous silicon film is crystallized. In this embodiment, a technique described in Japanese Patent Application Laid-Open No. 9-313260 is used as a crystallization means. The technique described in the publication discloses the crystallization of an amorphous silicon film by solid phase growth using an element selected from nickel, cobalt, palladium, germanium, platinum, iron or copper as a catalyst element for promoting crystallization. I do.

In this embodiment, nickel is selected as a catalyst element, and a layer containing nickel is formed on the amorphous silicon film.
A heat treatment at 550 ° C. for 14 hours is performed for crystallization. Then, the formed crystalline silicon (polysilicon) film is patterned to form an active layer (semiconductor film) 203 of the driving TFT,
An active layer (semiconductor film) 204 of the pixel TFT is formed.

Before and after forming the active layers of the driving TFT and the pixel TFT, an impurity element (phosphorus or boron) for controlling the threshold voltage of the TFT may be added to the crystalline silicon film. . This step is performed by NTFT or P
It may be performed only for the TFT or both.

Next, a gate insulating film (first insulating film) 205 is formed by a plasma CVD method or a sputtering method.
The gate insulating film 205 is an insulating film that functions as a gate insulating film of the pixel TFT, and has a thickness of 50 to 2
00 nm. In this embodiment, a silicon oxide film having a thickness of 100 nm is used.

Further, a laminated structure in which a silicon nitride film is provided on a silicon oxide film as well as a silicon oxide film may be used, or a silicon oxynitride film in which nitrogen is added to a silicon oxide film may be used. .

After the formation of the gate insulating film 205, a resist mask (not shown) is provided and the gate insulating film 205 is selectively removed. At this time, the gate insulating film 205 is left over the pixel TFT, and the region above the region serving as the driving TFT and the storage capacitor is removed. Thus, the state shown in FIG. 2A is obtained.

Next, at 800-1150 ° C. (preferably 9 ° C.)
A heat treatment step of 15 minutes to 8 hours (preferably 30 minutes to 2 hours) at a temperature of (00 to 1100 ° C.) is performed in an oxidizing atmosphere (thermal oxidation step). In this embodiment, 95
A thermal oxidation treatment is performed at 0 ° C. for 30 minutes.

The oxidizing atmosphere may be a dry oxygen atmosphere or a wet oxygen atmosphere, but a dry oxygen atmosphere is suitable for reducing crystal defects in a semiconductor film.
Further, an atmosphere containing a halogen element in an oxygen atmosphere may be used. This thermal oxidation step in an atmosphere containing a halogen element is effective because an effect of removing nickel can be expected.

By performing the thermal oxidation process in this way, a silicon oxide film (also referred to as an oxide film) 206 having a thickness of 5 to 50 nm (preferably 10 to 30 nm) is formed on the surface of the semiconductor film exposed in the region where the driving TFT and the storage capacitor are formed. , 207 are formed. Finally, the silicon oxide film 206 functions as a gate insulating film (second insulating film) of the driving TFT, and the silicon oxide film 20
Reference numeral 7 functions as a dielectric of the storage capacitor.

The oxidation reaction also proceeds at the interface between the gate insulating film 205 made of a silicon oxide film remaining in the pixel TFT and the semiconductor film 204 therebelow. Therefore, the thickness of the gate insulating film 205 of the pixel TFT finally becomes 50 to 2
00 nm (preferably 100 to 150 nm).

After the thermal oxidation process is completed, the gate wirings 209 (NTFT side) of the driving TFT and 210
(PTFT side), the gate wiring 211 of the pixel TFT, and the upper wiring (upper electrode) 212 of the storage capacitor are formed. Although the gate wiring 211 has two gate wirings because the pixel TFT has a double gate structure, it is actually the same wiring.

In this embodiment, the gate wirings 209 to 2
As the upper wiring 11 and the storage capacitor 212, a laminated film of a silicon film (which has conductivity) / a tungsten nitride film / a tungsten film (or a silicon film / a tungsten silicide film from a lower layer) is used. Of course, it is needless to say that other conductive films described in “Embodiments of the invention” can be used. In this embodiment,
The thickness of each gate wiring is 250 nm.

In this embodiment, the lowermost silicon film is formed by using a low pressure thermal CVD method. Since the gate insulating film of the driving circuit is as thin as 5 to 50 nm, the sputtering method or plasma CV
When the method D is used, a semiconductor film (active layer) may be used depending on conditions.
May cause damage to Therefore, a thermal CVD method capable of forming a film by a chemical vapor reaction is preferable.

Next, a silicon nitride film 213 having a thickness of 25 nm is formed to cover the gate wirings 209 to 211 and the upper wiring 212 of the storage capacitor. The silicon nitride film 213 prevents oxidation of the gate wirings 209 to 211 and the upper wiring 212 of the storage capacitor, and at the same time functions as an etching stopper when removing a sidewall made of a silicon film.

At this time, it is effective to perform a plasma treatment using a gas containing hydrogen (ammonia gas in this embodiment) as a pretreatment for forming the silicon nitride film 213. Hydrogen activated (excited) by the plasma by this pretreatment is confined in the active layer (semiconductor film), so that hydrogen termination is effectively performed.

Further, when nitrous oxide gas is added in addition to the gas containing hydrogen, the surface of the object to be treated is washed by the generated moisture, and it is possible to effectively prevent the contamination by boron and the like contained in the air. it can.

Thus, the state shown in FIG. 2B is obtained. next,
An amorphous silicon film (not shown) is formed, and anisotropic etching is performed with a chlorine-based gas to form sidewalls 214 to 21.
8 is formed. After the formation of the sidewalls 214 to 218, a step of adding an element belonging to Group 15 of the periodic table (phosphorus in this embodiment) to the active layers 203 and 204 is performed.

At this time, the gate wirings 209 to 211 are held.
Capacitor upper electrode 212 and sidewalls 214-2
18 serves as a mask, and the impurity regions 219 to
223 are formed. Added to impurity regions 219 to 223
The concentration of phosphorus used is 5 × 10 ¹⁹~ 1 × 10^{twenty one}atoms / cm^Three
Adjust so that In this specification, the phosphorus concentration at this time is
The degree is represented by (n +). (Fig. 2 (C))

This step may be performed separately on a region where the gate insulating film is a thin film transistor TFT and a region where the storage capacitor is to be formed, and separately on a region where the gate insulating film is a thick film pixel TFT and may be performed simultaneously. May be. In the step of adding phosphorus, an ion implantation method for performing mass separation may be used, or a plasma doping method for not performing mass separation may be used. Further, the condition of the acceleration voltage and the dose amount may be set by the practitioner to the optimal values.

When the state shown in FIG. 2C is obtained, the side walls 214 to 218 are removed, and the phosphorus adding step is performed again. In this step, the doping is performed at a lower dose than in the previous step of adding phosphorus. Thus, the sidewall 2
A low concentration impurity region is formed in a region where phosphorus is not added by using 14 to 218 as a mask. The concentration of phosphorus added to this low concentration impurity region is 5 × 10 ^{17 to} 5 × 1.
Adjust so as to be 0 ¹⁸ atoms / cm ³ . In this specification, the phosphorus concentration at this time is represented by (n-). (FIG. 2 (D))

Of course, this step may be performed separately for a region where the gate insulating film is thin and which is a driving TFT and a storage capacitor, and a region where the gate insulating film is thick and a pixel TFT where the gate insulating film is thick. You may go. In the step of adding phosphorus, an ion implantation method for performing mass separation may be used, or a plasma doping method for not performing mass separation may be used. Further, the condition of the acceleration voltage and the dose amount may be set by the practitioner to the optimal values.

However, since this low-concentration impurity region functions as an LDD region, it is necessary to carefully control the phosphorus concentration. Therefore, in this embodiment, the concentration distribution (concentration profile) of the added phosphorus is set as shown in FIG. 15 by using the plasma doping method.

In FIG. 15, the gate insulating film 83 on the driving circuit side and the gate insulating film 84 on the pixel portion are different in film thickness. Therefore, the concentration distribution of the added phosphorus in the depth direction is different.

In this embodiment, the phosphorus addition conditions (acceleration voltage, etc.) are adjusted so that the drive circuit has the density distribution indicated by 85 and the pixel portion has the density distribution indicated by 86. In this case, although the concentration distribution in the depth direction is different, the resulting low concentration impurity regions 87 and 88 have substantially the same phosphorus concentration.

The step shown in FIG. 15 can be used in all the impurity adding steps described in this specification.

In this process, a CMOS circuit N is formed.
A source region 224, an LDD region 225, and a channel forming region 226 of the TFT are defined. Further, the source region 227, the drain region 228, and the LDD region 229 of the pixel TFT are provided.
a, 229b and channel formation regions 230a, 230b are defined. Further, a lower electrode 231 of the storage capacitor is defined.
In the case of this embodiment, the lower electrode 231 of the storage capacitor is formed of a semiconductor region having the same composition as the channel formation region 230a or 230b, and is intrinsic or substantially intrinsic.

Also, a low concentration impurity region 232 is formed in a region to be a PTFT of a CMOS circuit, similarly to the NTFT.

Next, a region other than the region to be the PTFT of the CMOS circuit is hidden by resist masks 233 and 234, and an element belonging to Group 13 (boron in this embodiment) is added.
In this step, doping is performed at such a dose as to form an impurity region having a higher concentration than phosphorus already added. Specifically, the adjustment is performed so that boron is added at a concentration of 1 × 10 ^{20 to} 3 × 10 ²¹ atoms / cm ³ . In this specification, the boron concentration at this time is represented by (p ++). As a result, the impurity regions exhibiting N-type conductivity formed in the region that becomes the PTFT are all inverted in conductivity due to boron and become impurity regions exhibiting P-type conductivity. (FIG. 3 (A))

Of course, also in this step, an ion implantation method for performing mass separation may be used, or a plasma doping method for not performing mass separation may be used. Further, the condition of the acceleration voltage and the dose amount may be set by the practitioner to the optimal values.

By this step, P forming a CMOS circuit
A source region 235, a drain region 236, and a channel formation region 237 of the TFT are defined. Also, the drain region 238 of the NTFT of the CMOS circuit is defined.

After all the impurity regions have been formed, the resist masks 233 and 234 are removed. Then, a heat treatment step is performed in a temperature range of 750 to 1150 ° C. for 20 minutes to 12 hours. In this embodiment, heat treatment at 950 ° C. for 2 hours is performed in an inert atmosphere. (FIG. 3
(B))

In this step, phosphorus or boron added to each impurity region is activated, and at the same time, nickel (catalytic element used at the time of crystallization) remaining in the channel formation region is converted into a source region and a nickel by the gettering action of phosphorus. It also serves as a step of moving (gettering) to the drain region.

The reason why the processing temperature is high is that unless a temperature of about ± 50 ° C. is applied from the highest temperature in the heat history of the semiconductor film from the crystallization step to the gettering step, phosphorus gettering This is because the action does not work effectively. In the case of this embodiment, 950 is used for forming the gate insulating film.
Since the heat history passes through the heat history of 900C, a heat treatment at 900 to 1000C is effective.

In this step, nickel moves in the direction of the arrow in FIG. 3B and is gettered (captured) by phosphorus contained in the source region or the drain region. Accordingly, the concentration of nickel contained in channel formation regions 238 to 241 and lower electrode 242 of the storage capacitor is 2 × 10 ¹⁷
atoms / cm ³ or less (preferably 1 × 10 ¹⁶ atoms / cm ³ or less)
Is reduced to Therefore, the operation of the TFT is not affected at all.

[0074] On the contrary, the source region 243-245 and drain regions 246-248 concentrated ^{nickel, 1 × 10 19 atoms / cm} 3 or more (typically 3 × 10 ¹⁹
１1 × 10 ²¹ atoms / cm ³ ).

When the state shown in FIG. 3B is obtained,
A first interlayer insulating film 249 is formed. In this embodiment, a silicon oxide film having a thickness of 1 μm formed by a plasma CVD method is used. Then, after forming the contact holes, source wirings 250 to 252 and drain wirings 253 and 254 are formed. These wirings are formed of a stacked film in which a conductive film containing aluminum as a main component is sandwiched between titanium films.

At this time, the drain wiring 253 is used as a wiring common to NTFT and PTFT forming a CMOS circuit. In addition, since the source region and the drain region contain nickel at a high concentration as described above, good ohmic contact with the source wiring and the drain wiring can be realized.

After that, a passivation film 255 is formed. As the passivation film 255, a silicon nitride film, a silicon oxynitride film, a silicon nitride oxide film, or a stacked film of these insulating films and a silicon oxide film can be used.
In this embodiment, a silicon nitride film having a thickness of 300 nm is used as a passivation film.

In this embodiment, as a pretreatment for forming a silicon nitride film, a plasma treatment using an ammonia gas is performed, and a passivation film 255 is formed as it is.
Since hydrogen activated (excited) by plasma is confined by the passivation film 255 by this pretreatment, hydrogen termination of the active layer (semiconductor film) of the TFT can be promoted.

Further, when nitrous oxide gas is added in addition to the gas containing hydrogen, the surface of the object to be treated is washed by the generated moisture, and it is possible to effectively prevent the contamination by boron and the like contained in the air. it can.

After forming the passivation film 255,
As the second interlayer insulating film 256, a 0.5 μm-thick silicon oxide film, a 0.2 μm-thick silicon nitride oxide film, and a 0.5 μm-thick acrylic film are formed. Then, a titanium film is deposited on the
A black mask 257 is formed by forming a pattern having a thickness of 0 nm and performing patterning.

Next, as the third interlayer insulating film 258, 1
A contact hole is formed by forming an acrylic film having a thickness of μm, and a pixel electrode 259 made of an ITO film is formed. Thus, an AM-LCD having a structure as shown in FIG. 3C is completed.

In the AM-LCD of the present invention, the thickness of the gate insulating film differs between the driving circuit (or the signal processing circuit) and the pixel portion formed on the same substrate. Typically, a driving TFT used for a driving circuit has a thinner gate insulating film than a pixel TFT used for a pixel portion.

Further, the gate insulating film of the driving TFT and the dielectric of the storage capacitor provided in the pixel portion are simultaneously formed,
Another characteristic is that they have the same thickness.

As described above, the present invention is characterized in that the step of forming a thin gate insulating film of a driving TFT also serves as the step of thinning the dielectric of a storage capacitor. With such a configuration, it is possible to increase the capacity of the storage capacitor without increasing the area.

According to the fabrication process of this embodiment, the final active layer (semiconductor film) of the TFT is formed of a crystalline silicon film having a unique crystal structure having continuity in the crystal lattice. The features will be described below.

The active layer formed according to the above manufacturing steps
Microscopically, it has a crystal structure in which a plurality of needle-shaped or rod-shaped crystals (hereinafter, abbreviated as rod-shaped crystals) are gathered and arranged.
This was easily confirmed by TEM (transmission electron microscopy) observation.

Further, electron diffraction and X-ray (X-ray)
By using diffraction, it was confirmed that the surface of the active layer (portion where a channel is formed) had a {110} plane as a main orientation plane although the crystal axis contained some deviation. That is, as a result of the applicant's detailed observation of an electron beam diffraction photograph having a spot diameter of about 1.5 μm, it was confirmed that diffraction spots corresponding to the {110} plane appeared clearly, and each spot was distributed on a concentric circle. Was confirmed to have.

Further, the applicant of the present invention has observed by HR-TEM (high resolution transmission electron microscopy) the grain boundaries formed by the contact of individual rod-shaped crystals, and found that there is continuity in the crystal lattice at the grain boundaries. It was confirmed. This was easily confirmed from the fact that the observed lattice fringes were continuously connected at the crystal grain boundaries.

Note that the continuity of the crystal lattice at the crystal grain boundaries is caused by the fact that the crystal grain boundaries are grain boundaries called “planar grain boundaries”. The definition of the planar grain boundary in this specification is `` Characterization of High-Efficiency Cast-Si
Solar Cell Wafers by MBICMeasurement; Ryuichi Shi
mokawa and Yutaka Hayashi, Japanese Journal of Appl
ied Physics vol.27, No.5, pp.751-758, 1988 ".

According to the above paper, the planar grain boundaries include twin grain boundaries, special stacking faults, special twist grain boundaries, and the like. This planar grain boundary is characterized by being electrically inactive. In other words, since it is a crystal grain boundary but does not function as a trap that hinders the movement of carriers, it can be considered that it does not substantially exist.

In particular, the crystal axis (the axis perpendicular to the crystal plane) is <11
In the case of the <0> axis, the {211} twin grain boundaries are also called corresponding grain boundaries of {3}. The Σ value is a parameter serving as a guideline indicating the degree of consistency of the corresponding grain boundaries, and it is known that the smaller the Σ value, the better the grain boundaries of consistency.

In a crystalline silicon film obtained by carrying out this embodiment, a crystal grain boundary formed between two crystal grains having a crystal axis of <110> is observed by HR-TEM. In many cases, each lattice fringe is continuous at an angle of about 70.5 °. Therefore, it can be inferred that the crystal grain boundary is a corresponding grain boundary of {3}, that is, a {211} twin grain boundary.

Thus, the crystalline silicon film obtained by carrying out the present embodiment by the present applicant shows that most of the crystal grain boundaries (90% or more,
(Typically 95% or more) is the corresponding grain boundary of $ 3, that is, $ 21.
It is presumed to be 1｝ twin grain boundaries.

Such a crystal structure (accurately, a structure of a crystal grain boundary) indicates that two different crystal grains are bonded to each other with extremely high consistency at the crystal grain boundary. That is, the crystal lattice is continuously connected at the crystal grain boundary, and it is very difficult to form a trap level due to a crystal defect or the like. Therefore, a semiconductor thin film having such a crystal structure can be regarded as having substantially no crystal grain boundaries.

Further, it was confirmed by TEM observation that the defects existing in the crystal grains were almost completely eliminated by the heat treatment step at a high temperature of 700 to 1150 ° C. (corresponding to the thermal oxidation step or the gettering step in this embodiment). Has been confirmed. This is apparent from the fact that the number of defects is significantly reduced before and after this heat treatment step.

The difference in the number of defects was determined by electron spin resonance analysis (El
ectron Spin Resonance (ESR) appears as a difference in spin density. At present, the spin density of the crystalline silicon film manufactured according to the manufacturing process of this embodiment is at least
5 × 10 ¹⁷ spins / cm ³ or less (preferably 3 × 10 ¹⁷ spins / cm ³
Below). However, since this measured value is close to the detection limit of existing measuring devices, the actual spin density is expected to be lower.

As described above, since the crystalline silicon film obtained by carrying out this embodiment has substantially no inside of the crystal grain and no crystal grain boundary, the single-crystal silicon film or the substantially single-crystal silicon Think of it as a membrane.

(Knowledge Regarding Electrical Characteristics of TFT) The TFT manufactured in this example exhibited electrical characteristics comparable to MOSFET. The following data is obtained from a TFT (the active layer has a thickness of 30 nm and the gate insulating film has a thickness of 100 nm) prototyped by the present applicant.

(1) The sub-threshold coefficient as an index of the switching performance (the agility of switching on / off operation) is 60 to 100 mV / decade (typically 60 to 85 mV) for both the N-channel TFT and the P-channel TFT. / decade)
And small. (2) The field effect mobility (μ _FE ) as an index of the operation speed of the TFT is 200 to 650 cm ² / Vs for the N-channel TFT.
(Typically 300-500cm ² / Vs), P-channel type TFT
In (typically ^{150~200cm 2 / Vs) 100~300cm 2 /} Vs greater the. (3) The threshold voltage (V
_th ) is as small as -0.5 to 1.5 V for an N-channel TFT and -1.5 to 0.5 V for a P-channel TFT.

As described above, it has been confirmed that extremely excellent switching characteristics and high-speed operation characteristics can be realized.

(Knowledge on Circuit Characteristics) Next, the frequency characteristics of a ring oscillator manufactured using the TFT formed by carrying out the present embodiment will be described. The ring oscillator is a circuit in which inverter circuits having a CMOS structure are connected in an odd-numbered stage ring shape, and is used to determine a delay time per one stage of the inverter circuit. The configuration of the ring oscillator used in the experiment is as follows. Number of steps: 9 steps Thickness of gate insulating film of TFT: 30 nm and 50 nm Gate length (channel length) of TFT: 0.6 μm

As a result of examining the oscillation frequency with this ring oscillator, it was possible to obtain an oscillation frequency of about 1 GHz as the maximum value. Further, a shift register, which is one of the TEGs of the LSI circuit, was actually manufactured, and the operating frequency was confirmed. As a result, the thickness of the gate insulating film was 30 nm, and the gate length was 0.6.
An output pulse with an operating frequency of 100 MHz was obtained in a shift register circuit having 50 μm, a power supply voltage of 5 V and 50 stages.

The surprising data of the ring oscillator and the shift register as described above is that the TFT of this embodiment is a MOS transistor.
Performance comparable to or superior to FET (electrical characteristics)
Has been shown.

[Embodiment 2] In this embodiment, a specific description will be given of what kind of structure and how to arrange a TFT in a circuit with reference to FIG.

In the AM-LCD, the minimum required operating voltage (power supply voltage) differs depending on the circuit. For example, in a pixel portion, an operation voltage of 14 to 20 V is obtained in consideration of a voltage applied to liquid crystal and a voltage for driving a pixel TFT. Therefore, a TFT that can withstand such a high voltage must be used.

For a shift resist circuit used for a source driver circuit or a gate driver circuit, an operating voltage of about 5 to 10 V is sufficient. There is an advantage that the lower the operating voltage is, the more compatible with the external signal and the more the power consumption can be suppressed. However, the above-mentioned high breakdown voltage type TFT is not suitable for a circuit requiring a high speed operation such as a shift register circuit because the operation speed is sacrificed instead of having a good breakdown voltage characteristic.

As described above, the circuit formed on the substrate is:
Depending on the purpose, there is a circuit for obtaining a TFT that emphasizes the withstand voltage characteristic and a circuit for obtaining a TFT that emphasizes the operation speed.

FIG. 4 specifically shows the structure of this embodiment. FIG. 4A is a top view of a block diagram of the AM-LCD. Reference numeral 401 denotes a pixel portion, which functions as an image display portion. Reference numeral 402a denotes a shift register circuit, 402b denotes a level shifter circuit, and 402c denotes a buffer circuit. The circuit composed of these forms a gate drive circuit as a whole.

In the AM-LCD shown in FIG. 4A, a gate drive circuit is provided with the pixel portion interposed therebetween, and the same gate wiring is shared by the respective gate drive circuits. In this case, the redundancy can be provided such that a voltage can be applied to the gate wiring even if the occurrence of the error occurs.

Reference numeral 403a denotes a shift register circuit,
03b is a level shifter circuit, 403c is a buffer circuit, 4
03d is a sampling circuit, and a circuit composed of these forms a source drive circuit as a whole. A precharge circuit 40 is provided on the opposite side of the pixel unit from the source drive circuit.
4 are provided.

In the AM-LCD having such a configuration, the shift register circuits 402a and 403a are circuits for demanding high-speed operation, and the operating voltage is as low as 3.3 to 10 V (typically 3.3 to 5 V). High breakdown voltage characteristics are not particularly required. Therefore, the thickness of the gate insulating film is preferably as thin as 5 to 50 nm (preferably, 10 to 30 nm).

FIG. 4B is a schematic diagram of a CMOS circuit to be used mainly for a circuit requiring high-speed operation such as a shift register circuit or another signal processing circuit. In FIG. 4B, reference numeral 405a denotes a gate insulating film of an NTFT, and 405b denotes a gate insulating film of a PTFT, which are designed to be as thin as 5 to 50 nm (preferably, 10 to 30 nm).

Next, the CMOS circuit shown in FIG.
It is mainly suitable for the level shifter circuits 402b and 403b, the buffer circuits 402c and 403c, the sampling circuit 403d, and the precharge circuit 404. Since these circuits require a large current to flow, the operating voltage is as high as 14 to 16V. Especially on the gate driver side, sometimes 19V
In some cases, such an operating voltage is required. Therefore, a TFT having very good withstand voltage characteristics (high withstand voltage characteristics) is required.

At this time, in the CMOS circuit shown in FIG. 4C, the gate insulating film 406a of the NTFT and the PTFT
The gate insulating film 406b is designed to have a thickness of 50 to 200 nm (preferably 100 to 150 nm). In a circuit requiring such good withstand voltage characteristics, it is preferable that the gate insulating film be thicker than a TFT such as the shift register circuit illustrated in FIG.

Next, FIG. 4D is a schematic diagram of the pixel portion 401. The pixel TFT requires an operating voltage of 14 to 16 V because the voltage applied to the liquid crystal is also taken into account.
In addition, since the charge stored in the liquid crystal and the storage capacitor must be held for one frame period, the off-current must be as small as possible.

For this reason, in this embodiment, the NTF
The gate insulating film 407 has a double gate structure using T
Film thickness of 50 to 200 nm (preferably 100 to 150 n
m). This film thickness is the same as the CMO shown in FIG.
The film thickness may be the same as that of the S circuit, or may be different.

At the same time, the thickness of the dielectric 408 of the storage capacitor is the same as that of the gate insulating film of the CMOS circuit shown in FIG.
30 nm).

As described above, even in the case of an AM-LCD, various circuits are provided on the same substrate, and the required operating voltage (power supply voltage) may differ depending on the circuit.
In this case, it is necessary to use differently, such as disposing TFTs having different gate insulating films as in the present invention.

[Embodiment 3] In the embodiment 1, in the step of selectively removing the gate insulating film 205, the driving TFT
It is desirable to perform the removal in the region that becomes the storage capacitor or as shown in FIG. In FIG. 5, reference numeral 501 denotes an active layer;
2 is an end of the gate insulating film 205, and 503 and 504 are gate wirings. As shown in FIG. 5, in a portion 505 where the gate wiring crosses over the active layer, it is desirable to leave the gate insulating film 205 at the end of the active layer 501.

At the end of the active layer 501, a phenomenon called edge thinning occurs when a thermal oxidation step is performed later. This is a phenomenon in which the oxidation reaction proceeds so as to sunk under the edge of the active layer, and the edge becomes thinner and simultaneously rises upward. For this reason, when the edge thinning phenomenon occurs, there is a problem that the gate wiring is easily broken when the gate wiring gets over.

However, if the gate insulating film 205 is removed so as to have a structure as shown in FIG. 5, the edge thinning phenomenon can be prevented in the portion 505 over which the gate wiring goes. Therefore, a problem such as disconnection of the gate wiring can be prevented beforehand.

[Embodiment 4] In this embodiment, a structure in which a light-shielding film is provided below a TFT in an AM-LCD having the structure shown in FIG. 1 will be described with reference to FIG.

The structure shown in FIG. 6A is basically the same as that shown in FIG. 1, except that the light shielding films 601 to 601 are provided below each TFT.
604 is provided. FIG. 6B illustrates a structure in which a light-blocking film 605 is provided below a storage capacitor. As the light-shielding films 601 to 605, the same material as that of the gate wiring can be used.

In this embodiment, a tantalum film having a thickness of 250 nm is used so as to easily obtain a tapered shape, and after forming a light-shielding film, it is covered with a silicon nitride film (not shown) to take measures for preventing oxidation. Of course, the same material as the gate wiring may be used. For example,
A structure in which an n-type polysilicon film and a tungsten silicide film are stacked may be employed.

In the case of the structure shown in FIG.
05 can be used as an electrode of the storage capacitor.
In this case, the upper wiring 606 of the storage capacitor and the light shielding film 605 may be set to a fixed potential. Both fixed potentials may be set to the same potential.

In FIGS. 6A and 6B, the light-shielding films 603 and 604 provided below the pixel TFTs may be in a floating state or a fixed potential. As the fixed potential, it is desirable to set at least a potential lower than the lowest potential of the video signal, preferably a lowest power supply potential of the entire circuit formed on the substrate or a potential lower than the lowest power supply potential.

For example, in the case of an AM-LCD, various power supply lines are formed by a drive circuit and other signal processing circuits and a pixel portion, and a predetermined potential is applied to each of them. In other words, there is a certain reference minimum potential, and various voltages are formed based on the lowest potential. The minimum power supply potential refers to a minimum potential that is a reference in all of those circuits.

By setting the light-shielding films 603 and 604 provided below the pixel TFTs to a floating state or a fixed potential, a light-shielding film which does not affect the TFT operation (has almost no parasitic capacitance) is obtained. be able to.

In the driving circuit, light shielding films 601 and 602 are provided for both NTFT and PTFT. Note that N
It is also possible to adopt a structure in which a light shielding film is not provided in one or both of the TFT and the PTFT. At this time, it is desirable that the light-shielding films 601 and 602 are set in a floating state or a fixed potential (preferably the lowest power supply potential), similarly to the above-described light-shielding films 603 and 604 of the pixel TFT. That is, it is desirable to use it only for the purpose of a mere light shielding film.

As described above, by adopting the structure of this embodiment, it is possible to prevent the occurrence of light leakage current due to stray light from the substrate side. Note that the configuration of the present embodiment may be combined with the configuration of the third embodiment.

[Embodiment 5] In this embodiment, an example in which an AM-LCD is manufactured in a step different from that of Embodiment 1 will be described with reference to FIGS.

First, a silicon oxide film (underlying film) and an amorphous silicon film (not shown) are successively formed on a quartz substrate 201 in accordance with the manufacturing process of Example 1, and the amorphous silicon film is crystallized. After that, active layers 203 and 204 made of a crystalline silicon film are formed.

After the formation of the active layer, as shown in FIG. 7A, resist masks 701 to 703 are formed on the active layer, and an element belonging to Group 15 of the periodic table (phosphorus in this embodiment) is added. Perform the process. Thus, regions to which phosphorus is added (hereinafter, referred to as phosphorus-doped regions) 704 to 708 are formed.

It is preferable to oxidize the surface of the active layer before forming resist masks 701 to 703.
By providing the silicon oxide film, the adhesion between the active layer and the resist mask can be improved, and the active layer can be prevented from being contaminated with an organic substance.

The resist masks 701 and 702 are driven TF
It is provided on the active layer of T and is arranged so as to expose a part (or the whole) of a region to be a source region or a drain region later. The resist mask 703 is arranged so as to expose a part (or the whole) of the source region or the drain region of the pixel TFT. At this time, a region serving as a lower electrode of the storage capacitor is entirely exposed to become a phosphorus-doped region 708.

The concentration of phosphorus to be added is 5 × 10 ^18-
1 × 10 ²⁰ atoms / cm ³ (preferably 1 × 10 ^{19 to} 5 × 1
0 ¹⁹ atoms / cm ³ ) is preferable. However, the concentration of phosphorus to be added varies depending on the temperature and time of the later gettering step and the area of the phosphorus-doped region, and is not limited to this concentration range.

Next, the resist masks 701 to 703 are removed, and a heat treatment at 500 to 650 ° C. is applied for 2 to 16 hours to obtain a catalyst element (nickel in this embodiment) used for crystallization of the silicon film. I do. As described in the first embodiment, a temperature of about ± 50 ° C. from the highest temperature of the heat history is required to achieve the gettering action, but the heat treatment for crystallization is performed at 550 to 600 ° C. For,
The gettering action can be sufficiently exhibited by the heat treatment at 500 to 650 ° C.

In this embodiment, heat treatment at 600 ° C. for 8 hours causes nickel to move in the direction of the arrow, that is, to the phosphorus-doped regions 704 to 708. This may be described as nickel being gettered in the phosphorus-doped regions 704-708. Thus, the gettering region 709
To 713 are formed. The gettering area is 70
9 to 712 remain as part or all of the source region or the drain region of the TFT, and 713 remains as a lower electrode of the storage capacitor. (FIG. 7 (B))

After the gettering step shown in FIG. 7B is performed, a gate insulating film (not shown) is formed and patterned to form a gate insulating film 205 of the pixel TFT. Since this step may follow the steps of the first embodiment, the description is omitted.

As described above, the AM shown in FIG.
-LCD is completed. The sectional structure of the AM-LCD shown in FIG. 8 is the same as the sectional structure of the AM-LCD shown in FIG. This embodiment is different from the first embodiment in that the source region 10
3 and 107 and a part of the drain regions 104 and 108 includes regions 801 to 803 containing nickel.

[0141] In the region 801 to 803 containing the ^{nickel, 1 × 10 19 atoms / cm} 3 or more (typically 3 × 10 ¹⁹
Nickel is present at a concentration of about 1 × 10 ²¹ atoms / cm ³ ). However, since nickel exists in a very stable state, it is not a material having unstable TFT characteristics.

In this embodiment (FIG. 8), the drain wiring 127, the drain region 104 of the NTFT and the PTF
The contact portion in contact with the T drain region 108 is a region 802 containing nickel. With such a configuration, a good ohmic contact can be obtained due to the presence of nickel made of metal. Probably because of the silicidation due to the presence of nickel.

In FIG. 8, the source region 103 and the source wiring 125 (or the source region 107 and the source wiring 12
6) are in contact with each other without a region containing nickel, but needless to say, they can be in contact with each other through a region containing nickel as in the case of the drain wiring.

The above is the description of the source region 110 of the pixel portion,
The same applies to the drain region 111. Some of these regions also include regions 804 and 805 containing nickel.

Another feature of this embodiment is that the lower electrode 114 of the storage capacitor has a size of 5 × 10 ¹⁸ to 1 × 10 ²⁰ atoms / cm ^3.
(Preferably, phosphorus exists at a concentration of 1 × 10 ^{19 to} 5 × 10 ¹⁹ atoms / cm ³ ) and 1 × 10 ¹⁹ atoms / cm ³ or more (typically, 3 × 10 ¹⁹ to 1 × 10 ^21). Nickel exists at a concentration of atoms / cm ³ ). That is, the upper wiring 1 of the storage capacitor
Even if no voltage is applied to 22, the electrode 22 can be used as an electrode as it is, which is effective in reducing the power consumption of the AM-LCD.

As described above, as a feature of the manufacturing process of this embodiment, the phosphorus adding step performed for the gettering step is performed in order to make the lower electrode of the storage capacitor conductive. The point also serves as. Thus, power consumption can be reduced without increasing the number of manufacturing steps.

The structure of this embodiment can be freely combined with any of the first to fourth embodiments.

[Embodiment 6] In the manufacturing process of FIG. 7A of Embodiment 5, before forming resist masks 701 to 703, a gate insulating film for a pixel TFT (FIG. C) corresponding to the gate insulating film 205).

That is, the step of adding phosphorus in FIG.
This is performed by through doping via a gate insulating film provided with a thickness of about 200 nm. Then, after removing the resist masks 701 to 703, a gettering step is performed while the active layer is covered with the gate insulating film. After the gettering step is completed, the gate insulating film is patterned to obtain a structure similar to that of FIG.

The advantage of this embodiment is that the active layer is not exposed during the gettering step. When the active layer is exposed, phosphorus present in the phosphorus-doped regions 704 to 708 may diffuse in the atmosphere depending on conditions such as a processing temperature and a processing atmosphere, and may be added to a region to be a channel formation region later. is there. However, such a problem does not occur if the semiconductor device is covered with the gate insulating film as in this embodiment.

The structure of this embodiment can be freely combined with any of the first to fourth embodiments. The features of the finally completed AM-LCD are the same as those in FIG.

[Embodiment 7] In this embodiment, a TFT is formed on a substrate by the manufacturing process shown in Embodiment 1 and an AM-
A case where an LCD is manufactured will be described.

After the state shown in FIG. 3C is obtained, an alignment film is formed on the pixel electrode 259 to a thickness of 80 nm. Next, a color filter, a transparent electrode (counter electrode), and an alignment film are formed on a glass substrate as a counter substrate, and a rubbing process is performed on each alignment film to form a sealing material (sealing material). Then, the substrate on which the TFT is formed and the counter substrate are bonded to each other. Then, the liquid crystal is held in the meantime. Since a well-known means may be used for this cell assembling step, a detailed description is omitted.

Note that a spacer for maintaining the cell gap may be provided as needed. Therefore, when the cell gap can be maintained without the spacer as in the case of an AM-LCD having a diagonal of 1 inch or less, it is not necessary to particularly provide the cell gap.

Next, the AM-L manufactured as described above was used.
FIG. 9 shows the appearance of the CD. An active matrix substrate (refers to a substrate on which a TFT is formed) 901 has a pixel portion 9
02, a source drive circuit 903, a gate drive circuit 904,
Signal processing circuit (signal division circuit, D / A converter circuit,
905, a γ correction circuit, a differential amplifier circuit, etc.)
A C (flexible print circuit) 906 is attached. Note that reference numeral 907 denotes a counter substrate.

This embodiment can be freely combined with any one of Embodiments 1 to 6.

[Embodiment 8] In this embodiment, the case where another means is used for forming a crystalline silicon film in Embodiment 1 will be described.

Specifically, the crystallization of an amorphous silicon film is disclosed in Japanese Patent Application Laid-Open No. Hei 7-130652 (US Patent Application No. 08/3).
29, 644) is used. According to the technique described in the publication, a catalyst element (typically, nickel) that promotes crystallization is selectively retained on the surface of an amorphous silicon film, and crystallization is performed using the portion as a seed for nucleus growth. Technology.

According to this technique, a specific directionality can be given to crystal growth, so that a crystalline silicon film having extremely high crystallinity can be formed.

The structure of this embodiment can be freely combined with any of the structures of the first to seventh embodiments.

[Embodiment 9] In this embodiment, an example will be described in which a source region and a drain region are formed by adding an element belonging to Group 13 or Group 15 of the periodic table in a different order from Embodiment 1. FIG. 10 is used for the description.

First, in accordance with the steps of Embodiment 1, FIG.
Get the state of. Next, a phosphorus addition step is performed to obtain low concentration impurity regions 11a to 11f. At this time, the concentration of phosphorus to be added is (n−), and the low-concentration impurity regions 11a to 11f
Is doped with phosphorus at a concentration of 5 × 10 ^{17 to} 5 × 10 ¹⁸ atoms / cm ³ . (FIG. 10A)

Next, the sidewalls 12a to 12e are formed in the same manner as in the first embodiment, and the phosphorus addition step is performed again.
At this time, the concentration of phosphorus to be added is (n +). Thus, the source region 13, the LDD region 14 and the channel forming region 15 of the NTFT of the driving circuit are defined, and the source region 16, the drain region 17, and the LDD region 18 of the pixel portion are formed.
a, 18b, the channel forming regions 19a, 19b, and the lower electrode 20 of the storage capacitor are defined. (FIG. 10B)

Next, resist masks 21a and 21b are formed, and a boron adding step is performed. At this time, the concentration of boron to be added is (p ++). Thus, the drive circuit NT
A drain region 22 of FT, a source region 23 of PTFT,
A drain region 24 and a channel forming region 25 are defined. (FIG. 10 (C))

The following steps may follow the manufacturing steps of the first embodiment. The configuration of this embodiment can be freely combined with any of Embodiments 2 to 8.

[Embodiment 10] In this embodiment, an example in which a source region and a drain region are formed by adding an element belonging to Group 13 or Group 15 of the periodic table in a different order from that of Embodiment 1 will be described. FIG. 11 is used for the description.

First, in accordance with the steps of Embodiment 1, FIG.
After obtaining the above state, resist masks 27a and 27b are formed. Then, a boron addition step is performed. At this time, the concentration of boron to be added is (p ++). Thus, the source region 28, the drain region 29, and the channel forming region 30 of the PTFT of the driving circuit are defined. (FIG. 11A)

Next, the resist masks 27a and 27b are removed, and the side walls 31a to 31e are formed in the same manner as in the first embodiment.
To form Then, a phosphorus addition step is performed. At this time,
The concentration of phosphorus added is (n +). Thus, 5
Impurity regions 32a to 32d doped with phosphorus at a concentration of × 10 ¹⁹ to 1 × 10 ²¹ atoms / cm ³ are formed. (FIG. 11
(B))

Next, the side walls 31a to 31e are removed, and a phosphorus addition step is performed again. At this time, the concentration of phosphorus added is (n−). Thus, the NTF of the drive circuit
T source region 33, drain region 34, LDD region 3
5 and the channel forming region 36 are defined, and the source region 37, the drain region 38, the LDD regions 39a,
9b, the channel forming regions 40a and 40b, and the lower electrode 41 of the storage capacitor are defined. (FIG. 11 (C))

The following steps may follow the manufacturing steps of the first embodiment. The configuration of this embodiment can be freely combined with any of Embodiments 2 to 8.

[Embodiment 11] In this embodiment, an example in which a source region and a drain region are formed by adding an element belonging to Group 13 or Group 15 of the periodic table in a different order from that of Embodiment 1 will be described. FIG. 12 is used for the description.

First, in accordance with the steps of Embodiment 1, FIG.
After obtaining the above state, resist masks 27a and 27b are formed. Then, a boron addition step is performed. At this time, the concentration of boron to be added is (p ++). Thus, the source region 28, the drain region 29, and the channel forming region 30 of the PTFT of the driving circuit are defined. Up to this point, the operation is the same as in the tenth embodiment. (FIG. 12 (A))

Next, the resist masks 27a and 27b are removed, and a phosphorus addition step is performed. At this time, the concentration of phosphorus added is (n−). Thus, 5 × 10 ^{17 to} 5 × 1
Low concentration impurity regions 43a to 43e to which phosphorus is added at a concentration of 0 ¹⁸ atoms / cm ³ are formed. (FIG. 12 (B))

Next, sidewalls 44a to 44e are formed in the same manner as in the first embodiment. Then, the step of adding phosphorus is performed again. At this time, the concentration of phosphorus to be added is (n +). Thus, the source region 4 of the NTFT of the driving circuit
5, the drain region 46, the LDD region 47 and the channel forming region 48 are defined, and the source region 49, the drain region 50, the LDD regions 51a and 51b and the channel forming regions 52a and 52b of the pixel portion, and the lower electrode 53 of the storage capacitor are defined. I do. (FIG. 12 (C))

The following steps may follow the manufacturing steps of the first embodiment. The configuration of this embodiment can be freely combined with any of Embodiments 2 to 8.

[Embodiment 12] In this embodiment, an example in which a source region and a drain region are formed by adding an element belonging to Group 13 or Group 15 of the periodic table in a different order from that of Embodiment 1 will be described. FIG. 13 is used for the description.

First, according to the steps of Embodiment 1, FIG.
Get the state of. This state is shown in FIG.

Next, after removing the side walls 214 to 216, resist masks 55a and 55b are formed. Then, a boron addition step is performed. At this time, the concentration of boron to be added is (p ++). Thus, the driving circuit P
A source region 56, a drain region 57, and a channel forming region 58 of the TFT are defined. (FIG. 13 (B))

Next, the resist masks 55a and 55b are removed, and the step of adding phosphorus is performed again. At this time, the concentration of phosphorus added is (n−). Thus, the drive circuit NT
The source region 59, the drain region 60, the LDD region 61, and the channel forming region 62 of the FT are defined, and the source region 63, the drain region 64, the LDD region 65a of the pixel portion,
65b, the channel forming regions 66a and 66b, and the lower electrode 67 of the storage capacitor are defined. (FIG. 13 (C))

The following steps may follow the manufacturing steps of the first embodiment. The configuration of this embodiment can be freely combined with any of Embodiments 2 to 8.

[Embodiment 13] In this embodiment, an example in which a source region and a drain region are formed by adding an element belonging to Group 13 or Group 15 of the periodic table in a different order from that of Embodiment 1 will be described. FIG. 14 is used for the description.

First, according to the steps of Embodiment 1, FIG.
Get the state of. Next, a phosphorus addition step is performed to obtain low concentration impurity regions 11a to 11f. At this time, the concentration of phosphorus to be added is (n−), and the low-concentration impurity regions 11a to 11f
Is doped with phosphorus at a concentration of 5 × 10 ^{17 to} 5 × 10 ¹⁸ atoms / cm ³ . (FIG. 14A)

Next, resist masks 68a and 68b are formed, and a boron adding step is performed. At this time, the concentration of boron to be added is (p ++). Thus, the drive circuit PT
The source region 69, the drain region 70, and the channel forming region 71 of the FT are defined. (FIG. 14 (B))

Next, the sidewalls 72a to 72e are formed in the same manner as in the first embodiment, and the phosphorus addition step is performed again.
At this time, the concentration of phosphorus to be added is (n +). Thus, the source region 73, the drain region 74, the LDD region 75, and the channel formation region 76 of the NTFT of the drive circuit are provided.
Are defined, and the source region 77 and the drain region 7 of the pixel portion are formed.
8, LDD regions 79a and 79b and channel forming region 8
0a, 80b, and the lower electrode 81 of the storage capacitor are defined. (FIG. 14C)

The following steps may follow the manufacturing steps of the first embodiment. The configuration of this embodiment can be freely combined with any of Embodiments 2 to 8.

[Embodiment 14] Embodiments 1, 5, 6, 8 to 1
In the manufacturing process shown in FIG. 3, the sidewall is used for forming the LDD region, but the LDD region can be formed by patterning using a normal resist mask.

In this case, the width (length) of the LDD region can be freely designed as compared with the case where the sidewall is used. Therefore, it can be said that this is an effective technique when the width of the LDD region is designed to be 0.1 μm or more.

[Embodiment 15] In this embodiment, an example in which an AM-LCD is manufactured by a process different from that of Embodiment 4 will be described with reference to FIGS. The same parts as those in the fourth embodiment will be described with the same reference numerals.

First, an amorphous silicon film (not shown) is formed on a quartz substrate 201 according to the manufacturing process of the first embodiment, and the amorphous silicon film is crystallized and then formed of a crystalline silicon film. An active layer is formed. After the formation of the active layer, as shown in FIG. 16A, a mask 16 made of a silicon oxide film is formed on the active layer.
01a to 1601c are formed, and an addition step of an element belonging to Group 15 of the periodic table (in this embodiment, phosphorus) is performed. Embodiment 4 may be referred to for the concentration of an element belonging to Group 15 of the periodic table to be added. (FIG. 16A)

Thus, phosphorus-doped regions 704 to 708 are formed. Note that the step of adding an element belonging to Group 15 of the above periodic table may be performed while leaving a resist mask (not shown) used for forming the masks 1601a to 1601c.

Masks 1601a and 1601b are driving TFTs.
And is arranged so as to expose a part of a region which will later become a source region or a drain region. The mask 1601c is arranged so as to expose a part of the source region or the drain region of the pixel TFT. At this time, a part of the region serving as the lower electrode of the storage capacitor is exposed.

Next, with the masks 1601a to 1601c left, heat treatment at 500 to 650 ° C. is applied for 2 to 16 hours to perform a nickel gettering step. In this embodiment, nickel is subjected to a heat treatment at 600 ° C. for 12 hours so that nickel is moved in the direction of the arrow, that is, the phosphorus doped regions 704 to 708
Go to Thus, the gettering regions 709 to 713
Is formed. (FIG. 16 (B))

After the steps up to the gettering step in FIG. 16B are performed, the gettering regions 709 to 713 are removed using the masks 1601a to 1601c as masks.
This step may be performed by a dry etching method using a fluorine-based gas. Thus, crystalline silicon films 1602 to 1604 in which nickel has been reduced or removed are formed. (Figure 1
6 (C))

The crystalline silicon films 1602 and 1603 become an active layer of the driving TFT by patterning, and the crystalline silicon film 1604 is patterned to
It becomes an active layer of FT and a lower electrode of the storage capacitor. Thereafter, the steps after the step in FIG. 7B of the fourth embodiment may be performed.

The structure of this embodiment is similar to that of the first to fourteenth embodiments.
Any embodiment can be freely combined.

[Embodiment 16] In this embodiment, an example in which the first interlayer insulating film is formed by a method different from that of Embodiment 1 will be described. FIG. 17 is used for the description.

First, according to the manufacturing process of the first embodiment, FIG.
The process up to the gettering step shown in FIG. Next, a silicon nitride oxide film (A) 1701 having a thickness of 50 to 100 nm (70 nm in this embodiment) is formed, and 600 nm is formed thereon.
A silicon nitride oxide film (B) 1702 of m to 1 μm (800 nm in this embodiment) is formed. Further, a resist mask 1703 is formed thereon. (FIG. 17A)

Note that the silicon nitride oxide film (A) 1701 and the silicon nitride oxide film (B) 1702 have different composition ratios of nitrogen, oxygen, hydrogen, and silicon. The silicon oxynitride film (A) 1701 contains 7% of nitrogen, 59% of oxygen, 2% of hydrogen, and 32% of silicon.
Is 33% nitrogen, 15% oxygen, 23% hydrogen, and 29% silicon. Of course, it is not limited to this composition ratio.

Further, since the resist mask 1703 has a large thickness, unevenness of the surface of the silicon nitride oxide film (B) 1702 can be completely flattened.

Next, a resist mask 170 is formed by dry etching using a mixed gas of carbon tetrafluoride and oxygen.
3 and the silicon nitride oxide film (B) 1702 are etched. In the case of this embodiment, in dry etching using a mixed gas of carbon tetrafluoride and oxygen, the etching rates of the silicon nitride oxide film (B) 1702 and the resist mask 1703 are almost equal.

By this etching step, the resist mask 1703 is completely removed as shown in FIG.
Part of the silicon oxynitride film (B) 1702 (from the surface to a depth of 300 nm in this embodiment) is etched. As a result, the flatness of the surface of the resist mask 1703 is reflected on the flatness of the surface of the silicon nitride oxide film (B) etched as it is.

Thus, the first interlayer insulating film 1704 having extremely high flatness is obtained. In the case of the present embodiment, the first interlayer insulating film 1
The film thickness of 704 is 500 nm. Subsequent steps may refer to the manufacturing steps in Embodiment 1.

The structure of this embodiment is similar to those of the first to fifteenth embodiments.
Any embodiment can be freely combined.

[Embodiment 17] In this embodiment, an example in which an EL (electroluminescence) display device is manufactured by using the present invention will be described. Note that FIG. 18A is a top view of the EL display device of the present invention, and FIG. 18B is a cross-sectional view thereof.

In FIG. 18A, reference numeral 3001 denotes a substrate;
3002 is a pixel portion, 3003 is a source side driver circuit, 30
Reference numeral 04 denotes a gate-side drive circuit. Each drive circuit reaches an FPC (flexible print circuit) 3006 via a wiring 3005 and is connected to an external device.

At this time, a first seal member 3101, a cover member 3102, a filler 3103, and a second seal member 3104 are provided so as to surround the pixel portion 3002, the source driver circuit 3003, and the gate driver circuit 3004.

FIG. 18 (B) shows FIG.
The driving TFTs included in the source-side driving circuit 3003 on the substrate 3001 (however,
Here, an n-channel TFT and a p-channel TFT are illustrated. ) 3201 and a pixel TFT included in the pixel portion 3002 (here, a TFT for controlling current to an EL element is illustrated) 3202.

In this embodiment, a TFT having the same structure as that of the drive circuit shown in FIG. 1 is used as the drive TFT 3201. Also,
The pixel TFT 3202 has a TF having the same structure as the pixel portion of FIG.
T is used.

Drive TFT 3201 and Pixel TFT 320
An interlayer insulating film (flattening film) 33 made of a resin material is formed on
01 is formed thereon, and a pixel electrode (cathode) 3302 electrically connected to the drain of the pixel TFT 3202 is formed thereon. As the pixel electrode 3302, a conductive film having a light-blocking property (typically, a conductive film containing aluminum, copper, or silver as a main component, or a stacked film of such a conductive film and another conductive film) can be used. In this embodiment, an aluminum alloy is used as a pixel electrode.

An insulating film 3303 is formed on the pixel electrode 3302, and the insulating film 3303 is formed on the pixel electrode 330.
2, an opening is formed. In this opening, an EL (electroluminescence) layer 3304 is formed on the pixel electrode 3302. For the EL layer 3304, a known organic EL material or inorganic EL material can be used. As the organic EL material, there are a low-molecular (monomer) material and a high-molecular (polymer) material, and either may be used.

As a method for forming the EL layer 3304, a known technique may be used. The EL layer may have a stacked structure or a single-layer structure by freely combining a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, or an electron injection layer.

An anode 3305 made of a transparent conductive film is formed on the EL layer 3304. As the transparent conductive film, a compound of indium oxide and tin oxide or a compound of indium oxide and zinc oxide can be used. Also,
It is desirable that moisture and oxygen existing at the interface between the anode 3305 and the EL layer 3304 be eliminated as much as possible. Therefore, it is necessary to devise a method in which both are continuously formed in a vacuum or the EL layer 3304 is formed in a nitrogen or rare gas atmosphere, and the anode 3305 is formed without being exposed to oxygen or moisture.
In this embodiment, the above-described film formation is made possible by using a multi-chamber type (cluster tool type) film formation apparatus.

The anode 3305 is electrically connected to the wiring 3005 in a region indicated by 3306. A wiring 3005 is a wiring for applying a predetermined voltage to the anode 3305, and the FPC 3006 through the conductive material 3307.
Is electrically connected to

As described above, the pixel electrode (cathode) 33
02, an EL element including the EL layer 3304 and the anode 3305 is formed. This EL element is provided with a first sealing material 310
1 and a cover material 3102 bonded to the substrate 3001 by the first sealant 3101, and a filler 310.
3 enclosed.

As the cover material 3102, a glass plate, F
RP (Fiberglass-Reinforced)
Plastics) plate, PVF (polyvinyl fluoride) film, mylar film, polyester film or acrylic film can be used. In the case of this embodiment, the direction of light emission from the EL element is
A light-transmitting material is used in order to move toward 102.

However, when the direction of light emission from the EL element is on the opposite side to the cover material, it is not necessary to use a translucent material, and a metal plate (typically, a stainless steel plate), a ceramic plate, or A sheet having a structure in which an aluminum foil is sandwiched between PVF films or mylar films can be used.

Further, as the filler 3103, an ultraviolet curable resin or a thermosetting resin can be used. Acetate) can be used. By providing a hygroscopic substance (preferably barium oxide) inside the filler 3103, deterioration of the EL element can be suppressed. Note that in this embodiment, a transparent material is used so that light from the EL element can pass through the filler 3103.

[0218] The filler 3103 may contain a spacer. At this time, if the spacer is made of barium oxide, the spacer itself can have hygroscopicity. In the case where a spacer is provided, it is also effective to provide a resin film on the anode 3305 as a buffer layer for relaxing pressure from the spacer.

[0219] The wiring 3005 is formed of a conductive material 3307.
Is electrically connected to the FPC 3006 via the. Wiring 3
Reference numeral 005 denotes a signal transmitted to the pixel portion 3002, the source side driver circuit 3003, and the gate side driver circuit 3004 by FPC3.
006 to be electrically connected to an external device by the FPC 3006.

In this embodiment, the first sealing material 3101
A second sealing material 3104 is provided so as to cover the exposed portion of the FPC 3006 and a part of the FPC 3006, so that the EL element is completely shut off from the outside air. Thus, an EL display device having the cross-sectional structure of FIG. In addition, E of this embodiment
The L display device may be manufactured by combining any of the configurations of the first to sixth or eighth to sixteenth embodiments.

[Embodiment 18] In this embodiment, Embodiment 17 is described.
FIGS. 19A to 19C show an example of a pixel structure that can be used for the pixel portion of the EL display device shown in FIGS. In this embodiment, reference numeral 3401 denotes a switching TFT 340.
2, a source wiring 3403 and a switching TFT 34
02, a gate wiring 3404, a current controlling TFT 34,
05 is a capacitor, 3406 and 3408 are current supply lines,
Reference numeral 3407 denotes an EL element.

FIG. 19A shows an example in which the current supply line 3406 is shared between two pixels. That is, the feature is that two pixels are formed so as to be line-symmetric with respect to the current supply line 3406. In this case, the number of power supply lines can be reduced, so that the pixel portion can have higher definition.

FIG. 19B shows a current supply line 340.
8 is provided in parallel with the gate wiring 3403. Note that in FIG. 19B, the current supply line 3408 and the gate wiring 3403 are provided so as not to overlap with each other.
They can be provided so as to overlap with each other via an insulating film. In this case, the power supply line 3408 and the gate wiring 3403 can share an occupied area, so that the pixel portion can have higher definition.

In FIG. 19C, a current supply line 3408 is provided in parallel with the gate wiring 3403 in the same manner as in the structure of FIG. 19B, and two pixels are connected to the current supply line 3408.
It is characterized in that it is formed so as to be line-symmetric with respect to.
It is also effective to provide the current supply line 3408 so as to overlap with one of the gate wirings 3403. In this case, the number of power supply lines can be reduced, so that the pixel portion can have higher definition.

[Embodiment 19] The electro-optical device of the present invention,
Specifically, various liquid crystals other than the nematic liquid crystal can be used in the liquid crystal display device of the present invention. For example, 1998, SID, "Characteristics and Driving Scheme
of Polymer-Stabilized Monostable FLCD Exhibiting
Fast Response Time and High Contrast Ratio with Gr
ay-Scale Capability "by H. Furue et al., 1997, S
ID DIGEST, 841, "A Full-Color Thresholdless Antife
rroelectric LCD Exhibiting Wide Viewing Angle with
Fast Response Time "by T. Yoshida et al., 1996,
J. Mater. Chem. 6 (4), 671-673, "Thresholdless ant
iferroelectricity in liquid crystals and its appli
It is possible to use the liquid crystals disclosed in "Cation to displays" by S. Inui et al. and US Pat. No. 5,594,569.

Further, ferroelectric liquid crystals (FL) exhibiting an isotropic phase-cholesteric phase-chiral smectic phase transition series
FIG. 20 shows the electro-optical characteristics of a monostable FLC in which the cholesteric phase-chiral smectic phase transition was performed while applying a DC voltage using C) and the cone edge was substantially aligned with the rubbing direction.

A display mode using a ferroelectric liquid crystal as shown in FIG. 20 is called a “Half-V switching mode”. The vertical axis of the graph shown in FIG. 20 is the transmittance (arbitrary unit), and the horizontal axis is the applied voltage. Regarding the "Half-V switching mode", Terada et al.
Characteristic Switching Mode FLCD ", Proceedings of the 46th Joint Lecture on Applied Physics, March 1999, 131st
6, and "Time-Division Full-Color LCD with Ferroelectric Liquid Crystal" by Yoshihara et al., Liquid Crystal Vol. 3, No. 3, page 190.

As shown in FIG. 20, it can be seen that when such a ferroelectric mixed liquid crystal is used, low-voltage driving and gradation display are possible. The liquid crystal display device of the present invention includes:
A ferroelectric liquid crystal having such electro-optical characteristics can also be used.

A liquid crystal exhibiting an antiferroelectric phase in a certain temperature range is called an antiferroelectric liquid crystal (AFLC). As a mixed liquid crystal having an antiferroelectric liquid crystal, there is a so-called thresholdless antiferroelectric mixed liquid crystal exhibiting an electro-optical response characteristic in which transmittance changes continuously with an electric field. This thresholdless antiferroelectric mixed liquid crystal has a so-called V-shaped electro-optical response characteristic, and its driving voltage is about ± 2.5 V.
Some (cell thicknesses of about 1 μm to 2 μm) have been found.

In general, a thresholdless antiferroelectric mixed liquid crystal has a large spontaneous polarization and a high dielectric constant of the liquid crystal itself. Therefore, when a thresholdless antiferroelectric mixed liquid crystal is used for a liquid crystal display device, a relatively large storage capacitance is required for a pixel. Therefore, it is preferable to use a thresholdless antiferroelectric mixed liquid crystal having a small spontaneous polarization.

By using such a thresholdless antiferroelectric mixed liquid crystal in the liquid crystal display device of the present invention, low-voltage driving can be realized, so that low power consumption can be realized.

Note that the liquid crystal shown in this embodiment is the same as that of the first to third embodiments.
It can be used in a liquid crystal display device having any of the sixteen configurations.

[Embodiment 20] The present invention relates to a conventional MOSF
It is also possible to form an interlayer insulating film on the ET and use it when forming a TFT thereon. That is, it is possible to realize a semiconductor device having a three-dimensional structure in which an electro-optical device typified by a reflection type AM-LCD is formed on a semiconductor circuit. The semiconductor circuit is a SIMOX, Smart-
Cut (registered trademark of SOITEC) and ELTRAN (registered trademark of Canon Inc.) may be formed on an SOI substrate.

In implementing this embodiment, any of the configurations of Embodiments 1 to 19 may be combined.

[Embodiment 21] The electro-optical device and the semiconductor circuit of the present invention can be used as a display portion and a signal processing circuit of an electric appliance. Such appliances include video cameras, digital cameras, projectors, projection TVs, goggle-type displays (head-mounted displays), navigation systems, sound reproducers, notebook personal computers, game machines,
A portable information terminal (a mobile computer, a mobile phone, a portable game machine, an electronic book, or the like), an image reproducing device provided with a recording medium, and the like are included. Specific examples of these electric appliances are shown in FIGS.

FIG. 21 (A) shows a mobile phone,
01, audio output unit 2002, audio input unit 2003, display unit 2004, operation switch 2005, antenna 2006
It consists of. The electro-optical device according to the present invention includes the display unit 200.
Fourth, the semiconductor circuit of the present invention can be used for the audio output unit 2002, the audio input unit 2003, the CPU, the memory, and the like.

FIG. 21B shows a video camera, which includes a main body 2101, a display portion 2102, an audio input portion 2103, operation switches 2104, a battery 2105, and an image receiving portion 210.
6. The electro-optical device according to the present invention has a display unit 21.
02, the semiconductor circuit of the present invention can be used for the audio input unit 2103, the CPU, the memory, or the like.

FIG. 21C shows a mobile computer (mobile computer), which comprises a main body 2201, a camera section 2202, an image receiving section 2203, operation switches 2204, and a display section 2205. The electro-optical device of the present invention can be used for the display portion 2205, and the semiconductor circuit of the present invention can be used for a CPU, a memory, and the like.

FIG. 21D shows a goggle type display, which includes a main body 2301, a display portion 2302, and an arm portion 230.
3 The electro-optical device according to the present invention has a display unit 23.
02, the semiconductor circuit of the present invention can be used for a CPU, a memory, and the like.

FIG. 21E shows a rear projector (projection TV).
2, liquid crystal display device 2403, polarizing beam splitter 24
04, reflectors 2405, 2406, screen 2
407. The present invention can be used for the liquid crystal display device 2403, and the semiconductor circuit of the present invention can be used for a CPU, a memory, and the like.

FIG. 21F shows a front projector, which includes a main body 2501, a light source 2502, and a liquid crystal display device 25.
03, an optical system 2504, and a screen 2505. The present invention can be used for the liquid crystal display device 2503, and the semiconductor circuit of the present invention can be used for a CPU, a memory, and the like.

FIG. 22A shows a personal computer, which includes a main body 2601, a video input section 2602, and a display section 26.
03, a keyboard 2604, and the like. The electro-optical device of the present invention is provided in the display unit 2603, and the semiconductor circuit of the present invention is provided in C
It can be used for PUs and memories.

FIG. 22B shows an electronic game machine (game machine), which includes a main body 2701, a recording medium 2702, a display portion 2703, and a controller 2704. The audio and video output from the electronic game machine are reproduced on a display including the housing 2705 and the display portion 2706. As communication means between the controller 2704 and the main body 2701 or communication means between the electronic game apparatus and the display, wired communication, wireless communication, or optical communication can be used. In this embodiment, infrared rays are transmitted to the sensor units 2707 and 2708.
It is configured to detect by. The electro-optical device of the present invention can be used for the display portions 2703 and 2706, and the semiconductor circuit of the present invention can be used for a CPU, a memory, and the like.

FIG. 22C shows a player (image reproducing apparatus) using a recording medium on which a program is recorded (hereinafter, referred to as a recording medium).
A speaker unit 2803, a recording medium 2804, and operation switches 2805 are included. This image reproducing apparatus uses a DVD (Digital Versatile D) as a recording medium.
isc), music, movies, games, and the Internet using CDs and the like. The electro-optical device of the present invention can be used for the display portion 2802, a CPU, a memory, and the like.

FIG. 22D shows a digital camera, which includes a main body 2901, a display portion 2902, an eyepiece portion 2903, operation switches 2904, and an image receiving portion (not shown). The electro-optical device of the present invention can be used for the display portion 2902, the CPU, the memory, and the like.

FIG. 23 shows a detailed description of an optical engine that can be used for the rear projector of FIG. 21E and the front projector of FIG. 21F. FIG. 23A shows an optical engine, and FIG.
3 (B) is a light source optical system built in the optical engine.

The optical engine shown in FIG. 23A has a light source optical system 3001, mirrors 3002, 3005 to 300
7, including dichroic mirrors 3003 and 3004, optical lenses 3008a to 3008c, prism 3011, liquid crystal display device 3010, and projection optical system 3012. The projection optical system 3012 is an optical system including a projection lens. In this embodiment, an example of a three-panel type using three liquid crystal display devices 3010 is shown, but a single-panel type may be used. FIG.
In the optical path indicated by the arrow in (A), an optical lens,
A film having a polarizing function, a film for adjusting a phase difference, an IR film, or the like may be provided.

As shown in FIG. 23B, the light source optical system 3001 includes light sources 3013 and 3014, a combining prism 3015, collimator lenses 3016 and 3020, lens arrays 3017 and 3018, and a polarization conversion element 3019.
including. Note that the light source optical system shown in FIG. 23B uses two light sources, but may use one light source or three or more light sources. Also, somewhere in the optical path of the light source optical system, an optical lens,
A film having a polarizing function, a film for adjusting a phase difference, an IR film, or the like may be provided.

As described above, the applicable range of the present invention is extremely wide, and the present invention can be applied to electric appliances in various fields. Further, the electric appliance of the present embodiment can be realized by using a configuration composed of any combination of the embodiments 1 to 20.

[0250]

According to the present invention, on the same substrate,
TFTs having gate insulating films with different thicknesses can be formed. Therefore, in an electro-optical device typified by an AM-LCD or a semiconductor device including an electric appliance having such an electro-optical device as a display unit, a circuit having an appropriate performance should be arranged according to a specification required by the circuit. And the performance and reliability of the semiconductor device can be significantly improved.

Further, in the pixel portion of the electro-optical device, the dielectric of the storage capacitor can be made thinner without increasing the number of steps, so that a storage capacitor having a large area and a large capacity can be formed. Therefore, even in an electro-optical device having a diagonal width of 1 inch or less, it is possible to secure a sufficient storage capacity without reducing the aperture ratio.

[Brief description of the drawings]

FIG. 1 is a diagram showing a cross-sectional structure of an AM-LCD.

FIG. 2 is a diagram showing a manufacturing process of an AM-LCD.

FIG. 3 is a view showing a manufacturing process of an AM-LCD.

FIG. 4 shows a block diagram and a circuit arrangement of an AM-LCD.

FIG. 5 is a diagram illustrating a structure of a driving TFT (CMOS circuit).

FIG. 6 is a diagram showing a cross-sectional structure of an AM-LCD.

FIG. 7 is a diagram showing a manufacturing process of an AM-LCD.

FIG. 8 is a diagram showing a cross-sectional structure of an AM-LCD.

FIG. 9 is a diagram showing an appearance of an AM-LCD.

FIG. 10 is a diagram showing a manufacturing process of an AM-LCD.

FIG. 11 is a diagram showing a manufacturing process of an AM-LCD.

FIG. 12 is a diagram showing a manufacturing process of an AM-LCD.

FIG. 13 is a view showing a manufacturing process of an AM-LCD.

FIG. 14 is a diagram showing a manufacturing process of an AM-LCD.

FIG. 15 is a diagram illustrating a relationship between concentration distributions when an impurity element is added.

FIG. 16 is a diagram showing a manufacturing process of an AM-LCD.

FIG. 17 is a diagram showing a manufacturing process of an AM-LCD.

FIG. 18 illustrates a top structure and a cross-sectional structure of an EL display device.

FIG. 19 illustrates a structure of a pixel portion of an EL display device.

FIG. 20 is a diagram showing optical response characteristics of a liquid crystal.

FIG. 21 illustrates an example of an electric appliance.

FIG. 22 illustrates an example of an electric appliance.

FIG. 23 is a diagram showing a configuration of an optical engine.

Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat II (Reference) H01L 29/78 613A 616A 616L 627G (72) Inventor Kenji Fukunaga 398 Hase, Atsugi City, Kanagawa Prefecture Inside the Semiconductor Energy Laboratory Co., Ltd.

Claims (17)

[Claims] 1. A semiconductor device having a driving circuit portion and a pixel portion on the same substrate, wherein a driving TFT of the driving circuit portion and a pixel TFT of the pixel portion are provided.
And the thickness of the dielectric of the storage capacitor formed in the pixel portion is different from that of the driving TFT.
A semiconductor device having the same thickness as the gate insulating film. 2. A semiconductor device having a driving circuit portion and a pixel portion on the same substrate, wherein a thickness of a gate insulating film of a driving TFT of the driving circuit portion is:
The thickness of the gate insulating film of the pixel TFT in the pixel portion is smaller than that of the gate insulating film, and the thickness of the dielectric of the storage capacitor formed in the pixel portion is the same as the thickness of the gate insulating film of the driving TFT. Characteristic semiconductor device. 3. The pixel TFT according to claim 1, wherein the gate insulating film of the pixel TFT has a thickness of 50 to 200 nm, and the gate insulating film of the driving TFT has a thickness of 5 to 50 nm.
A semiconductor device, characterized in that: 4. The storage capacitor according to claim 1, wherein the storage capacitor includes an electrode made of a semiconductor film, and the electrode includes a 1 × electrode.
A semiconductor device comprising an element selected from nickel, cobalt, palladium, germanium, platinum, iron and copper at a concentration of 10 ¹⁹ atoms / cm ³ or more. 5. The electrode according to claim 4, wherein the electrode has 5 × 10
A semiconductor device comprising an element belonging to Group 15 of the periodic table at a concentration of ¹⁸ to 1 × 10 ²⁰ atoms / cm ³ . 6. An electric appliance using the semiconductor device according to any one of claims 1 to 5 as a display unit. 7. A first step of forming an amorphous semiconductor film on a substrate, and forming the amorphous semiconductor film using an element selected from nickel, cobalt, palladium, germanium, platinum, iron and copper. Second method for forming a crystalline semiconductor film by phase growth
A step of patterning the crystalline semiconductor film to form an active layer, a fourth step of forming an insulating film on the surface of the active layer, and a thermal oxidation process after the fourth step. A fifth step of oxidizing the active layer, a sixth step of adding an element belonging to Group 15 of the periodic table or an element belonging to Group 13 of the periodic table to the active layer having passed through the fifth step, and after the sixth step And a seventh step of performing a heat treatment at a temperature of 750 to 1150 ° C. 8. A method for manufacturing a semiconductor device including a driving TFT and a pixel TFT on the same substrate, comprising: a first step of forming an amorphous semiconductor film on the substrate; A second step of forming a crystalline semiconductor film by solid phase growth using an element selected from cobalt, palladium, germanium, platinum, iron or copper;
Patterning the crystalline semiconductor film and driving the TFT
A third step of forming an active layer of the pixel TFT and an active layer of the pixel TFT; a fourth step of forming a first insulating film on the active layer of the drive TFT and the active layer of the pixel TFT; A fifth step of etching the film to expose the whole of the active layer of the driving TFT and a part of the active layer of the pixel TFT, and a second step on the surface of the active layer exposed in the fifth step by a thermal oxidation treatment. A sixth step of forming an insulating film; a seventh step of forming a wiring on the first insulating film and the second insulating film; and an element belonging to Group 15 of the periodic table or A method of manufacturing a semiconductor device, comprising: an eighth step of adding an element belonging to Group 13 of the periodic table; and a ninth step of performing a heat treatment at a temperature of 750 to 1150 ° C. after the eighth step. . 9. A first step of forming an amorphous semiconductor film on a substrate, and forming the amorphous semiconductor film by using an element selected from nickel, cobalt, palladium, germanium, platinum, iron and copper. Second method for forming a crystalline semiconductor film by phase growth
A third step of adding an element belonging to Group 15 of the periodic table to the crystalline semiconductor film; and after the third step, the crystalline semiconductor film has a temperature of 500 to 650 ° C.
A fourth step of performing a heat treatment, a fifth step of patterning the crystalline semiconductor film having undergone the fourth step to form an active layer, a sixth step of forming an insulating film on a surface of the active layer, After the sixth step, a seventh step of oxidizing the active layer by a thermal oxidation treatment, and adding an element belonging to Group 15 of the periodic table or an element belonging to Group 13 of the periodic table to the active layer after the seventh step. An eighth step, and a ninth step of performing a heat treatment at a temperature of 750 to 1150 ° C. after the eighth step. 10. A driving TFT and a pixel TFT on the same substrate.
A first step of forming an amorphous semiconductor film on a substrate, wherein the amorphous semiconductor film is selected from nickel, cobalt, palladium, germanium, platinum, iron or copper. To form a crystalline semiconductor film by solid phase growth using a different element
A third step of adding an element belonging to Group 15 of the periodic table to the crystalline semiconductor film; and after the third step, the crystalline semiconductor film has a temperature of 500 to 650 ° C.
A fifth step of patterning the crystalline semiconductor film after the fourth step to form an active layer of the driving TFT and an active layer of the pixel TFT; and an active layer of the driving TFT. And a sixth step of forming a first insulating film on the active layer of the pixel TFT; and etching the first insulating film to remove all of the active layer of the driving TFT and part of the active layer of the pixel TFT. A seventh step of exposing, an eighth step of forming a second insulating film on the surface of the active layer exposed in the seventh step by a thermal oxidation treatment, and a step of forming a second insulating film on the first insulating film and the second insulating film. A ninth step of forming a wiring, a tenth step of adding an element belonging to Group 15 of the periodic table or an element belonging to Group 13 of the periodic table to the active layer using the wiring as a mask, and 750 after the tenth step. Heat treatment at a temperature of ~ 1150 ° C 11. A method for manufacturing a semiconductor device, comprising: performing an eleventh step. 11. The method for manufacturing a semiconductor device according to claim 7, wherein said thermal oxidation treatment is performed at a temperature of 800 to 1150 ° C. 12. A method for manufacturing a semiconductor device having a driving circuit portion and a pixel portion on the same substrate, comprising: forming an element selected from nickel, cobalt, palladium, germanium, platinum, iron or copper on the substrate. A second step of forming a gate insulating film on the semiconductor film by using a first step of forming a semiconductor film using the first step; removing a part of the gate insulating film to expose a part of the active layer; A third step of forming an oxide film on a part of the active layer exposed in the third step by a thermal oxidation process; and a fifth step of forming a gate wiring on the gate insulating film and the oxide film. And forming a sidewall on a side surface of the gate wiring.
A step of adding an element belonging to Group 15 of the periodic table to the active layer using the gate wiring and the sidewall as a mask, an eighth step of removing the sidewall, A ninth step of adding an element belonging to Group 15 of the periodic table to the active layer as a mask, and forming a resist mask on a region that will later become an NTFT;
A tenth step of adding an element belonging to Group 13 of the periodic table; and performing a heat treatment at the same temperature as the fourth step or at a temperature higher than the fourth step. An eleventh step of moving to a region to which an element belonging to Group 15 is added; 13. A method for manufacturing a semiconductor device having a driving circuit portion and a pixel portion on the same substrate, comprising: forming an element selected from nickel, cobalt, palladium, germanium, platinum, iron and copper on the substrate. A first step of forming a semiconductor film by using the semiconductor film; a second step of selectively adding an element belonging to Group 15 of the periodic table to the semiconductor film; A third step of moving the element to a region to which the element belongs, a fourth step of forming a gate insulating film on the semiconductor film, removing a part of the gate insulating film, and removing a part of the active layer. A fifth step of exposing, a sixth step of forming an oxide film on a part of the active layer exposed in the fifth step by thermal oxidation, and forming a gate wiring on the gate insulating film and the oxide film 7th process to do 8 to form a sidewall on a side face of the gate wiring
A ninth step of adding an element belonging to Group 15 of the periodic table to the active layer using the gate wiring and the sidewall as a mask, a tenth step of removing the sidewall, An eleventh step of adding an element belonging to Group 15 of the periodic table to the active layer as a mask, and forming a resist mask on a region that will later become an NTFT;
A twelfth step of adding an element belonging to Group 13; and a method for manufacturing a semiconductor device. 14. The device according to claim 13, wherein the region to which an element belonging to Group 15 of the periodic table is added in the second step includes at least a region serving as a storage capacitor of the pixel portion. A method for manufacturing a semiconductor device. 15. The method according to claim 13, wherein the third step is 5
A method for manufacturing a semiconductor device, which is performed at a temperature of 00 to 650 ° C. 16. The method according to claim 12, wherein
The method for manufacturing a semiconductor device, wherein the thermal oxidation treatment is performed at a temperature of 800 to 1150 ° C. 17. The method according to claim 12, wherein
The method for manufacturing a semiconductor device, wherein the sidewall is formed of a semiconductor film.