WO2012070521A1 - Semiconductor device and method for manufacturing same - Google Patents

Semiconductor device and method for manufacturing same Download PDF

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Publication number
WO2012070521A1
WO2012070521A1 PCT/JP2011/076785 JP2011076785W WO2012070521A1 WO 2012070521 A1 WO2012070521 A1 WO 2012070521A1 JP 2011076785 W JP2011076785 W JP 2011076785W WO 2012070521 A1 WO2012070521 A1 WO 2012070521A1
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Prior art keywords
tft
semiconductor device
region
semiconductor layer
light shielding
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PCT/JP2011/076785
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French (fr)
Japanese (ja)
Inventor
齊藤　肇
堀田　和重
牧田　直樹
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シャープ株式会社
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Publication of WO2012070521A1 publication Critical patent/WO2012070521A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate

Definitions

  • the present invention relates to a semiconductor device including a thin film transistor (TFT) and a manufacturing method thereof.
  • TFT thin film transistor
  • liquid crystal display devices are widely used in televisions, mobile phones, and the like.
  • a TFT having a polycrystalline silicon (p-Si) semiconductor layer (hereinafter sometimes referred to as a polycrystalline silicon TFT) is used as a switching element.
  • the mobility of the polycrystalline silicon TFT is higher than the mobility of the TFT having an amorphous silicon (a-Si) semiconductor layer used in a television or the like.
  • a method for manufacturing a polycrystalline silicon TFT with reduced manufacturing cost has been actively developed.
  • Patent Document 1 in a TFT having a top gate structure, in order to suppress an increase in off current of a TFT due to light from a backlight included in a display device, the TFT is interposed between a light-transmitting substrate and a semiconductor layer.
  • a semiconductor device in which a light shielding layer is provided so as to overlap with a semiconductor layer is disclosed. Further, by performing backside (backside) exposure using the light shielding layer as a mask, a doping mask for forming the source / drain regions is formed in a self-aligned manner with respect to the light shielding layer using a photoresist.
  • a method for manufacturing a semiconductor device in which the number of semiconductor devices does not increase. Further, Patent Document 1 discloses a TFT having a low concentration region (Lightly Doped Drain, hereinafter sometimes referred to as “LDD region”) and a manufacturing method thereof.
  • LDD region Lightly Doped Drain
  • Patent Document 1 when a semiconductor device has an n-type TFT and a p-type TFT such as a CMOS (Complementary Metal Oxide Semiconductor) circuit, or when these TFTs further have TFTs for pixels.
  • CMOS Complementary Metal Oxide Semiconductor
  • a method for manufacturing a semiconductor device having multiple types of TFTs without increasing the number of photomasks when multiple types of TFTs are formed on the same substrate is not disclosed.
  • an object of the present invention is to provide a method for manufacturing a semiconductor device with reduced manufacturing costs and a semiconductor device manufactured by such a manufacturing method when many types of TFTs are formed on the same substrate. .
  • a semiconductor device includes an insulating substrate, a first light-shielding layer formed on the insulating substrate, a pixel TFT supported on the insulating substrate, and an auxiliary capacitor.
  • the electrode is made of the same material as that forming the semiconductor layer of the pixel TFT, and the semiconductor layer of the pixel TFT is formed so as to overlap the first light shielding layer, and the auxiliary capacitor The electrode is formed so as not to overlap the first light shielding layer.
  • the semiconductor layer of the pixel TFT has a low concentration region.
  • the above-described semiconductor device further includes a second light-shielding layer formed on the insulating substrate, and an n-type TFT for a driving circuit supported by the insulating substrate.
  • the semiconductor layer of the n-type TFT is formed so as to overlap the second light shielding layer.
  • the above-described semiconductor device further includes a p-type TFT for a drive circuit supported on the insulating substrate.
  • the above-described semiconductor device has a third light shielding layer formed on the insulating substrate, and the third light shielding layer is formed so as to overlap with a semiconductor layer of the p-type TFT for the drive circuit. Has been.
  • the concentration of the p-type impurity in the channel region of the semiconductor layer of the p-type TFT for the drive circuit is higher than the concentration of the p-type impurity in the channel region of the semiconductor layer of the n-type TFT for the drive circuit.
  • the concentration of the p-type impurity in the channel region of the semiconductor layer of the p-type TFT for the drive circuit is equal to the concentration of the p-type impurity in the channel region of the semiconductor layer of the n-type TFT for the drive circuit.
  • a method for manufacturing a semiconductor device is a method for manufacturing a semiconductor device in which an n-type TFT for a driving circuit, a TFT for a pixel, and an auxiliary capacitor are formed on the same insulating substrate.
  • the step (D) includes a step (D1) in which the auxiliary capacitor electrode is formed of the same material as that for forming the semiconductor layer of the pixel TFT.
  • the above-described method for manufacturing a semiconductor device includes a step (E) of forming a low concentration region in the crystalline semiconductor layer of the pixel TFT.
  • the above-described method for manufacturing a semiconductor device includes: a p-type TFT for the drive circuit; an n-type TFT for the drive circuit; a TFT for the pixel; and the auxiliary capacitor. Form on top.
  • a method of manufacturing a semiconductor device with reduced manufacturing costs and a semiconductor device manufactured by such a manufacturing method when many types of TFTs are formed on the same substrate are provided.
  • FIG. 1 is a schematic cross-sectional view of a semiconductor device 100A according to an embodiment of the present invention
  • (b) is a schematic plan view taken along line A1-A1 ′ of (a)
  • (c) ) Is a schematic plan view taken along line A2-A2 ′ of FIG.
  • (A)-(g) is sectional drawing explaining the manufacturing method of 100 A of semiconductor devices.
  • (A)-(c) is sectional drawing explaining the manufacturing method of 100 A of semiconductor devices. It is typical sectional drawing of the semiconductor device 100B in other embodiment by this invention.
  • (A)-(c) is sectional drawing explaining the manufacturing method of the semiconductor device 100B.
  • (A)-(c) is sectional drawing explaining the manufacturing method of the semiconductor device 100B.
  • (A)-(e) is sectional drawing explaining the manufacturing process of the semiconductor device 100C in further another embodiment by this invention. It is typical sectional drawing of semiconductor device 100D in further another embodiment by this invention.
  • (A) And (b) is sectional drawing explaining the manufacturing method of semiconductor device 100D.
  • (A)-(c) is sectional drawing explaining the manufacturing method of semiconductor device 100D.
  • TFT substrate used in the liquid crystal display device
  • FIG. 1A is a schematic cross-sectional view showing the structure of the TFT 10A1, TFT 10A2, TFT 10A3 and auxiliary capacitor Cs included in the semiconductor device 100A according to the embodiment of the present invention.
  • FIG. 1B is a schematic plan view corresponding to the line A1-A1 ′ in FIG. 1A
  • FIG. 1C corresponds to the line A2-A2 ′ in FIG. It is a typical top view.
  • the semiconductor device 100A includes light shielding layers 4A1 to 4A3 formed on an insulating substrate (for example, a glass substrate) 11, a first base insulating film 12 formed on the light shielding layers 4A1 to 4A3, and a first base insulating film 12
  • the second base insulating film 14 is formed.
  • the semiconductor device 100A includes TFTs 10A1, 10A2 and 10A3 supported by the insulating substrate 11, and an auxiliary capacitor Cs.
  • the TFTs 10A1 to 10A3 and the auxiliary capacitor Cs are formed on the second base insulating film.
  • the light shielding layers 4A1 to 4A3 are formed so as to overlap the crystalline semiconductor layers 30A1 to 30A3 of the corresponding TFTs 10A1 to 10A3, respectively, and light from the backlight hits the crystalline semiconductor layers 30A1 to 30A3 of the TFTs 10A1 to 10A3, for example. It is formed so that there is no.
  • the TFT 10A1 is, for example, an n-type TFT for a drive circuit.
  • the TFT 10A2 is, for example, a p-type TFT for a drive circuit.
  • the TFT 10A3 is, for example, a pixel TFT.
  • the TFT 10A1 has a crystalline semiconductor layer 30A1 including a channel region 33A1, a source region 31A1, and a drain region 35A1. Further, the TFT 10A1 has a gate electrode 13A1 for controlling the conductivity of the channel region 33A1.
  • the gate electrode 13A1 is electrically connected to the gate wiring 13.
  • the channel region 33A1 is formed between the source region 31A1 and the drain region 35A1.
  • the channel region 33A1 is formed so as to overlap the gate electrode 13A1, and the channel region 33A1 is formed in a self-aligned manner with respect to the gate electrode 13A1.
  • the source region 31A1 and the drain region 35A1 have an n-type impurity (for example, phosphorus (P)) at a high concentration.
  • the concentration of the n-type impurity in the source region 31A1 and the drain region 35A1 is preferably, for example, 1 ⁇ 10 20 cm ⁇ 3 to 1 ⁇ 10 21 cm ⁇ 3 (in this embodiment, 5 ⁇ 10 20 cm ⁇ 3 ).
  • Channel region 33A1 typically does not have an n-type impurity.
  • the channel region 33A1 may have a p-type impurity, and may have an n-type impurity at a concentration lower than the n-type impurity concentration of the source region 31A1 and the drain region 35A1.
  • a gate insulating film 16 is formed on the crystalline semiconductor layer 30A1, and a gate electrode 13A1 is formed on the gate insulating film 16. Further, a first protective film 18 is formed so as to cover the gate electrode 13A1, and a second protective film 22 is formed on the first protective film 18. Further, the TFT 10A1 includes a source electrode 15A1 electrically connected to the source region 31A1 and a drain electrode 17A1 electrically connected to the drain region 35A1. The source electrode 15A1 and the drain electrode 17A1 are formed on the second protective film 22.
  • the TFT 10A2 has a crystalline semiconductor layer 30A2 including a channel region 33A2, a source region 31A2, and a drain region 35A2. Further, the TFT 10A2 has a gate electrode 13A2 that controls the conductivity of the channel region 33A2. The gate electrode 13A2 is electrically connected to the gate wiring 13. The channel region 33A2 is formed between the source region 31A2 and the drain region 35A2. The channel region 33A2 is formed so as to overlap the gate electrode 13A2, and the channel region 33A2 is formed in a self-aligned manner with respect to the gate electrode 13A2.
  • the source region 31A2 and the drain region 35A2 have a p-type impurity (for example, boron (B)) at a high concentration.
  • the concentration of the p-type impurity in the source region 31A2 and the drain region 35A2 is preferably, for example, 1.5 ⁇ 10 19 cm ⁇ 3 or more and 3 ⁇ 10 21 cm ⁇ 3 or less (in this embodiment, 5 ⁇ 10 20 cm ⁇ 3 ).
  • Channel region 33A2 typically does not have a p-type impurity.
  • the channel region 33A2 may have p-type impurities at a concentration lower than the p-type impurity concentration of the source region 31A2 and the drain region 35A2.
  • a gate insulating film 16 is formed on the crystalline semiconductor layer 30A2, and a gate electrode 13A2 is formed on the gate insulating film 16. Further, a first protective film 18 is formed so as to cover the gate electrode 13A2, and a second protective film 22 is formed on the first protective film 18. Further, the TFT 10A2 includes a source electrode 15A2 electrically connected to the source region 31A2 and a drain electrode 17A2 electrically connected to the drain region 35A2. The source electrode 15A2 and the drain electrode 17A2 are formed on the second protective film 22.
  • the TFT 10A3 has, for example, a double gate structure.
  • the TFT 10A3 has a crystalline semiconductor layer 30A3 including channel regions 33A3a and 33A3b, a high concentration region 36A, a source region 31A3, and a drain region 35A3. Further, a part of the crystalline semiconductor layer 30A3 has a medium concentration region 38A that functions as an auxiliary capacitance electrode.
  • the high concentration region 36A is formed between the source region 31A3 and the drain region 35A3.
  • the crystalline semiconductor layer 30A3 typically has a low concentration region 32Aa formed between the source region 31A3 and the channel region 33A3a, and a low concentration region formed between the high concentration region 36A and the channel region 33A3a. Density region 34Aa.
  • the crystalline semiconductor layer 30A3 typically includes a low concentration region 32Ab formed between the high concentration region 36A and the channel region 33Ab, and a low concentration region formed between the channel region 33Ab and the drain region 35A3. Region 34Ab. Note that only one of the low concentration region 32Ab and the low concentration region 34Ab may be formed. Further, the medium concentration region 38A of the crystalline semiconductor layer 30A3 is an electrode that forms an auxiliary capacitance Cs described later. The high concentration region 36A is formed between the low concentration region 34Aa and the low concentration region 32Ab.
  • the high concentration region 36A, the source region 31A3, and the drain region 35A3 have a high concentration and an n-type impurity.
  • the concentration of the n-type impurity in the high concentration region 36A, the source region 31A3, and the drain region 35A3 is, for example, 1 ⁇ 10 20 cm ⁇ 3 to 1 ⁇ 10 21 cm ⁇ 3 (in this embodiment, 5 ⁇ 10 20 cm). -3 ) is preferred.
  • Channel regions 33A3a and 33A3b typically do not have n-type impurities.
  • Channel regions 33A3a and 33A3b may have p-type impurities, and may have n-type impurities at a concentration lower than the n-type impurity concentration of source region 31A3 and drain region 35A3.
  • the low concentration regions 32Aa and 34Aa and the low concentration regions 32Ab and 34Ab have n-type impurities at a lower concentration than the high concentration region 36A, the source region 31A3, and the drain region 35A3.
  • the low concentration regions 32Aa and 34Aa and the low concentration regions 32Ab and 34Ab have n-type impurities at higher concentrations than the channel regions 33A3a and 33A3b, respectively.
  • the concentration of the n-type impurity in the low concentration regions 32Aa and 34Aa and the low concentration regions 32Ab and 34Ab is, for example, 1 ⁇ 10 17 cm ⁇ 3 or more and 1 ⁇ 10 19 cm ⁇ 3 or less (in this embodiment, 1 ⁇ 10 18 cm ⁇ 3 ) is preferred.
  • the intermediate concentration region 38A has an n-type impurity.
  • the n-type impurity concentration in the intermediate concentration region 38A is preferably, for example, 1 ⁇ 10 19 cm ⁇ 3 or more and 1 ⁇ 10 21 cm ⁇ 3 or less (1 ⁇ 10 20 cm ⁇ 3 in this embodiment).
  • the concentration of the n-type impurity in the intermediate concentration region 38A (1 ⁇ 10 20 cm ⁇ 3 in this embodiment) is the concentration of the n-type impurity in the low concentration regions 32A and 34A (1 ⁇ 10 18 cm ⁇ in this embodiment). 3 ) It is larger and smaller than the concentration of the n-type impurity in the high concentration region 36A, the source region 31A3 and the drain region 35A3 (in this embodiment, 5 ⁇ 10 20 cm ⁇ 3 ).
  • the concentration of the n-type impurity in the intermediate concentration region 38A is in such a range, it is possible to prevent a crystal current in the intermediate concentration region 38A from increasing and a leakage current from flowing to the auxiliary capacitance Cs, and to achieve a desired electric capacity. Can keep you.
  • a gate insulating film 16 is formed on the crystalline semiconductor layer 30A3, and gate electrodes 13A3a and 13A3b are formed on the gate insulating film 16. Further, a first protective film 18 is formed so as to cover the gate electrodes 13A3a and 13A3b, and a second protective film 22 is formed on the first protective film 18. Further, the TFT 10A3 has a source electrode 15A3 that is electrically connected to the source region 31A3. Further, the TFT 10A3 is electrically connected to the pixel electrode 19A3 via the drain region 35A3 of the crystalline semiconductor layer 30A3. The source electrode 15A3 and the pixel electrode 19A3 are formed on the second protective film 22.
  • the auxiliary capacitance Cs includes a medium concentration region 38A of the crystalline semiconductor layer 30A3 and an auxiliary capacitance electrode 13A3c.
  • a gate insulating film 16 is formed on the intermediate concentration region 38A, and an auxiliary capacitance electrode 13A3c is formed on the gate insulating film 16.
  • the light shielding layers 4A1 to 4A3 are made of a light-shielding metal such as Cr (chromium), Mo (molybdenum), or W (tungsten).
  • the thickness of each of the light shielding layers 4A1 to 4A3 is, for example, not less than 30 nm and not more than 300 nm, more preferably not less than 50 nm and not more than 200 nm.
  • the gate electrodes 13A1 to 13A3, the source electrodes 15A1 to 15A3, the drain electrodes 17A1 and 17A2, and the auxiliary capacitance electrode 13A3c have a laminated structure in which, for example, the upper layer is a Cu (copper) layer and the lower layer is a Ti (titanium) layer.
  • the upper layer may be an Al layer instead of the Cu layer.
  • the thicknesses of the gate electrodes 13A1 to 13A3, the source electrodes 15A1 to 15A3, the drain electrodes 17A1 and 17A2, and the auxiliary capacitance electrode 13A3c are, for example, an upper layer made of Cu or Al, and a lower layer made of Ti. Is 50 nm to 200 nm.
  • the pixel electrode 19A3 is made of, for example, ITO (Indium Tin Oxide).
  • the thickness of the pixel electrode 19A3 is, for example, 50 nm to 300 nm.
  • the crystalline semiconductor layers 30A1 to 30A3 are, for example, polycrystalline silicon layers.
  • the thickness of the crystalline semiconductor layers 30A1 to 30A3 is, for example, 30 nm to 100 nm.
  • the first base insulating film 12 is made of, for example, SiN x (silicon nitride).
  • the thickness of the first base insulating film 12 is, for example, 50 nm to 200 nm.
  • the second base insulating film 14 is made of, for example, SiO 2 (silicon dioxide).
  • the thickness of the second base insulating film 14 is, for example, 50 nm to 200 nm.
  • the gate insulating film 16 is made of, for example, SiO 2 .
  • the thickness of the gate insulating film 16 is, for example, 30 nm to 200 nm.
  • the first protective film 18 is made of, for example, SiN x .
  • the thickness of the first protective film 18 is, for example, 100 nm to 500 nm.
  • the second protective film 22 is made of, for example, SiO 2 .
  • the thickness of the second protective film 22 is, for example, 300 nm to 1000 nm.
  • the semiconductor device 100A has a plurality of TFTs having different characteristics, and light shielding layers 4A1 to 4A3 are formed corresponding to the TFTs.
  • the semiconductor device 100A having such a structure is manufactured by a method for manufacturing a semiconductor device in which the number of photomasks does not increase, as will be described later.
  • the semiconductor device 100A has a structure in which, for example, light from the backlight does not strike the crystalline semiconductor layer of each TFT. Therefore, the semiconductor device 100A can prevent an increase in off current due to, for example, light from a backlight, and the number of photomasks does not increase even when many types of TFTs are formed on the same substrate.
  • the semiconductor device 100A can be manufactured by the manufacturing method.
  • the TFT 10A3 included in the semiconductor device 100A has a low concentration region (Lightly Doped Drain, sometimes referred to as “LDD region” hereinafter), the off-current of the TFT 10A3 can be reduced and long-term reliability can be improved. Can do.
  • LDD region Lightly Doped Drain
  • FIGS. 3 (a) to 3 (c) are cross-sectional views illustrating a method for manufacturing the semiconductor device 100A.
  • light shielding layers 4A1 to 4A3 are formed on an insulating substrate (for example, a glass substrate) 11 by a known method.
  • the light shielding layers 4A1 to 4A3 are made of a light-shielding metal such as Cr (chromium), Mo (molybdenum), or W (tungsten).
  • a first base insulating film 12 containing SiN x is formed by a known method.
  • a second base insulating film 14 containing, for example, SiO 2 is formed on the first base insulating film 12 by a known method.
  • An amorphous semiconductor film 30 is formed on the second base insulating film 14 by a known method.
  • the amorphous semiconductor film 30 is, for example, an amorphous silicon (a-Si) film.
  • the amorphous semiconductor film 30 is irradiated with laser light L1.
  • the laser light L1 at this time is, for example, XeCl (xenon chloride) excimer laser light having a wavelength of 308 nm.
  • a long beam light is scanned to irradiate the entire surface of the insulating substrate 11 with the laser light L1.
  • the amorphous semiconductor film 30 is crystallized to become a crystalline semiconductor film 30a.
  • the crystalline semiconductor film 30a is, for example, a polycrystalline silicon (p-Si) film.
  • the crystalline semiconductor film 30a is patterned into an island shape, and the crystalline semiconductor layer 30A1 that later becomes the active region of the n-type TFT 10A1, and the active region of the p-type TFT 10A2 later.
  • a region overlapping with the light shielding layer 4A3 is a region that later becomes an active region of the pixel TFT 10A3.
  • a region that will later become the auxiliary capacitance electrode 13Ac3 of the auxiliary capacitance Cs does not overlap the light shielding layer 4A3.
  • a gate insulating film 16 is formed on the entire surface of the insulating substrate 11 by a known method so as to cover the crystalline semiconductor layers 30A1 to 30A3.
  • a positive photoresist 71 is formed on the entire surface of the gate insulating film 16.
  • the light shielding layers 4A1 to 4A3 function as a mask, so that positive photoresists 71A1 to 71A3 are formed so as to overlap the light shielding layers 4A1 to 4A3.
  • the other portions are removed by development because they do not have the light shielding layers 4A1 to 4A3.
  • an n-type impurity for example, phosphorus (P)
  • n1 is doped into part of the crystalline semiconductor layer 30A3 to form an intermediate concentration region 38A.
  • Conditions for doping the n-type impurity n1 include, for example, using PH 3 (phosphine) as a doping gas, an acceleration voltage of 60 kV to 90 kV, and a dose of 1 ⁇ 10 14 cm ⁇ 2 to 1 ⁇ 10 16 cm ⁇ 2 ( In this embodiment, an acceleration voltage of 70 kV and a dose of 1 ⁇ 10 15 cm ⁇ 2 are preferable.
  • the n-type impurity n1 is not implanted into regions other than the medium concentration region 38A.
  • the medium concentration region 38A is a region that becomes an electrode of the auxiliary capacitor Cs.
  • the positive photoresists 71A1 to 71A3 are removed by a known method.
  • the gate electrodes 13A1 to 13A3 and the auxiliary capacitance electrode 13A3c are formed on the gate insulating film 16 by a known method.
  • n-type impurities for example, phosphorus (P)
  • P phosphorus
  • the conditions for doping the n-type impurity are, for example, using PH 3 (phosphine) as a doping gas, and a dose amount of 1 ⁇ 10 12 cm ⁇ 2 to 1 ⁇ 10 14 cm ⁇ 2 in a range of acceleration voltage of 60 kV to 90 kV. (In this embodiment, an acceleration voltage of 70 kV and a dose of 2 ⁇ 10 13 cm ⁇ 2 ) are preferable.
  • channel regions 33A1 to 33A3 are formed in the respective crystalline semiconductor layers 30A1 to 30A3.
  • the channel regions 33A1 to 33A3 are formed in a self-aligned manner with respect to the gate electrodes 13A1 to 13A3.
  • regions not covered with the gate electrodes 13A1 to 13A3 and the auxiliary capacitance electrode 13A3c contain the n-type impurity n2.
  • Channel regions 33A1 to 33A3 do not contain n-type impurity n2.
  • a positive photoresist 72a is formed so as to cover the crystalline semiconductor layer 30A2. Further, positive photoresists 72b and 72c are formed by a known method so as to cover the gate electrodes 13A3a and 13A3b and the region to be the LDD region of the pixel TFT.
  • the crystalline semiconductor layers 30A1 and 30A3 are doped with an n-type impurity n3.
  • the conditions for doping the n-type impurity n3 are, for example, using PH 3 (phosphine) as a doping gas, an acceleration voltage of 60 kV to 90 kV, and a dose of 1 ⁇ 10 15 cm ⁇ 2 to 1 ⁇ 10 16 cm ⁇ 2 ( In the present embodiment, an acceleration voltage of 70 kV and a dose of 5 ⁇ 10 15 cm ⁇ 2 are preferable.
  • an n-type impurity n3 is doped in a region not covered with the positive photoresists 72a to 72c.
  • a source region 31A1 and a drain region 35A1 are formed in the crystalline semiconductor layer 30A1. Further, a source region 31A3, a drain region 35A3, and a high concentration region 36A3 are formed in the crystalline semiconductor layer 30A3.
  • the crystalline semiconductor layer 30A2 is not doped with the n-type impurity n3.
  • LDD regions 32A and 34A are formed in regions other than the channel regions 33A3a and 33A3b, which are covered with the positive photoresists 72b and 72c and the auxiliary capacitance electrode 13A3c in the crystalline semiconductor layer 30A3.
  • the positive photoresists 72a to 72c are removed by a known method. Thereafter, positive photoresists 73a and 73b are formed by a known method. The positive photoresist 73a is formed so as to cover the crystalline semiconductor layer 30A1, and the positive photoresist 73b is formed so as to cover the crystalline semiconductor layer 30A3.
  • the crystalline semiconductor layer 30A2 is doped with a high-concentration p-type impurity (for example, boron (B)) p1.
  • a high-concentration p-type impurity for example, boron (B)
  • the conditions for doping the p-type impurity p1 are, for example, using diborane (B 2 H 6 ) as a doping gas, an acceleration voltage of 40 kV to 90 kV, and a dose of 1 ⁇ 10 15 cm ⁇ 2 to 1 ⁇ 10 16 cm ⁇ . 2 or less (accelerating voltage 75 kV, dose amount 3 ⁇ 10 15 cm ⁇ 2 in this embodiment) is preferable.
  • the source region 31A2 and the drain region 35A2 are formed in the crystalline semiconductor layer 30A2.
  • the crystalline semiconductor layers 30A1 and 30A3 are not doped with p-type impurities.
  • the positive photoresist resists 73a and 73b are removed by a known method.
  • a first protective film 18 containing SiN x is formed on the gate electrodes 13A1 to 13A3 by a known method.
  • a second protective film 22 containing SiO 2 is formed on the first protective film 18 by a known method. After that, heat treatment for hydrogenation may be performed.
  • contact holes are formed in the first and second protective films 18 and 22 and the gate insulating film 16 by a known method.
  • source electrodes 15A1 to 15A3, drain electrodes 17A1 and 17A2, and a pixel electrode 19A3 are formed on the second protective film 18 by a known method.
  • Source electrodes 15A1 to 15A3 are electrically connected to the source regions of the respective crystalline semiconductor layers.
  • the drain electrodes 17A1 and 17A2 and the pixel electrode 19A3 are electrically connected to the drain regions of the respective crystalline semiconductor layers. Also.
  • Contact holes are also formed in the first and second protective films 18 and 22 on the gate electrodes 13A1 and 13A2, and the source electrodes 15A1 and 15A2 (or the drain electrodes 17A1 and 17A2) and the gate electrodes 13A1 and 13A2 are electrically connected. You may connect. Thereafter, a further protective film may be formed on the source electrodes 15A1 to 15A3 (or the drain electrodes 17A1 and 17A2).
  • semiconductor devices 100B to 100D according to other embodiments of the present invention having the same effect as the semiconductor device 100A will be described. Note that components common to the semiconductor device 100A are denoted by the same reference numerals to avoid duplicate description.
  • FIG. 4 is a schematic cross-sectional view of the semiconductor device 100B. Although not shown, the semiconductor device 100B includes the same pixel TFT as the pixel TFT 10A3 included in the semiconductor device 100A.
  • the semiconductor device 100B shown in FIG. 4 does not form the light shielding layers 4A2 and 4A3 of the semiconductor device 100A, and further includes a semiconductor containing a low concentration p-type impurity in the channel region 33A1 of the crystalline semiconductor layer 30A1 of the TFT 10A1. Device.
  • the concentration of the p-type impurity in the channel region 33A1 is preferably, for example, from 1 ⁇ 10 16 cm ⁇ 3 to 5 ⁇ 10 17 cm ⁇ 3 (in this embodiment, 5 ⁇ 10 16 cm ⁇ 3 ).
  • FIGS. 5 (a) to 5 (c) and FIGS. 6 (a) to 6 (c) are cross-sectional views illustrating a method for manufacturing the semiconductor device 100B. Note that a description of a method for manufacturing a portion related to the pixel TFT 10A3 in the semiconductor device 100B is omitted.
  • the light shielding layer 4A1, the first and second base insulating films 12 and 14, the island-shaped crystalline semiconductor layers 30A1 and 30A2, the gate insulation are formed on the insulating substrate 11 by the method described above.
  • a film 16 is formed.
  • the above-described light shielding layers 4A2 and 4A3 are not formed.
  • a p-type impurity for example, boron (B)
  • B boron
  • a negative photoresist 74 ′ is formed on the entire surface of the insulating substrate 11 by a known method.
  • the crystalline semiconductor layer 30A1 is doped with the p-type impurity p2 using the negative photoresist 74 as a mask.
  • Conditions for doping the p-type impurity p2 include, for example, diborane (B 2 H 6 ) as a doping gas, an acceleration voltage of 40 kV to 90 kV, and a dose of 1 ⁇ 10 11 cm ⁇ 2 to 1 ⁇ 10 12 cm ⁇ . 2 or less (accelerating voltage 75 kV, dose amount 3 ⁇ 10 11 cm ⁇ 2 in this embodiment) is preferable.
  • the crystalline semiconductor layer 30A2 covered with the negative photoresist 74 is not doped with the p-type impurity p2.
  • gate electrodes 13A1 and 13A2 are respectively formed on the crystalline semiconductor layers 30A1 and 30A2 by a known method.
  • a positive photoresist 75 is formed so as to cover the crystalline semiconductor layer 30A1.
  • p-type impurity p1 is doped using positive photoresist 75 and gate electrode 13A2 as a mask.
  • the conditions for doping the p-type impurity p1 are, for example, using diborane (B 2 H 6 ) as a doping gas, an acceleration voltage of 40 kV to 90 kV, and a dose of 1 ⁇ 10 15 cm ⁇ 2 to 1 ⁇ 10 16 cm ⁇ . 2 or less (accelerating voltage 75 kV, dose amount 3 ⁇ 10 15 cm ⁇ 2 in this embodiment) is preferable.
  • the source region 31A2 and the drain region 35A2 are formed in the crystalline semiconductor layer 30A2, and the channel region 33A2 is formed in a region where the p-type impurity p1 is not doped.
  • the channel region 33A2 is formed in a self-aligned manner with respect to the gate electrode 13A2.
  • the channel region 33A2 is formed between the source region 31A2 and the drain region 35A2.
  • the positive photoresist 75 is removed by a known method, and a positive photoresist 76 is formed by a known method so as to cover the crystalline semiconductor layer 30A2.
  • the n-type impurity n3 is doped into the crystalline semiconductor layer 30A1 using the positive photoresist 76 and the gate electrode 13A1 as a mask.
  • the conditions for doping the n-type impurity n3 include, for example, PH 3 as a doping gas, an acceleration voltage of 60 kV to 90 kV, and a dose of 1 ⁇ 10 15 cm ⁇ 2 to 1 ⁇ 10 16 cm ⁇ 2 (this embodiment) In this case, an acceleration voltage of 70 kV and a dose of 5 ⁇ 10 15 cm ⁇ 2 are preferable.
  • a source region 31A1 and a drain region 35A1 are formed in the crystalline semiconductor layer 30A1, and a channel region 33A1 is formed in a region where the n-type impurity n3 is not doped.
  • the channel region 33A1 is formed in a self-aligned manner with respect to the gate electrode 13A1, and is formed between the source region 31A1 and the drain region 35A1.
  • the positive photoresist 76 is removed by a known method, and heat treatment is performed as described above.
  • the first protective film 18, the second protective film 22, the source electrodes 15A1 and 15A2, the drain electrodes 17A1 and 17A2, and the pixel electrode are formed, and the semiconductor device 100B shown in FIG. 4 is manufactured. Is done.
  • a semiconductor device 100C according to still another embodiment of the present invention will be described. Note that since the structure of the semiconductor device 100C is the same as that of the semiconductor device 100B, a cross-sectional view of the semiconductor device 100C is omitted.
  • the semiconductor device 100C is a semiconductor device in which p-type impurities are not contained in the channel regions 33A1 to 33A3 of all the crystalline semiconductor layers 30A1 to 30A3 of the semiconductor device 100B.
  • FIG. 7A to 7E are cross-sectional views illustrating a method for manufacturing the semiconductor device 100C.
  • the manufacturing method of the pixel TFT 10A3 is also omitted in the semiconductor device 100C.
  • the light shielding layer 4A1, the first and second base insulating films 12 and 14, the island-shaped crystalline semiconductor layers 30A1 and 30A2, and the gate insulating film 16 are formed on the insulating substrate 11 by the method described above. At this time, the above-described light shielding layers 4A2 and 4A3 are not formed. Further, after forming the gate insulating film 16, a p-type impurity (for example, boron (B)) may be doped on the entire surface of each of the crystalline semiconductor layers 30A1 to 30A3.
  • a p-type impurity for example, boron (B)
  • gate electrodes 13A1 and 13A2 are formed on the crystalline semiconductor layer 30A1 and the crystalline semiconductor layer 30A2 by a known method. Gate electrodes 13A1 and 13A2 are formed on gate insulating film 16, respectively.
  • a positive photoresist 77 is formed on the entire surface of the insulating substrate 11 by a known method. Thereafter, exposure is performed from the back surface of the insulating substrate 11 using the light shielding layer 4A1 and the gate electrode 13A2 as a mask (back surface exposure). At this time, a photomask is not used.
  • the light shielding layer 4A1 and the gate electrode 13A2 are used as a mask, so that a positive photoresist 77 corresponding to the light shielding layer 4A1 and the gate electrode 13A2 is formed.
  • the crystalline semiconductor layer 30A1 is covered with a positive photoresist 77a, and is patterned so that a positive photoresist 77b is formed on the gate electrode 13A2. At this time, the regions to be the source region and the drain region of the crystalline semiconductor layer 30A2 are not covered with the positive photoresist 77b.
  • the crystalline semiconductor layer 30A2 is doped with a p-type impurity p1 using the positive photoresists 77a and 77b as a mask.
  • the conditions for doping the p-type impurity p1 are, for example, PH 3 (phosphine) as a doping gas, an acceleration voltage of 40 kV to 90 kV, and a dose of 1 ⁇ 10 15 cm ⁇ 2 to 1 ⁇ 10 16 cm ⁇ 2 ( In this embodiment, an acceleration voltage of 75 kV and a dose amount of 3 ⁇ 10 15 cm ⁇ 2 are preferable.
  • the crystalline semiconductor layer 30A1 is covered with the positive photoresist 77a, the p-type impurity p1 is not doped into the crystalline semiconductor layer 30A1. Further, the region covered with the gate electrode 13A2 in the crystalline semiconductor layer 30A2 is not doped with the p-type impurity p1. As a result, the source region 31A2 and the drain region 35A2 are formed in the crystalline semiconductor layer 30A2. A channel region 33A2 is formed between the source region 31A2 and the drain region 35A2. The channel region 33A2 is formed in a self-aligned manner with respect to the gate electrode 13A2.
  • the positive photoresists 77a and 77b are removed by a known method.
  • a positive photoresist 78 is formed so as to cover the crystalline semiconductor layer 30A2.
  • the crystalline semiconductor layer 30A1 is doped with an n-type impurity n3.
  • the conditions for doping the n-type impurity n3 include, for example, PH 3 as a doping gas, an acceleration voltage of 60 kV to 90 kV, and a dose of 1 ⁇ 10 15 cm ⁇ 2 to 1 ⁇ 10 16 cm ⁇ 2 (this embodiment) In this case, an acceleration voltage of 70 kV and a dose of 5 ⁇ 10 15 cm ⁇ 2 are preferable.
  • the source region 31A1 and the drain region 35A1 are formed in the crystalline semiconductor layer 30A1.
  • a channel region 33A1 is formed between the source region 31A1 and the drain region 35A1.
  • the channel region 33A1 is formed in a self-aligned manner with respect to the gate electrode 13A1.
  • the positive photoresist 78 is removed by a known method, and heat treatment is performed as described above.
  • the first protective film 18, the second protective film 22, the source electrodes 15A1 and 15A2, the drain electrodes 17A1 and 17A2, and the pixel electrode 19A3 are formed, and the semiconductor device 100C is manufactured.
  • FIG. 8 is a schematic cross-sectional view of the semiconductor device 100D.
  • the semiconductor device 100D has a structure in which the p-type TFT 10A2 and the light shielding layer 4A2 included in the semiconductor device 100A are not formed.
  • the semiconductor device 100D has the same effect as the semiconductor device 100A.
  • FIGS. 9A and 9B and FIGS. 10A to 10C are cross-sectional views illustrating a method for manufacturing the semiconductor device 100D.
  • the gate insulating film 16 is formed. Further, after the gate insulating film 16 is formed, a p-type impurity may be doped on the entire surface of each crystalline semiconductor layer.
  • a positive photoresist 79 is formed on the entire surface of the insulating substrate 11 by a known method.
  • a positive photoresist 79 is patterned corresponding to each of the light shielding layers 4A1 and 4A3 to form island-shaped positive electrodes. Mold photoresists 81a and 81b are formed. The positive photoresists 81a and 81b are formed in a self-aligned manner with respect to the light shielding layers 4A1 and 4A3, respectively. In addition, the region serving as the electrode of the auxiliary capacitance Cs in the crystalline semiconductor layer 30A3 is not covered with the positive photoresist 81b.
  • n-type impurity n1 is doped in the crystalline semiconductor layer 30A3 in the region serving as the electrode of the auxiliary capacitor Cs using the positive photoresists 81a and 81b as a mask.
  • Conditions for doping the n-type impurity n1 include, for example, using PH 3 (phosphine) as a doping gas, an acceleration voltage of 60 kV to 90 kV, and a dose of 1 ⁇ 10 14 cm ⁇ 2 to 1 ⁇ 10 16 cm ⁇ 2 ( In this embodiment, an acceleration voltage of 70 kV and a dose of 1 ⁇ 10 15 cm ⁇ 2 are preferable.
  • the region covered with the positive photoresist 81b is not doped with the n-type impurity n1.
  • an intermediate concentration region 38A is formed in the crystalline semiconductor layer 30A3.
  • the positive photoresists 81a and 81b are removed by a known method.
  • gate electrodes 13A1, 13A3a and 13A3b, and auxiliary capacitance electrodes 13A3c are formed on the crystalline semiconductor layers 30A1 and 30A3 by a known method. Further, the auxiliary capacitance electrode 13A3c is formed so as to overlap the intermediate concentration region 38A.
  • the crystalline semiconductor layers 30A1 and 30A3 are doped with an n-type impurity n2 using the gate electrodes 13A1 and 13A3a and 13A3b and the auxiliary capacitance electrode 13A3c as a mask.
  • the conditions for doping the n-type impurity n2 are, for example, using PH 3 (phosphine) as a doping gas and a dose amount of 1 ⁇ 10 12 cm ⁇ 2 or more and 1 ⁇ 10 14 cm ⁇ 2 in an acceleration voltage range of 60 kV to 90 kV.
  • acceleration voltage 70 kV, dose amount 5 ⁇ 10 13 cm ⁇ 2 is preferable.
  • a region to be a low concentration region (LDD region) of the pixel TFT 10A3 is formed by doping with the n-type impurity.
  • regions overlapping with the gate electrodes 13A1, 13A3a, and 13A3b are channel regions 33A1, 33Aa, and 33Ab, respectively.
  • positive photoresists 82a and 82b are formed by a known method so as to cover a region that becomes a low concentration region (LDD region) of the pixel TFT 10A3.
  • LDD region low concentration region
  • the n-type impurity n3 is doped into the crystalline semiconductor layers 30A1 and 30A3 using the positive photoresists 82a and 82b, the gate electrode 13A1, and the auxiliary capacitance electrode 13A3c as a mask.
  • the conditions for doping the n-type impurity n3 are, for example, using PH 3 (phosphine) as a doping gas, an acceleration voltage of 60 kV to 90 kV, and a dose of 1 ⁇ 10 15 cm ⁇ 2 to 1 ⁇ 10 16 cm ⁇ 2 ( In the present embodiment, an acceleration voltage of 70 kV and a dose of 5 ⁇ 10 15 cm ⁇ 2 are preferable.
  • the source region 31A1 and the drain region 35A1 are formed in the crystalline semiconductor layer 30A1.
  • a source region 31A3, a drain region 35A3, and a high concentration region 36A3 are formed in the crystalline semiconductor layer 30A3.
  • the positive photoresists 82a and 82b are removed by a known method, and heat treatment is performed as described above.
  • the first protective film 18, the second protective film 22, the source electrodes 15A1 and 15A3, the drain electrode 17A1, and the pixel electrode 19A3 are formed, and the semiconductor device 100D shown in FIG. 8 is manufactured.
  • the semiconductor devices 100A to 100D provide a method for manufacturing a semiconductor device with reduced manufacturing costs and a semiconductor device manufactured by such a manufacturing method when many types of TFTs are formed on the same substrate. .
  • the applicable range of the present invention is extremely wide, and it can be applied to a semiconductor device provided with a TFT or an electronic device in any field having such a semiconductor device.
  • a circuit or a pixel portion formed by implementing the present invention can be used for an active matrix liquid crystal display device or an organic EL display device.
  • Such a display device can be used for a display screen of a mobile phone or a portable game machine, a monitor of a digital camera, or the like. Therefore, the present invention can be applied to all electronic devices in which a liquid crystal display device or an organic EL display device is incorporated.

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Abstract

A semiconductor device (100A) of the present invention comprises: an insulating substrate (11); a first light-blocking layer (4A3) that is formed on the insulating substrate (11); a TFT (10A3) for a pixel, said TFT being supported by the insulating substrate (11); and an auxiliary capacitor (Cs). An electrode of the auxiliary capacitor (Cs) is formed from the same material as a semiconductor layer of the TFT (10A3) for a pixel. The semiconductor layer of the TFT (10A3) for a pixel is formed so as to overlap the first light-blocking layer (4A3). The electrode of the auxiliary capacitor (Cs) is formed so as not to overlap the first light-blocking layer (4A3).

Description

半導体装置およびその製造方法Semiconductor device and manufacturing method thereof
　本発明は、薄膜トランジスタ（Thin Film Transistor：ＴＦＴ）を備える半導体装置およびその製造方法に関する。 The present invention relates to a semiconductor device including a thin film transistor (TFT) and a manufacturing method thereof.
　現在、液晶表示装置は、テレビ、および、携帯電話などに広く用いられている。特に、携帯電話などに用いられている液晶表示装置には、スイッチング素子として、多結晶シリコン（ｐ－Ｓｉ）半導体層を備えるＴＦＴ（以下、多結晶シリコンＴＦＴという場合がある）が用いられている。多結晶シリコンＴＦＴの移動度は、テレビなどに使われているアモルファスシリコン（ａ－Ｓｉ）半導体層を備えるＴＦＴの移動度よりも高い。また、製造コストが削減された多結晶シリコンＴＦＴの製造方法も盛んに開発されている。 Currently, liquid crystal display devices are widely used in televisions, mobile phones, and the like. In particular, in a liquid crystal display device used for a mobile phone or the like, a TFT having a polycrystalline silicon (p-Si) semiconductor layer (hereinafter sometimes referred to as a polycrystalline silicon TFT) is used as a switching element. . The mobility of the polycrystalline silicon TFT is higher than the mobility of the TFT having an amorphous silicon (a-Si) semiconductor layer used in a television or the like. In addition, a method for manufacturing a polycrystalline silicon TFT with reduced manufacturing cost has been actively developed.
　特許文献１には、トップゲート構造を有するＴＦＴにおいて、表示装置が有するバックライトからの光により、ＴＦＴのオフ電流が増大することを抑制するために、透光性基板と半導体層との間に、半導体層と重なるように遮光層を設けた半導体装置が開示されている。さらに、遮光層をマスクとして、背面（裏面）露光を行うことにより、ソース・ドレイン領域の形成のためのドーピングマスクを、フォトレジストを用いて遮光層に対して自己整合的に形成し、フォトマスクの数が増大しない半導体装置の製造方法が開示されている。さらに、特許文献１には、低濃度領域（Lightly Doped Drain、以下「ＬＤＤ領域」という場合がある。）を有するＴＦＴおよびその製造方法が開示されている。 In Patent Document 1, in a TFT having a top gate structure, in order to suppress an increase in off current of a TFT due to light from a backlight included in a display device, the TFT is interposed between a light-transmitting substrate and a semiconductor layer. A semiconductor device in which a light shielding layer is provided so as to overlap with a semiconductor layer is disclosed. Further, by performing backside (backside) exposure using the light shielding layer as a mask, a doping mask for forming the source / drain regions is formed in a self-aligned manner with respect to the light shielding layer using a photoresist. Discloses a method for manufacturing a semiconductor device in which the number of semiconductor devices does not increase. Further, Patent Document 1 discloses a TFT having a low concentration region (Lightly Doped Drain, hereinafter sometimes referred to as “LDD region”) and a manufacturing method thereof.
特開２００３－３４７５５６号公報JP 2003-347556 A
　しかしながら特許文献１には、例えば、半導体装置がＣＭＯＳ（Complementary Metal Oxide Semiconductor）回路のようにｎ型ＴＦＴとｐ型ＴＦＴとを有する場合、または、これらのＴＦＴにさらに画素用のＴＦＴを有する場合などのように、多種類のＴＦＴを同一基板上に形成する場合において、フォトマスクの数を増大させずに、多種類のＴＦＴを有する半導体装置を製造する方法は開示されていない。 However, in Patent Document 1, for example, when a semiconductor device has an n-type TFT and a p-type TFT such as a CMOS (Complementary Metal Oxide Semiconductor) circuit, or when these TFTs further have TFTs for pixels. As described above, a method for manufacturing a semiconductor device having multiple types of TFTs without increasing the number of photomasks when multiple types of TFTs are formed on the same substrate is not disclosed.
　そこで本発明の目的は、多種類のＴＦＴを同一基板上に形成する場合における、製造コストが削減された半導体装置の製造方法およびそのような製造方法によって製造される半導体装置を提供することにある。 SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a method for manufacturing a semiconductor device with reduced manufacturing costs and a semiconductor device manufactured by such a manufacturing method when many types of TFTs are formed on the same substrate. .
　本発明による半導体装置は、絶縁基板と、前記絶縁基板上に形成された第１遮光層と、前記絶縁基板に支持された、画素用のＴＦＴと、補助容量とを有し、前記補助容量の電極は、前記画素用のＴＦＴの半導体層を形成する材料と同一の材料から形成されており、前記画素用のＴＦＴの半導体層は、前記第１遮光層と重なるように形成され、前記補助容量の電極は、前記第１遮光層と重ならないように形成されている。 A semiconductor device according to the present invention includes an insulating substrate, a first light-shielding layer formed on the insulating substrate, a pixel TFT supported on the insulating substrate, and an auxiliary capacitor. The electrode is made of the same material as that forming the semiconductor layer of the pixel TFT, and the semiconductor layer of the pixel TFT is formed so as to overlap the first light shielding layer, and the auxiliary capacitor The electrode is formed so as not to overlap the first light shielding layer.
　ある実施形態において、前記画素用のＴＦＴの半導体層は、低濃度領域を有する。 In one embodiment, the semiconductor layer of the pixel TFT has a low concentration region.
　ある実施形態において、上述の半導体装置は、前記絶縁基板上に形成された第２遮光層と、前記絶縁基板に支持された、駆動回路用のｎ型ＴＦＴとをさらに有し、前記駆動回路用のｎ型ＴＦＴの半導体層は、前記第２遮光層と重なるように形成されている。 In one embodiment, the above-described semiconductor device further includes a second light-shielding layer formed on the insulating substrate, and an n-type TFT for a driving circuit supported by the insulating substrate. The semiconductor layer of the n-type TFT is formed so as to overlap the second light shielding layer.
　ある実施形態において、上述の半導体装置は、前記絶縁基板上に支持された、駆動回路用のｐ型ＴＦＴをさらに有する。 In one embodiment, the above-described semiconductor device further includes a p-type TFT for a drive circuit supported on the insulating substrate.
　ある実施形態において、上述の半導体装置は、前記絶縁基板上に形成された第３遮光層を有し、前記第３遮光層は、前記駆動回路用のｐ型ＴＦＴの半導体層と重なるように形成されている。 In one embodiment, the above-described semiconductor device has a third light shielding layer formed on the insulating substrate, and the third light shielding layer is formed so as to overlap with a semiconductor layer of the p-type TFT for the drive circuit. Has been.
　ある実施形態において、前記駆動回路用のｐ型ＴＦＴの半導体層のチャネル領域におけるｐ型不純物の濃度は、前記駆動回路用のｎ型ＴＦＴの半導体層のチャネル領域におけるｐ型不純物の濃度より大きい。 In one embodiment, the concentration of the p-type impurity in the channel region of the semiconductor layer of the p-type TFT for the drive circuit is higher than the concentration of the p-type impurity in the channel region of the semiconductor layer of the n-type TFT for the drive circuit.
　ある実施形態において、前記駆動回路用のｐ型ＴＦＴの半導体層のチャネル領域におけるｐ型不純物の濃度は、前記駆動回路用のｎ型ＴＦＴの半導体層のチャネル領域におけるｐ型不純物の濃度と等しい。 In one embodiment, the concentration of the p-type impurity in the channel region of the semiconductor layer of the p-type TFT for the drive circuit is equal to the concentration of the p-type impurity in the channel region of the semiconductor layer of the n-type TFT for the drive circuit.
　本発明による半導体装置の製造方法は、駆動回路用のｎ型ＴＦＴと、画素用のＴＦＴと、補助容量とを同一絶縁基板上に形成する半導体装置の製造方法であって、前記絶縁基板上に遮光層を形成する工程（Ａ）と、前記遮光層と重なるように半導体層を形成する工程（Ｂ）と、前記遮光層に対して自己整合的にフォトレジストを形成する工程（Ｃ）と、前記フォトレジストをマスクとして、前記半導体層に不純物をドーピングする工程（Ｄ）とを包含する。 A method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device in which an n-type TFT for a driving circuit, a TFT for a pixel, and an auxiliary capacitor are formed on the same insulating substrate. A step (A) of forming a light shielding layer, a step (B) of forming a semiconductor layer so as to overlap the light shielding layer, a step (C) of forming a photoresist in a self-aligned manner with respect to the light shielding layer, And (D) doping the semiconductor layer with impurities using the photoresist as a mask.
　ある実施形態において、前記工程（Ｄ）は、前記補助容量の電極を、前記画素用のＴＦＴの半導体層を形成する材料と同じ材料で形成する工程（Ｄ１）を包含する。 In one embodiment, the step (D) includes a step (D1) in which the auxiliary capacitor electrode is formed of the same material as that for forming the semiconductor layer of the pixel TFT.
　ある実施形態において、上述の半導体装置の製造方法は、前記画素用のＴＦＴの結晶質半導体層に、低濃度領域を形成する工程（Ｅ）を包含する。 In one embodiment, the above-described method for manufacturing a semiconductor device includes a step (E) of forming a low concentration region in the crystalline semiconductor layer of the pixel TFT.
　ある実施形態において、上述の半導体装置の製造方法は、前記駆動回路用のｐ型ＴＦＴと、前記駆動回路用のｎ型ＴＦＴと、前記画素用のＴＦＴと、前記補助容量とを前記同一絶縁基板上に形成する。 In one embodiment, the above-described method for manufacturing a semiconductor device includes: a p-type TFT for the drive circuit; an n-type TFT for the drive circuit; a TFT for the pixel; and the auxiliary capacitor. Form on top.
　本発明によると、多種類のＴＦＴを同一基板上に形成する場合における、製造コストが削減された半導体装置の製造方法およびそのような製造方法によって製造される半導体装置が提供される。 According to the present invention, there are provided a method of manufacturing a semiconductor device with reduced manufacturing costs and a semiconductor device manufactured by such a manufacturing method when many types of TFTs are formed on the same substrate.
（ａ）は、本発明による実施形態における半導体装置１００Ａの模式的な断面図であり、（ｂ）は、（ａ）のＡ１－Ａ１’線に沿った模式的な平面図であり，（ｃ）は、（ａ）のＡ２－Ａ２’線に沿った模式的な平面図である。(A) is a schematic cross-sectional view of a semiconductor device 100A according to an embodiment of the present invention, (b) is a schematic plan view taken along line A1-A1 ′ of (a), and (c) ) Is a schematic plan view taken along line A2-A2 ′ of FIG. （ａ）～（ｇ）は、半導体装置１００Ａの製造方法を説明する断面図である。(A)-(g) is sectional drawing explaining the manufacturing method of 100 A of semiconductor devices. （ａ）～（ｃ）は、半導体装置１００Ａの製造方法を説明する断面図である。(A)-(c) is sectional drawing explaining the manufacturing method of 100 A of semiconductor devices. 本発明による他の実施形態における半導体装置１００Ｂの模式的な断面図である。It is typical sectional drawing of the semiconductor device 100B in other embodiment by this invention. （ａ）～（ｃ）は、半導体装置１００Ｂの製造方法を説明する断面図である。(A)-(c) is sectional drawing explaining the manufacturing method of the semiconductor device 100B. （ａ）～（ｃ）は、半導体装置１００Ｂの製造方法を説明する断面図である。(A)-(c) is sectional drawing explaining the manufacturing method of the semiconductor device 100B. （ａ）～（ｅ）は、本発明によるさらに他の実施形態における半導体装置１００Ｃの製造工程を説明する断面図である。(A)-(e) is sectional drawing explaining the manufacturing process of the semiconductor device 100C in further another embodiment by this invention. 本発明によるさらに他の実施形態における半導体装置１００Ｄの模式的な断面図である。It is typical sectional drawing of semiconductor device 100D in further another embodiment by this invention. （ａ）および（ｂ）は、半導体装置１００Ｄの製造方法を説明する断面図である。(A) And (b) is sectional drawing explaining the manufacturing method of semiconductor device 100D. （ａ）～（ｃ）は、半導体装置１００Ｄの製造方法を説明する断面図である。(A)-(c) is sectional drawing explaining the manufacturing method of semiconductor device 100D.
　以下、図面を参照して本発明による実施形態を説明するが、本発明は例示する実施形態に限定されない。液晶表示装置に用いられる半導体装置（ＴＦＴ基板）を例示して本発明による実施形態の半導体装置およびその製造方法を説明する。 Hereinafter, embodiments according to the present invention will be described with reference to the drawings, but the present invention is not limited to the illustrated embodiments. The semiconductor device (TFT substrate) used in the liquid crystal display device will be exemplified to describe the semiconductor device and the manufacturing method thereof according to the embodiment of the present invention.
　図１（ａ）は、本発明による実施形態における半導体装置１００Ａが有するＴＦＴ１０Ａ１、ＴＦＴ１０Ａ２およびＴＦＴ１０Ａ３ならびに補助容量Ｃｓの構造を示す模式的な断面図である。図１（ｂ）は、図１（ａ）のＡ１－Ａ１’線に対応する模式的な平面図であり、図１（ｃ）は、図１（ａ）のＡ２－Ａ２’線に対応する模式的な平面図である。 FIG. 1A is a schematic cross-sectional view showing the structure of the TFT 10A1, TFT 10A2, TFT 10A3 and auxiliary capacitor Cs included in the semiconductor device 100A according to the embodiment of the present invention. FIG. 1B is a schematic plan view corresponding to the line A1-A1 ′ in FIG. 1A, and FIG. 1C corresponds to the line A2-A2 ′ in FIG. It is a typical top view.
　半導体装置１００Ａは、絶縁基板（例えばガラス基板）１１上に形成された遮光層４Ａ１～４Ａ３と、遮光層４Ａ１～４Ａ３上に形成された第１下地絶縁膜１２と、第１下地絶縁膜１２上に形成された第２下地絶縁膜１４とを有する。さらに、半導体装置１００Ａは、絶縁基板１１に支持されたＴＦＴ１０Ａ１、ＴＦＴ１０Ａ２およびＴＦＴ１０Ａ３ならびに補助容量Ｃｓを有する。ＴＦＴ１０Ａ１～１０Ａ３および補助容量Ｃｓは、第２下地絶縁膜１４上に形成されている。遮光層４Ａ１～４Ａ３は、それぞれ、対応するＴＦＴ１０Ａ１～１０Ａ３の結晶質半導体層３０Ａ１～３０Ａ３と重なるように形成され、ＴＦＴ１０Ａ１～１０Ａ３の結晶質半導体層３０Ａ１～３０Ａ３に、例えばバックライトからの光が当たらないように形成されている。ＴＦＴ１０Ａ１は、例えば駆動回路用のｎ型ＴＦＴである。ＴＦＴ１０Ａ２は、例えば駆動回路用のｐ型ＴＦＴである。ＴＦＴ１０Ａ３は、例えば画素用のＴＦＴである。 The semiconductor device 100A includes light shielding layers 4A1 to 4A3 formed on an insulating substrate (for example, a glass substrate) 11, a first base insulating film 12 formed on the light shielding layers 4A1 to 4A3, and a first base insulating film 12 The second base insulating film 14 is formed. Further, the semiconductor device 100A includes TFTs 10A1, 10A2 and 10A3 supported by the insulating substrate 11, and an auxiliary capacitor Cs. The TFTs 10A1 to 10A3 and the auxiliary capacitor Cs are formed on the second base insulating film. The light shielding layers 4A1 to 4A3 are formed so as to overlap the crystalline semiconductor layers 30A1 to 30A3 of the corresponding TFTs 10A1 to 10A3, respectively, and light from the backlight hits the crystalline semiconductor layers 30A1 to 30A3 of the TFTs 10A1 to 10A3, for example. It is formed so that there is no. The TFT 10A1 is, for example, an n-type TFT for a drive circuit. The TFT 10A2 is, for example, a p-type TFT for a drive circuit. The TFT 10A3 is, for example, a pixel TFT.
　ＴＦＴ１０Ａ１は、チャネル領域３３Ａ１、ソース領域３１Ａ１およびドレイン領域３５Ａ１を含む結晶質半導体層３０Ａ１を有する。さらに、ＴＦＴ１０Ａ１は、チャネル領域３３Ａ１の導電性を制御するゲート電極１３Ａ１を有する。ゲート電極１３Ａ１は、ゲート配線１３と電気的に接続している。チャネル領域３３Ａ１は、ソース領域３１Ａ１とドレイン領域３５Ａ１との間に形成されている。チャネル領域３３Ａ１はゲート電極１３Ａ１と重なるように形成され、チャネル領域３３Ａ１は、ゲート電極１３Ａ１に対して自己整合的に形成されている。ソース領域３１Ａ１およびドレイン領域３５Ａ１は、高濃度でｎ型不純物（例えばリン（Ｐ））を有する。ソース領域３１Ａ１およびドレイン領域３５Ａ１のｎ型不純物の濃度は、例えば１×１０20ｃｍ-3以上１×１０21ｃｍ-3以下（本実施形態において、５×１０20ｃｍ-3）が好ましい。チャネル領域３３Ａ１は、典型的には、ｎ型不純物を有しない。チャネル領域３３Ａ１は、ｐ型不純物を有する場合もあり、ソース領域３１Ａ１およびドレイン領域３５Ａ１のｎ型不純物濃度より低い濃度でｎ型不純物を有する場合もある。 The TFT 10A1 has a crystalline semiconductor layer 30A1 including a channel region 33A1, a source region 31A1, and a drain region 35A1. Further, the TFT 10A1 has a gate electrode 13A1 for controlling the conductivity of the channel region 33A1. The gate electrode 13A1 is electrically connected to the gate wiring 13. The channel region 33A1 is formed between the source region 31A1 and the drain region 35A1. The channel region 33A1 is formed so as to overlap the gate electrode 13A1, and the channel region 33A1 is formed in a self-aligned manner with respect to the gate electrode 13A1. The source region 31A1 and the drain region 35A1 have an n-type impurity (for example, phosphorus (P)) at a high concentration. The concentration of the n-type impurity in the source region 31A1 and the drain region 35A1 is preferably, for example, 1 × 10 20 cm −3 to 1 × 10 21 cm −3 (in this embodiment, 5 × 10 20 cm −3 ). Channel region 33A1 typically does not have an n-type impurity. The channel region 33A1 may have a p-type impurity, and may have an n-type impurity at a concentration lower than the n-type impurity concentration of the source region 31A1 and the drain region 35A1.
　結晶質半導体層３０Ａ１上にはゲート絶縁膜１６が形成され、ゲート絶縁膜１６上にはゲート電極１３Ａ１が形成されている。さらに、ゲート電極１３Ａ１を覆うように第１保護膜１８が形成され、第１保護膜１８上に第２保護膜２２が形成されている。さらに、ＴＦＴ１０Ａ１は、ソース領域３１Ａ１と電気的に接続するソース電極１５Ａ１と、ドレイン領域３５Ａ１と電気的に接続するドレイン電極１７Ａ１とを有する。ソース電極１５Ａ１およびドレイン電極１７Ａ１は、第２保護膜２２上に形成されている。 A gate insulating film 16 is formed on the crystalline semiconductor layer 30A1, and a gate electrode 13A1 is formed on the gate insulating film 16. Further, a first protective film 18 is formed so as to cover the gate electrode 13A1, and a second protective film 22 is formed on the first protective film 18. Further, the TFT 10A1 includes a source electrode 15A1 electrically connected to the source region 31A1 and a drain electrode 17A1 electrically connected to the drain region 35A1. The source electrode 15A1 and the drain electrode 17A1 are formed on the second protective film 22.
　ＴＦＴ１０Ａ２は、チャネル領域３３Ａ２、ソース領域３１Ａ２およびドレイン領域３５Ａ２を含む結晶質半導体層３０Ａ２を有する。さらに、ＴＦＴ１０Ａ２は、チャネル領域３３Ａ２の導電性を制御するゲート電極１３Ａ２を有する。ゲート電極１３Ａ２は、ゲート配線１３と電気的に接続されている。チャネル領域３３Ａ２は、ソース領域３１Ａ２とドレイン領域３５Ａ２との間に形成されている。チャネル領域３３Ａ２はゲート電極１３Ａ２と重なるように形成され、チャネル領域３３Ａ２はゲート電極１３Ａ２に対して自己整合的に形成されている。ソース領域３１Ａ２およびドレイン領域３５Ａ２は、高濃度でｐ型不純物（例えばボロン（Ｂ））を有する。ソース領域３１Ａ２およびドレイン領域３５Ａ２のｐ型不純物の濃度は、例えば１．５×１０19ｃｍ-3以上３×１０21ｃｍ-3以下（本実施形態において、５×１０20ｃｍ-3）が好ましい。チャネル領域３３Ａ２は、典型的には、ｐ型不純物を有しない。チャネル領域３３Ａ２は、ソース領域３１Ａ２およびドレイン領域３５Ａ２のｐ型不純物濃度より低い濃度でｐ型不純物を有する場合もある。 The TFT 10A2 has a crystalline semiconductor layer 30A2 including a channel region 33A2, a source region 31A2, and a drain region 35A2. Further, the TFT 10A2 has a gate electrode 13A2 that controls the conductivity of the channel region 33A2. The gate electrode 13A2 is electrically connected to the gate wiring 13. The channel region 33A2 is formed between the source region 31A2 and the drain region 35A2. The channel region 33A2 is formed so as to overlap the gate electrode 13A2, and the channel region 33A2 is formed in a self-aligned manner with respect to the gate electrode 13A2. The source region 31A2 and the drain region 35A2 have a p-type impurity (for example, boron (B)) at a high concentration. The concentration of the p-type impurity in the source region 31A2 and the drain region 35A2 is preferably, for example, 1.5 × 10 19 cm −3 or more and 3 × 10 21 cm −3 or less (in this embodiment, 5 × 10 20 cm −3 ). . Channel region 33A2 typically does not have a p-type impurity. The channel region 33A2 may have p-type impurities at a concentration lower than the p-type impurity concentration of the source region 31A2 and the drain region 35A2.
　結晶質半導体層３０Ａ２上にはゲート絶縁膜１６が形成され、ゲート絶縁膜１６上にゲート電極１３Ａ２が形成されている。さらに、ゲート電極１３Ａ２を覆うように第１保護膜１８が形成され、第１保護膜１８上に第２保護膜２２が形成されている。さらに、ＴＦＴ１０Ａ２は、ソース領域３１Ａ２と電気的に接続するソース電極１５Ａ２と、ドレイン領域３５Ａ２と電気的に接続するドレイン電極１７Ａ２とを有する。ソース電極１５Ａ２およびドレイン電極１７Ａ２は、第２保護膜２２上に形成されている。 A gate insulating film 16 is formed on the crystalline semiconductor layer 30A2, and a gate electrode 13A2 is formed on the gate insulating film 16. Further, a first protective film 18 is formed so as to cover the gate electrode 13A2, and a second protective film 22 is formed on the first protective film 18. Further, the TFT 10A2 includes a source electrode 15A2 electrically connected to the source region 31A2 and a drain electrode 17A2 electrically connected to the drain region 35A2. The source electrode 15A2 and the drain electrode 17A2 are formed on the second protective film 22.
　ＴＦＴ１０Ａ３は、例えばダブルゲート構造を有する。ＴＦＴ１０Ａ３は、チャネル領域３３Ａ３ａおよび３３Ａ３ｂ、高濃度領域３６Ａ、ソース領域３１Ａ３、ならびに、ドレイン領域３５Ａ３を含む結晶質半導体層３０Ａ３を有する。また、結晶質半導体層３０Ａ３の一部は、補助容量電極として機能する中濃度領域３８Ａを有する。高濃度領域３６Ａは、ソース領域３１Ａ３とドレイン領域３５Ａ３との間に形成されている。さらに、結晶質半導体層３０Ａ３は、典型的には、ソース領域３１Ａ３とチャネル領域３３Ａ３ａとの間に形成された低濃度領域３２Ａａと、高濃度領域３６Ａとチャネル領域３３Ａ３ａとの間に形成された低濃度領域３４Ａａとを有する。なお、低濃度領域３２Ａａおよび低濃度領域３４Ａａは、いずれか一方のみ形成される場合もある。さらに、結晶質半導体層３０Ａ３は、典型的には、高濃度領域３６Ａとチャネル領域３３Ａｂと間に形成された低濃度領域３２Ａｂと、チャネル領域３３Ａｂとドレイン領域３５Ａ３との間に形成された低濃度領域３４Ａｂとを有する。なお、低濃度領域３２Ａｂおよび低濃度領域３４Ａｂは、いずれか一方のみ形成される場合もある。さらに、結晶質半導体層３０Ａ３の中濃度領域３８Ａは、後述する補助容量Ｃｓを形成する電極である。高濃度領域３６Ａは、低濃度領域３４Ａａと低濃度領域３２Ａｂとの間に形成されている。 The TFT 10A3 has, for example, a double gate structure. The TFT 10A3 has a crystalline semiconductor layer 30A3 including channel regions 33A3a and 33A3b, a high concentration region 36A, a source region 31A3, and a drain region 35A3. Further, a part of the crystalline semiconductor layer 30A3 has a medium concentration region 38A that functions as an auxiliary capacitance electrode. The high concentration region 36A is formed between the source region 31A3 and the drain region 35A3. Further, the crystalline semiconductor layer 30A3 typically has a low concentration region 32Aa formed between the source region 31A3 and the channel region 33A3a, and a low concentration region formed between the high concentration region 36A and the channel region 33A3a. Density region 34Aa. Note that only one of the low concentration region 32Aa and the low concentration region 34Aa may be formed. Further, the crystalline semiconductor layer 30A3 typically includes a low concentration region 32Ab formed between the high concentration region 36A and the channel region 33Ab, and a low concentration region formed between the channel region 33Ab and the drain region 35A3. Region 34Ab. Note that only one of the low concentration region 32Ab and the low concentration region 34Ab may be formed. Further, the medium concentration region 38A of the crystalline semiconductor layer 30A3 is an electrode that forms an auxiliary capacitance Cs described later. The high concentration region 36A is formed between the low concentration region 34Aa and the low concentration region 32Ab.
　高濃度領域３６Ａ、ソース領域３１Ａ３、および、ドレイン領域３５Ａ３は、高濃度でｎ型不純物を有する。高濃度領域３６Ａ、ソース領域３１Ａ３、および、ドレイン領域３５Ａ３のｎ型不純物の濃度は、例えば１×１０20ｃｍ-3以上１×１０21ｃｍ-3以下（本実施形態において、５×１０20ｃｍ-3）が好ましい。チャネル領域３３Ａ３ａおよび３３Ａ３ｂは、典型的には、ｎ型不純物を有しない。チャネル領域３３Ａ３ａおよび３３Ａ３ｂは、ｐ型不純物を有する場合もあり、ソース領域３１Ａ３およびドレイン領域３５Ａ３のｎ型不純物濃度より低い濃度でｎ型不純物を有する場合もある。低濃度領域３２Ａａおよび３４Ａａ、ならびに、低濃度領域３２Ａｂおよび３４Ａｂは、高濃度領域３６Ａ、ソース領域３１Ａ３およびドレイン領域３５Ａ３よりも低い濃度でｎ型不純物を有する。また、低濃度領域３２Ａａおよび３４Ａａ、ならびに、低濃度領域３２Ａｂおよび３４Ａｂは、それぞれチャネル領域３３Ａ３ａおよび３３Ａ３ｂよりも高い濃度でｎ型不純物を有する。低濃度領域３２Ａａおよび３４Ａａ、ならびに、低濃度領域３２Ａｂおよび３４Ａｂのｎ型不純物の濃度は、例えば１×１０17ｃｍ-3以上１×１０19ｃｍ-3以下（本実施形態において、１×１０18ｃｍ-3）が好ましい。さらに、典型的には、低濃度領域３２Ａａおよび３４Ａａは、ゲート電極１３Ａ３ａに覆われておらず、低濃度領域３２Ａｂおよび３４Ａｂは、ゲート電極１３Ａ３ｂに覆われていない。しかしながら、低濃度領域３２Ａａおよび３４Ａａは、ゲート電極１３Ａ３ａに覆われていてもよいし、低濃度領域３２Ａｂおよび３４Ａｂは、ゲート電極１３Ａ３ｂに覆われていてもよい。中濃度領域３８Ａは、ｎ型不純物を有する。中濃度領域３８Ａのｎ型不純物の濃度は、例えば１×１０19ｃｍ-3以上１×１０21ｃｍ-3以下（本実施形態において、１×１０20ｃｍ-3）が好ましい。中濃度領域３８Ａのｎ型不純物の濃度（本実施形態において、１×１０20ｃｍ-3）は、低濃度領域３２Ａおよび３４Ａのｎ型不純物の濃度（本実施形態において、１×１０18ｃｍ-3）より大きく高濃度領域３６Ａ、ソース領域３１Ａ３およびドレイン領域３５Ａ３のｎ型不純物の濃度（本実施形態において、５×１０20ｃｍ-3）より小さい。中濃度領域３８Ａのｎ型不純物の濃度が、このような範囲にあると、中濃度領域３８Ａの結晶欠陥が増大して補助容量Ｃｓにリーク電流が流れることを防ぐことができ、所望の電気容量を保つことができる。 The high concentration region 36A, the source region 31A3, and the drain region 35A3 have a high concentration and an n-type impurity. The concentration of the n-type impurity in the high concentration region 36A, the source region 31A3, and the drain region 35A3 is, for example, 1 × 10 20 cm −3 to 1 × 10 21 cm −3 (in this embodiment, 5 × 10 20 cm). -3 ) is preferred. Channel regions 33A3a and 33A3b typically do not have n-type impurities. Channel regions 33A3a and 33A3b may have p-type impurities, and may have n-type impurities at a concentration lower than the n-type impurity concentration of source region 31A3 and drain region 35A3. The low concentration regions 32Aa and 34Aa and the low concentration regions 32Ab and 34Ab have n-type impurities at a lower concentration than the high concentration region 36A, the source region 31A3, and the drain region 35A3. The low concentration regions 32Aa and 34Aa and the low concentration regions 32Ab and 34Ab have n-type impurities at higher concentrations than the channel regions 33A3a and 33A3b, respectively. The concentration of the n-type impurity in the low concentration regions 32Aa and 34Aa and the low concentration regions 32Ab and 34Ab is, for example, 1 × 10 17 cm −3 or more and 1 × 10 19 cm −3 or less (in this embodiment, 1 × 10 18 cm −3 ) is preferred. Further, typically, the low concentration regions 32Aa and 34Aa are not covered with the gate electrode 13A3a, and the low concentration regions 32Ab and 34Ab are not covered with the gate electrode 13A3b. However, the low concentration regions 32Aa and 34Aa may be covered with the gate electrode 13A3a, and the low concentration regions 32Ab and 34Ab may be covered with the gate electrode 13A3b. The intermediate concentration region 38A has an n-type impurity. The n-type impurity concentration in the intermediate concentration region 38A is preferably, for example, 1 × 10 19 cm −3 or more and 1 × 10 21 cm −3 or less (1 × 10 20 cm −3 in this embodiment). The concentration of the n-type impurity in the intermediate concentration region 38A (1 × 10 20 cm −3 in this embodiment) is the concentration of the n-type impurity in the low concentration regions 32A and 34A (1 × 10 18 cm − in this embodiment). 3 ) It is larger and smaller than the concentration of the n-type impurity in the high concentration region 36A, the source region 31A3 and the drain region 35A3 (in this embodiment, 5 × 10 20 cm −3 ). When the concentration of the n-type impurity in the intermediate concentration region 38A is in such a range, it is possible to prevent a crystal current in the intermediate concentration region 38A from increasing and a leakage current from flowing to the auxiliary capacitance Cs, and to achieve a desired electric capacity. Can keep you.
　結晶質半導体層３０Ａ３上にはゲート絶縁膜１６が形成され、ゲート絶縁膜１６上にはゲート電極１３Ａ３ａおよび１３Ａ３ｂが形成されている。さらに、ゲート電極１３Ａ３ａおよび１３Ａ３ｂを覆うように第１保護膜１８が形成され、第１保護膜１８上に第２保護膜２２が形成されている。さらに、ＴＦＴ１０Ａ３は、ソース領域３１Ａ３と電気的に接続するソース電極１５Ａ３を有する。さらに、ＴＦＴ１０Ａ３は、結晶質半導体層３０Ａ３のドレイン領域３５Ａ３を介して画素電極１９Ａ３と電気的に接続されている。ソース電極１５Ａ３および画素電極１９Ａ３は、第２保護膜２２上に形成されている。 A gate insulating film 16 is formed on the crystalline semiconductor layer 30A3, and gate electrodes 13A3a and 13A3b are formed on the gate insulating film 16. Further, a first protective film 18 is formed so as to cover the gate electrodes 13A3a and 13A3b, and a second protective film 22 is formed on the first protective film 18. Further, the TFT 10A3 has a source electrode 15A3 that is electrically connected to the source region 31A3. Further, the TFT 10A3 is electrically connected to the pixel electrode 19A3 via the drain region 35A3 of the crystalline semiconductor layer 30A3. The source electrode 15A3 and the pixel electrode 19A3 are formed on the second protective film 22.
　補助容量Ｃｓは、結晶質半導体層３０Ａ３の中濃度領域３８Ａと、補助容量電極１３Ａ３ｃとを有する。中濃度領域３８Ａ上にゲート絶縁膜１６が形成され、ゲート絶縁膜１６上に補助容量電極１３Ａ３ｃが形成されている。 The auxiliary capacitance Cs includes a medium concentration region 38A of the crystalline semiconductor layer 30A3 and an auxiliary capacitance electrode 13A3c. A gate insulating film 16 is formed on the intermediate concentration region 38A, and an auxiliary capacitance electrode 13A3c is formed on the gate insulating film 16.
　遮光層４Ａ１～４Ａ３は、例えばＣｒ（クロム）、Ｍｏ（モリブデン）またはＷ（タングステン）などの遮光性を有する金属から形成されている。遮光層４Ａ１～４Ａ３の厚さは、それぞれ、例えば、３０ｎｍ以上３００ｎｍ以下、より好ましくは５０ｎｍ以上２００ｎｍ以下である。 The light shielding layers 4A1 to 4A3 are made of a light-shielding metal such as Cr (chromium), Mo (molybdenum), or W (tungsten). The thickness of each of the light shielding layers 4A1 to 4A3 is, for example, not less than 30 nm and not more than 300 nm, more preferably not less than 50 nm and not more than 200 nm.
　ゲート電極１３Ａ１～１３Ａ３、ソース電極１５Ａ１～１５Ａ３、ドレイン電極１７Ａ１、１７Ａ２および補助容量電極１３Ａ３ｃは、例えば上層をＣｕ（銅）層とし、下層をＴｉ（チタン）層とする積層構造を有する。上層は、Ｃｕ層の代わりに、Ａｌ層であってもよい。ゲート電極１３Ａ１～１３Ａ３、ソース電極１５Ａ１～１５Ａ３、ドレイン電極１７Ａ１、１７Ａ２および補助容量電極１３Ａ３ｃのそれぞれの厚さは、例えば、ＣｕあるいはＡｌから形成された上層が１００ｎｍ～５００ｎｍ、Ｔｉから形成された下層が５０ｎｍ～２００ｎｍである。 The gate electrodes 13A1 to 13A3, the source electrodes 15A1 to 15A3, the drain electrodes 17A1 and 17A2, and the auxiliary capacitance electrode 13A3c have a laminated structure in which, for example, the upper layer is a Cu (copper) layer and the lower layer is a Ti (titanium) layer. The upper layer may be an Al layer instead of the Cu layer. The thicknesses of the gate electrodes 13A1 to 13A3, the source electrodes 15A1 to 15A3, the drain electrodes 17A1 and 17A2, and the auxiliary capacitance electrode 13A3c are, for example, an upper layer made of Cu or Al, and a lower layer made of Ti. Is 50 nm to 200 nm.
　画素電極１９Ａ３は、例えばＩＴＯ（Indium Tin Oxide）から形成されている。画素電極１９Ａ３の厚さは、例えば、５０ｎｍ～３００ｎｍである。 The pixel electrode 19A3 is made of, for example, ITO (Indium Tin Oxide). The thickness of the pixel electrode 19A3 is, for example, 50 nm to 300 nm.
　結晶質半導体層３０Ａ１～３０Ａ３は、例えば、多結晶シリコン層である。結晶質半導体層３０Ａ１～３０Ａ３の厚さは、例えば、３０ｎｍ～１００ｎｍである。 The crystalline semiconductor layers 30A1 to 30A3 are, for example, polycrystalline silicon layers. The thickness of the crystalline semiconductor layers 30A1 to 30A3 is, for example, 30 nm to 100 nm.
　第１下地絶縁膜１２は、例えば、ＳｉＮX（窒化シリコン）から形成されている。第１下地絶縁膜１２の厚さは、例えば、５０ｎｍ～２００ｎｍである。 The first base insulating film 12 is made of, for example, SiN x (silicon nitride). The thickness of the first base insulating film 12 is, for example, 50 nm to 200 nm.
　第２下地絶縁膜１４は、例えば、ＳｉＯ2（二酸化シリコン）から形成されている。第２下地絶縁膜１４の厚さは、例えば、５０ｎｍ～２００ｎｍである。 The second base insulating film 14 is made of, for example, SiO 2 (silicon dioxide). The thickness of the second base insulating film 14 is, for example, 50 nm to 200 nm.
　ゲート絶縁膜１６は、例えば、ＳｉＯ2から形成されている。ゲート絶縁膜１６の厚さは、例えば、３０ｎｍ～２００ｎｍである。 The gate insulating film 16 is made of, for example, SiO 2 . The thickness of the gate insulating film 16 is, for example, 30 nm to 200 nm.
　第１保護膜１８は、例えば、ＳｉＮXから形成されている。第１保護膜１８の厚さは、例えば、１００ｎｍ～５００ｎｍである。 The first protective film 18 is made of, for example, SiN x . The thickness of the first protective film 18 is, for example, 100 nm to 500 nm.
　第２保護膜２２は、例えば、ＳｉＯ2から形成されている。第２保護膜２２の厚さは、例えば、３００ｎｍ～１０００ｎｍである。 The second protective film 22 is made of, for example, SiO 2 . The thickness of the second protective film 22 is, for example, 300 nm to 1000 nm.
　図１に示すように、半導体装置１００Ａは、互いに特性が異なる複数のＴＦＴを有し、それぞれのＴＦＴに対応して遮光層４Ａ１～４Ａ３が形成されている。このような構造を有する半導体装置１００Ａは、後述するように、フォトマスクの数が増大しない半導体装置の製造方法によって製造される。さらに、半導体装置１００Ａは、例えば、バックライトからの光が、それぞれのＴＦＴの結晶質半導体層に当たらないような構造を有する。従って、半導体装置１００Ａによって、例えばバックライトからの光によりオフ電流が増大することを防ぐことができ、多種類のＴＦＴを同一基板上に形成する場合であっても、フォトマスクの数が増大しない製造方法で半導体装置１００Ａを製造し得る。さらに、半導体装置１００Ａが有するＴＦＴ１０Ａ３は、低濃度領域（Lightly Doped Drain、以下「ＬＤＤ領域」という場合もある）を有しているので、ＴＦＴ１０Ａ３のオフ電流を小さくでき、かつ長期信頼性も高めることができる。 As shown in FIG. 1, the semiconductor device 100A has a plurality of TFTs having different characteristics, and light shielding layers 4A1 to 4A3 are formed corresponding to the TFTs. The semiconductor device 100A having such a structure is manufactured by a method for manufacturing a semiconductor device in which the number of photomasks does not increase, as will be described later. Furthermore, the semiconductor device 100A has a structure in which, for example, light from the backlight does not strike the crystalline semiconductor layer of each TFT. Therefore, the semiconductor device 100A can prevent an increase in off current due to, for example, light from a backlight, and the number of photomasks does not increase even when many types of TFTs are formed on the same substrate. The semiconductor device 100A can be manufactured by the manufacturing method. Further, since the TFT 10A3 included in the semiconductor device 100A has a low concentration region (Lightly Doped Drain, sometimes referred to as “LDD region” hereinafter), the off-current of the TFT 10A3 can be reduced and long-term reliability can be improved. Can do.
　次に、図２および図３を参照しながら、半導体装置１００Ａの製造方法を説明する。 Next, a method for manufacturing the semiconductor device 100A will be described with reference to FIGS.
　図２（ａ）～図２（ｇ）および図３（ａ）～図３（ｃ）は、半導体装置１００Ａの製造方法を説明する断面図である。 2 (a) to 2 (g) and FIGS. 3 (a) to 3 (c) are cross-sectional views illustrating a method for manufacturing the semiconductor device 100A.
　図２（ａ）に示すように、絶縁基板（例えばガラス基板）１１上に、遮光層４Ａ１～４Ａ３をそれぞれ公知の方法で形成する。遮光層４Ａ１～４Ａ３は、例えばＣｒ（クロム）、Ｍｏ（モリブデン）またはＷ（タングステン）などの遮光性を有する金属から形成されている。遮光層４Ａ１～４Ａ３上に、例えばＳｉＮXを含有する第１下地絶縁膜１２を公知の方法で形成する。第１下地絶縁膜１２上に、例えばＳｉＯ2を含有する第２下地絶縁膜１４を公知の方法で形成する。第２下地絶縁膜１４上に非晶質半導体膜３０を公知の方法で形成する。非晶質半導体膜３０は、例えばアモルファスシリコン（ａ－Ｓｉ）膜である。 As shown in FIG. 2A, light shielding layers 4A1 to 4A3 are formed on an insulating substrate (for example, a glass substrate) 11 by a known method. The light shielding layers 4A1 to 4A3 are made of a light-shielding metal such as Cr (chromium), Mo (molybdenum), or W (tungsten). On the light shielding layers 4A1 to 4A3, for example, a first base insulating film 12 containing SiN x is formed by a known method. A second base insulating film 14 containing, for example, SiO 2 is formed on the first base insulating film 12 by a known method. An amorphous semiconductor film 30 is formed on the second base insulating film 14 by a known method. The amorphous semiconductor film 30 is, for example, an amorphous silicon (a-Si) film.
　次に、図２（ｂ）に示すように、非晶質半導体膜３０にレーザ光Ｌ１を照射する。このときのレーザ光Ｌ１は、例えば波長３０８ｎｍのＸｅＣｌ（塩化キセノン）エキシマレーザ光である。長尺のビーム光を走査して、絶縁基板１１の全面にレーザ光Ｌ１を照射する。これにより、非晶質半導体膜３０は結晶化され、結晶質半導体膜３０ａとなる。結晶質半導体膜３０ａは、例えば多結晶シリコン（ｐ－Ｓｉ）膜である。 Next, as shown in FIG. 2B, the amorphous semiconductor film 30 is irradiated with laser light L1. The laser light L1 at this time is, for example, XeCl (xenon chloride) excimer laser light having a wavelength of 308 nm. A long beam light is scanned to irradiate the entire surface of the insulating substrate 11 with the laser light L1. Thereby, the amorphous semiconductor film 30 is crystallized to become a crystalline semiconductor film 30a. The crystalline semiconductor film 30a is, for example, a polycrystalline silicon (p-Si) film.
　次に、図２（ｃ）に示すように、結晶質半導体膜３０ａを島状にパターニングして、後にｎ型ＴＦＴ１０Ａ１の活性領域となる結晶質半導体層３０Ａ１と、後にｐ型ＴＦＴ１０Ａ２の活性領域となる結晶質半導体層３０Ａ２と、後に画素用のＴＦＴの活性領域および補助容量Ｃｓの電極（下部電極）となる結晶質半導体層３０Ａ３を形成する。結晶質半導体層３０Ａ３の内、遮光層４Ａ３と重なる領域は、後に画素用のＴＦＴ１０Ａ３の活性領域となる領域である。結晶質半導体層３０Ａ３の内、後に補助容量Ｃｓの補助容量電極１３Ａｃ３となる領域は、遮光層４Ａ３とは重ならない。 Next, as shown in FIG. 2C, the crystalline semiconductor film 30a is patterned into an island shape, and the crystalline semiconductor layer 30A1 that later becomes the active region of the n-type TFT 10A1, and the active region of the p-type TFT 10A2 later. A crystalline semiconductor layer 30A3 to be formed, and an active region of the pixel TFT and an electrode (lower electrode) of the auxiliary capacitor Cs later are formed. Of the crystalline semiconductor layer 30A3, a region overlapping with the light shielding layer 4A3 is a region that later becomes an active region of the pixel TFT 10A3. Of the crystalline semiconductor layer 30A3, a region that will later become the auxiliary capacitance electrode 13Ac3 of the auxiliary capacitance Cs does not overlap the light shielding layer 4A3.
　次に、図２（ｄ）に示すように、結晶質半導体層３０Ａ１～３０Ａ３を覆うようにゲート絶縁膜１６を絶縁基板１１の全面に、公知の方法で形成する。 Next, as shown in FIG. 2D, a gate insulating film 16 is formed on the entire surface of the insulating substrate 11 by a known method so as to cover the crystalline semiconductor layers 30A1 to 30A3.
　次に、ゲート絶縁膜１６上にポジ型のフォトレジスト７１を全面に形成する。 Next, a positive photoresist 71 is formed on the entire surface of the gate insulating film 16.
　次に、図２（ｅ）に示すように、それぞれの遮光層４Ａ１～４Ａ３をマスクとして、ガラス基板１１の裏面より露光する（背面露光）。このとき、フォトマスクを用いない。従って、フォトマスクの数を削減し、製造コストを削減し得る。 Next, as shown in FIG. 2E, exposure is performed from the back surface of the glass substrate 11 using the respective light shielding layers 4A1 to 4A3 as masks (back surface exposure). At this time, a photomask is not used. Therefore, the number of photomasks can be reduced and the manufacturing cost can be reduced.
　次に、図２（ｆ）に示すように、背面露光の結果、遮光層４Ａ１～４Ａ３がマスクとして機能するので、遮光層４Ａ１～４Ａ３と重なるようにポジ型のフォトレジスト７１Ａ１～７１Ａ３が形成される。それ以外の部分は、遮光層４Ａ１～４Ａ３がないので、現像により除去される。 Next, as shown in FIG. 2F, as a result of the back exposure, the light shielding layers 4A1 to 4A3 function as a mask, so that positive photoresists 71A1 to 71A3 are formed so as to overlap the light shielding layers 4A1 to 4A3. The The other portions are removed by development because they do not have the light shielding layers 4A1 to 4A3.
　次に、図２（ｇ）に示すように、結晶質半導体層３０Ａ３の一部にｎ型不純物（例えば、リン（Ｐ））ｎ１をドーピングし、中濃度領域３８Ａを形成する。ｎ型不純物ｎ１をドーピングする条件は、例えば、ドーピングガスとしてＰＨ3（フォスフィン）を用い、加速電圧６０ｋＶ以上９０ｋＶ以下で、ドーズ量１×１０14ｃｍ-2以上１×１０16ｃｍ-2以下（本実施形態において、加速電圧７０ｋＶ、ドーズ量１×１０15ｃｍ-2）が好ましい。結晶質半導体層３０Ａ１および３０Ａ２、ならびに、結晶質半導体層３０Ａ３の内、中濃度領域３８Ａ以外の領域にはｎ型不純物ｎ１は注入されない。中濃度領域３８Ａは、補助容量Ｃｓの電極となる領域である。 Next, as shown in FIG. 2G, an n-type impurity (for example, phosphorus (P)) n1 is doped into part of the crystalline semiconductor layer 30A3 to form an intermediate concentration region 38A. Conditions for doping the n-type impurity n1 include, for example, using PH 3 (phosphine) as a doping gas, an acceleration voltage of 60 kV to 90 kV, and a dose of 1 × 10 14 cm −2 to 1 × 10 16 cm −2 ( In this embodiment, an acceleration voltage of 70 kV and a dose of 1 × 10 15 cm −2 are preferable. Of the crystalline semiconductor layers 30A1 and 30A2 and the crystalline semiconductor layer 30A3, the n-type impurity n1 is not implanted into regions other than the medium concentration region 38A. The medium concentration region 38A is a region that becomes an electrode of the auxiliary capacitor Cs.
　次に、図３（ａ）に示すように、公知の方法で、ポジ型のフォトレジスト７１Ａ１～７１Ａ３を除去する。次に、ゲート絶縁膜１６上に、公知の方法で、ゲート電極１３Ａ１～１３Ａ３と、補助容量電極１３Ａ３ｃとを形成する。その後、ゲート電極１３Ａ１～１３Ａ３および補助容量電極１３Ａ３ｃをマスクとして、ｎ型不純物（例えば、リン（Ｐ））ｎ２をドーピングする。ｎ型不純物をドーピングする条件は、例えば、ドーピングガスとしてＰＨ3（フォスフィン）を用い、加速電圧６０ｋＶ以上９０ｋＶ以下の範囲で、ドーズ量１×１０12ｃｍ-2以上１×１０14ｃｍ-2以下（本実施形態において、加速電圧７０ｋＶ、ドーズ量２×１０13ｃｍ-2）が好ましい。その結果、それぞれの結晶質半導体層３０Ａ１～３０Ａ３に、チャネル領域３３Ａ１～３３Ａ３が形成される。それぞれのチャネル領域３３Ａ１～３３Ａ３は、ゲート電極１３Ａ１～１３Ａ３に対して、自己整合的に形成される。それぞれの結晶質半導体層３０Ａ１～３０Ａ３の内、ゲート電極１３Ａ１～１３Ａ３および補助容量電極１３Ａ３ｃで覆われていない領域は、ｎ型不純物ｎ２を含有する。チャネル領域３３Ａ１～３３Ａ３は、ｎ型不純物ｎ２を含有しない。 Next, as shown in FIG. 3A, the positive photoresists 71A1 to 71A3 are removed by a known method. Next, the gate electrodes 13A1 to 13A3 and the auxiliary capacitance electrode 13A3c are formed on the gate insulating film 16 by a known method. Thereafter, n-type impurities (for example, phosphorus (P)) n2 are doped using the gate electrodes 13A1 to 13A3 and the auxiliary capacitance electrode 13A3c as a mask. The conditions for doping the n-type impurity are, for example, using PH 3 (phosphine) as a doping gas, and a dose amount of 1 × 10 12 cm −2 to 1 × 10 14 cm −2 in a range of acceleration voltage of 60 kV to 90 kV. (In this embodiment, an acceleration voltage of 70 kV and a dose of 2 × 10 13 cm −2 ) are preferable. As a result, channel regions 33A1 to 33A3 are formed in the respective crystalline semiconductor layers 30A1 to 30A3. The channel regions 33A1 to 33A3 are formed in a self-aligned manner with respect to the gate electrodes 13A1 to 13A3. Of the respective crystalline semiconductor layers 30A1 to 30A3, regions not covered with the gate electrodes 13A1 to 13A3 and the auxiliary capacitance electrode 13A3c contain the n-type impurity n2. Channel regions 33A1 to 33A3 do not contain n-type impurity n2.
　次に、図３（ｂ）に示すように、結晶質半導体層３０Ａ２を覆うようにポジ型のフォトレジスト７２ａを形成する。さらに、ゲート電極１３Ａ３ａおよび１３Ａ３ｂと画素用のＴＦＴのＬＤＤ領域となる領域を覆うようにポジ型のフォトレジスト７２ｂおよび７２ｃを、公知の方法で形成する。 Next, as shown in FIG. 3B, a positive photoresist 72a is formed so as to cover the crystalline semiconductor layer 30A2. Further, positive photoresists 72b and 72c are formed by a known method so as to cover the gate electrodes 13A3a and 13A3b and the region to be the LDD region of the pixel TFT.
　次に、結晶質半導体層３０Ａ１および３０Ａ３に、ｎ型不純物ｎ３をドーピングする。ｎ型不純物ｎ３をドーピングする条件は、例えば、ドーピングガスとしてＰＨ3（フォスフィン）を用い、加速電圧６０ｋＶ以上９０ｋＶ以下で、ドーズ量１×１０15ｃｍ-2以上１×１０16ｃｍ-2以下（本実施形態において、加速電圧７０ｋＶ、ドーズ量５×１０15ｃｍ-2）が好ましい。結晶質半導体層３０Ａ１および３０Ａ３の内、ポジ型のフォトレジスト７２ａ～７２ｃで覆われていない領域にｎ型不純物ｎ３がドーピングされる。その結果、結晶質半導体層３０Ａ１にソース領域３１Ａ１とドレイン領域３５Ａ１とが形成される。また、結晶質半導体層３０Ａ３にソース領域３１Ａ３とドレイン領域３５Ａ３と高濃度領域３６Ａ３とが形成される。結晶質半導体層３０Ａ２には、ｎ型不純物ｎ３がドーピングされない。また、結晶質半導体層３０Ａ３の内、ポジ型のフォトレジスト７２ｂおよび７２ｃ、ならびに、補助容量電極１３Ａ３ｃで覆われ、かつ、チャネル領域３３Ａ３ａおよび３３Ａ３ｂ以外の領域にＬＤＤ領域３２Ａ、３４Ａが形成される。 Next, the crystalline semiconductor layers 30A1 and 30A3 are doped with an n-type impurity n3. The conditions for doping the n-type impurity n3 are, for example, using PH 3 (phosphine) as a doping gas, an acceleration voltage of 60 kV to 90 kV, and a dose of 1 × 10 15 cm −2 to 1 × 10 16 cm −2 ( In the present embodiment, an acceleration voltage of 70 kV and a dose of 5 × 10 15 cm −2 are preferable. Of the crystalline semiconductor layers 30A1 and 30A3, an n-type impurity n3 is doped in a region not covered with the positive photoresists 72a to 72c. As a result, a source region 31A1 and a drain region 35A1 are formed in the crystalline semiconductor layer 30A1. Further, a source region 31A3, a drain region 35A3, and a high concentration region 36A3 are formed in the crystalline semiconductor layer 30A3. The crystalline semiconductor layer 30A2 is not doped with the n-type impurity n3. In addition, LDD regions 32A and 34A are formed in regions other than the channel regions 33A3a and 33A3b, which are covered with the positive photoresists 72b and 72c and the auxiliary capacitance electrode 13A3c in the crystalline semiconductor layer 30A3.
　次に、図３（ｃ）に示すように、ポジ型のフォトレジスト７２ａ～７２ｃを公知の方法で除去する。その後、ポジ型のフォトレジスト７３ａおよび７３ｂを公知の方法で形成する。ポジ型のフォトレジスト７３ａは、結晶質半導体層３０Ａ１を覆うように形成され、ポジ型のフォトレジスト７３ｂは、結晶質半導体層３０Ａ３を覆うように形成される。 Next, as shown in FIG. 3C, the positive photoresists 72a to 72c are removed by a known method. Thereafter, positive photoresists 73a and 73b are formed by a known method. The positive photoresist 73a is formed so as to cover the crystalline semiconductor layer 30A1, and the positive photoresist 73b is formed so as to cover the crystalline semiconductor layer 30A3.
　次に、高濃度のｐ型不純物（例えば、ボロン（Ｂ））ｐ１を結晶質半導体層３０Ａ２にドーピングする。ｐ型不純物ｐ１をドーピングする条件は、例えば、ドーピングガスとして、ジボラン（Ｂ2Ｈ6）を用い、加速電圧４０ｋＶ以上９０ｋＶ以下で、ドーズ量１×１０15ｃｍ-2以上１×１０16ｃｍ-2以下（本実施形態において、加速電圧７５ｋＶ、ドーズ量３×１０15ｃｍ-2）が好ましい。その結果、結晶質半導体層３０Ａ２にソース領域３１Ａ２およびドレイン領域３５Ａ２が形成される。また、結晶質半導体層３０Ａ１および３０Ａ３に、ｐ型不純物はドーピングされない。 Next, the crystalline semiconductor layer 30A2 is doped with a high-concentration p-type impurity (for example, boron (B)) p1. The conditions for doping the p-type impurity p1 are, for example, using diborane (B 2 H 6 ) as a doping gas, an acceleration voltage of 40 kV to 90 kV, and a dose of 1 × 10 15 cm −2 to 1 × 10 16 cm −. 2 or less (accelerating voltage 75 kV, dose amount 3 × 10 15 cm −2 in this embodiment) is preferable. As a result, the source region 31A2 and the drain region 35A2 are formed in the crystalline semiconductor layer 30A2. The crystalline semiconductor layers 30A1 and 30A3 are not doped with p-type impurities.
　次に、ポジ型のフォトレジストレジスト７３ａおよび７３ｂを、公知の方法で除去する。 Next, the positive photoresist resists 73a and 73b are removed by a known method.
　次に、熱処理を行い、上述のｎ型およびｐ型不純物を活性化させる。その後、図１（ａ）に示すように、ゲート電極１３Ａ１～１３Ａ３上に、ＳｉＮXを含有する第１保護膜１８を公知の方法で形成する。次に、第１保護膜１８上に、ＳｉＯ2を含有する第２保護膜２２を公知の方法で形成する。なお、この後、水素化のための熱処理を行ってもよい。 Next, heat treatment is performed to activate the n-type and p-type impurities described above. Thereafter, as shown in FIG. 1A, a first protective film 18 containing SiN x is formed on the gate electrodes 13A1 to 13A3 by a known method. Next, a second protective film 22 containing SiO 2 is formed on the first protective film 18 by a known method. After that, heat treatment for hydrogenation may be performed.
　次に、第１および第２保護膜１８および２２、ならびに、ゲート絶縁膜１６にコンタクトホールを公知の方法で形成する。その後、第２保護膜１８上にソース電極１５Ａ１～１５Ａ３、ドレイン電極１７Ａ１、１７Ａ２および画素電極１９Ａ３を公知の方法で形成する。ソース電極１５Ａ１～１５Ａ３は、それぞれの結晶質半導体層のソース領域と電気的に接続される。ドレイン電極１７Ａ１および１７Ａ２、ならびに、画素電極１９Ａ３は、それぞれの結晶質半導体層のドレイン領域と電気的に接続される。また。ゲート電極１３Ａ１および１３Ａ２上の第１および第２保護膜１８および２２にもコンタクトホールを形成し、ソース電極１５Ａ１および１５Ａ２（または、ドレイン電極１７Ａ１および１７Ａ２）とゲート電極１３Ａ１および１３Ａ２とを電気的に接続してもよい。その後、ソース電極１５Ａ１～１５Ａ３（または、ドレイン電極１７Ａ１および１７Ａ２）上に、さらなる保護膜を形成してもよい。 Next, contact holes are formed in the first and second protective films 18 and 22 and the gate insulating film 16 by a known method. Thereafter, source electrodes 15A1 to 15A3, drain electrodes 17A1 and 17A2, and a pixel electrode 19A3 are formed on the second protective film 18 by a known method. Source electrodes 15A1 to 15A3 are electrically connected to the source regions of the respective crystalline semiconductor layers. The drain electrodes 17A1 and 17A2 and the pixel electrode 19A3 are electrically connected to the drain regions of the respective crystalline semiconductor layers. Also. Contact holes are also formed in the first and second protective films 18 and 22 on the gate electrodes 13A1 and 13A2, and the source electrodes 15A1 and 15A2 (or the drain electrodes 17A1 and 17A2) and the gate electrodes 13A1 and 13A2 are electrically connected. You may connect. Thereafter, a further protective film may be formed on the source electrodes 15A1 to 15A3 (or the drain electrodes 17A1 and 17A2).
　次に、半導体装置１００Ａと同じ効果を有する本発明による他の実施形態における半導体装置１００Ｂ～１００Ｄを説明する。なお、半導体装置１００Ａと共通する構成要素は同じ参照符号を付し、説明の重複を避ける。 Next, semiconductor devices 100B to 100D according to other embodiments of the present invention having the same effect as the semiconductor device 100A will be described. Note that components common to the semiconductor device 100A are denoted by the same reference numerals to avoid duplicate description.
　図４は、半導体装置１００Ｂの模式的な断面図である。なお、半導体装置１００Ｂは、図示していないが、半導体装置１００Ａが有する画素用のＴＦＴ１０Ａ３と同じ画素用のＴＦＴを有している。 FIG. 4 is a schematic cross-sectional view of the semiconductor device 100B. Although not shown, the semiconductor device 100B includes the same pixel TFT as the pixel TFT 10A3 included in the semiconductor device 100A.
　図４に示す半導体装置１００Ｂは、半導体装置１００Ａの遮光層４Ａ２および４Ａ３を形成せず、さらに、ＴＦＴ１０Ａ１の結晶質半導体層３０Ａ１のチャネル領域３３Ａ１に、低濃度のｐ型不純物を含有している半導体装置である。 The semiconductor device 100B shown in FIG. 4 does not form the light shielding layers 4A2 and 4A3 of the semiconductor device 100A, and further includes a semiconductor containing a low concentration p-type impurity in the channel region 33A1 of the crystalline semiconductor layer 30A1 of the TFT 10A1. Device.
　チャネル領域３３Ａ１のｐ型不純物の濃度は、例えば１×１０16ｃｍ-3以上５×１０17ｃｍ-3以下（本実施形態において、５×１０16ｃｍ-3）が好ましい。 The concentration of the p-type impurity in the channel region 33A1 is preferably, for example, from 1 × 10 16 cm −3 to 5 × 10 17 cm −3 (in this embodiment, 5 × 10 16 cm −3 ).
　次に、図５および図６を参照しながら半導体装置１００Ｂの製造方法について説明する。図５（ａ）～図５（ｃ）および図６（ａ）～図６（ｃ）は、半導体装置１００Ｂの製造方法を説明する断面図である。なお、半導体装置１００Ｂの内、画素用のＴＦＴ１０Ａ３に係る部分の製造方法についての説明は、省略する。 Next, a method for manufacturing the semiconductor device 100B will be described with reference to FIGS. 5 (a) to 5 (c) and FIGS. 6 (a) to 6 (c) are cross-sectional views illustrating a method for manufacturing the semiconductor device 100B. Note that a description of a method for manufacturing a portion related to the pixel TFT 10A3 in the semiconductor device 100B is omitted.
　図５（ａ）に示すように、上述した方法で、絶縁基板１１上に、遮光層４Ａ１、第１および第２下地絶縁膜１２および１４、島状の結晶質半導体層３０Ａ１および３０Ａ２、ゲート絶縁膜１６を形成する。このとき、上述の遮光層４Ａ２および４Ａ３は、形成されない。また、ゲート絶縁膜１６を形成した後、ｐ型不純物（例えばボロン（Ｂ））をそれぞれの結晶質半導体層の全面にドーピングしてもよい。 As shown in FIG. 5A, the light shielding layer 4A1, the first and second base insulating films 12 and 14, the island-shaped crystalline semiconductor layers 30A1 and 30A2, the gate insulation are formed on the insulating substrate 11 by the method described above. A film 16 is formed. At this time, the above-described light shielding layers 4A2 and 4A3 are not formed. Further, after forming the gate insulating film 16, a p-type impurity (for example, boron (B)) may be doped on the entire surface of each crystalline semiconductor layer.
　次に、ネガ型のフォトレジスト７４’を絶縁基板１１の全面に公知の方法で形成する。 Next, a negative photoresist 74 ′ is formed on the entire surface of the insulating substrate 11 by a known method.
　次に、図５（ｂ）に示すように、遮光層４Ａ１をマスクとして、絶縁基板１１の裏面から露光する（背面露光）。このとき、フォトマスクを用いない。その結果、遮光層４Ａ１をマスクとしているので、遮光層４Ａ１に対応して、ネガ型のフォトレジスト７４がパターニングされる。結晶質半導体層３０Ａ１は、ネガ型のフォトレジスト７４に覆われていない。 Next, as shown in FIG. 5B, exposure is performed from the back surface of the insulating substrate 11 using the light shielding layer 4A1 as a mask (back surface exposure). At this time, a photomask is not used. As a result, since the light shielding layer 4A1 is used as a mask, the negative photoresist 74 is patterned corresponding to the light shielding layer 4A1. The crystalline semiconductor layer 30A1 is not covered with the negative photoresist 74.
　次に、図５（ｃ）に示すように、ネガ型のフォトレジスト７４をマスクとして、ｐ型不純物ｐ２を結晶質半導体層３０Ａ１にドーピングする。ｐ型不純物ｐ２をドーピングする条件は、例えば、ドーピングガスとして、ジボラン（Ｂ2Ｈ6）を用い、加速電圧４０ｋＶ以上９０ｋＶ以下で、ドーズ量１×１０11ｃｍ-2以上１×１０12ｃｍ-2以下（本実施形態において、加速電圧７５ｋＶ、ドーズ量３×１０11ｃｍ-2）が好ましい。ネガ型のフォトレジスト７４で覆われた結晶質半導体層３０Ａ２にはｐ型不純物ｐ２はドーピングされない。 Next, as shown in FIG. 5C, the crystalline semiconductor layer 30A1 is doped with the p-type impurity p2 using the negative photoresist 74 as a mask. Conditions for doping the p-type impurity p2 include, for example, diborane (B 2 H 6 ) as a doping gas, an acceleration voltage of 40 kV to 90 kV, and a dose of 1 × 10 11 cm −2 to 1 × 10 12 cm −. 2 or less (accelerating voltage 75 kV, dose amount 3 × 10 11 cm −2 in this embodiment) is preferable. The crystalline semiconductor layer 30A2 covered with the negative photoresist 74 is not doped with the p-type impurity p2.
　次に、図６（ａ）に示すように、結晶質半導体層３０Ａ１および３０Ａ２上にゲート電極１３Ａ１および１３Ａ２をそれぞれ公知の方法で形成する。 Next, as shown in FIG. 6A, gate electrodes 13A1 and 13A2 are respectively formed on the crystalline semiconductor layers 30A1 and 30A2 by a known method.
　次に、図６（ｂ）に示すように、結晶質半導体層３０Ａ１を覆うようにポジ型のフォトレジスト７５を形成する。その後、ポジ型のフォトレジスト７５およびゲート電極１３Ａ２をマスクとして、ｐ型不純物ｐ１をドーピングする。ｐ型不純物ｐ１をドーピングする条件は、例えば、ドーピングガスとして、ジボラン（Ｂ2Ｈ6）を用い、加速電圧４０ｋＶ以上９０ｋＶ以下で、ドーズ量１×１０15ｃｍ-2以上１×１０16ｃｍ-2以下（本実施形態において、加速電圧７５ｋＶ、ドーズ量３×１０15ｃｍ-2）が好ましい。このとき、結晶質半導体層３０Ａ２に、ソース領域３１Ａ２およびドレイン領域３５Ａ２が形成され、ｐ型不純物ｐ１がドーピングされていない領域にチャネル領域３３Ａ２が形成される。チャネル領域３３Ａ２は、ゲート電極１３Ａ２に対して自己整合的に形成される。チャネル領域３３Ａ２は、ソース領域３１Ａ２とドレイン領域３５Ａ２との間に形成される。 Next, as shown in FIG. 6B, a positive photoresist 75 is formed so as to cover the crystalline semiconductor layer 30A1. Thereafter, p-type impurity p1 is doped using positive photoresist 75 and gate electrode 13A2 as a mask. The conditions for doping the p-type impurity p1 are, for example, using diborane (B 2 H 6 ) as a doping gas, an acceleration voltage of 40 kV to 90 kV, and a dose of 1 × 10 15 cm −2 to 1 × 10 16 cm −. 2 or less (accelerating voltage 75 kV, dose amount 3 × 10 15 cm −2 in this embodiment) is preferable. At this time, the source region 31A2 and the drain region 35A2 are formed in the crystalline semiconductor layer 30A2, and the channel region 33A2 is formed in a region where the p-type impurity p1 is not doped. The channel region 33A2 is formed in a self-aligned manner with respect to the gate electrode 13A2. The channel region 33A2 is formed between the source region 31A2 and the drain region 35A2.
　次に、図６（ｃ）に示すように、ポジ型のフォトレジスト７５を公知の方法で除去し、結晶質半導体層３０Ａ２を覆うようにポジ型のフォトレジスト７６を公知の方法で形成する。 Next, as shown in FIG. 6C, the positive photoresist 75 is removed by a known method, and a positive photoresist 76 is formed by a known method so as to cover the crystalline semiconductor layer 30A2.
　次に、ポジ型のフォトレジスト７６とゲート電極１３Ａ１とをマスクとして、ｎ型不純物ｎ３を結晶質半導体層３０Ａ１にドーピングする。ｎ型不純物ｎ３をドーピングする条件は、例えば、ドーピングガスとしてＰＨ3を用い、加速電圧６０ｋＶ以上９０ｋＶ以下で、ドーズ量１×１０15ｃｍ-2以上１×１０16ｃｍ-2以下（本実施形態において、加速電圧７０ｋＶ、ドーズ量５×１０15ｃｍ-2）が好ましい。結晶質半導体層３０Ａ１に、ソース領域３１Ａ１およびドレイン領域３５Ａ１が形成され、ｎ型不純物ｎ３がドーピングされていない領域にチャネル領域３３Ａ１が形成される。チャネル領域３３Ａ１は、ゲート電極１３Ａ１に対して自己整合的に形成され、ソース領域３１Ａ１とドレイン領域３５Ａ１との間に形成される。 Next, the n-type impurity n3 is doped into the crystalline semiconductor layer 30A1 using the positive photoresist 76 and the gate electrode 13A1 as a mask. The conditions for doping the n-type impurity n3 include, for example, PH 3 as a doping gas, an acceleration voltage of 60 kV to 90 kV, and a dose of 1 × 10 15 cm −2 to 1 × 10 16 cm −2 (this embodiment) In this case, an acceleration voltage of 70 kV and a dose of 5 × 10 15 cm −2 are preferable. A source region 31A1 and a drain region 35A1 are formed in the crystalline semiconductor layer 30A1, and a channel region 33A1 is formed in a region where the n-type impurity n3 is not doped. The channel region 33A1 is formed in a self-aligned manner with respect to the gate electrode 13A1, and is formed between the source region 31A1 and the drain region 35A1.
　次に、ポジ型のフォトレジスト７６を公知の方法で除去し、上述したように熱処理を行う。 Next, the positive photoresist 76 is removed by a known method, and heat treatment is performed as described above.
　次に、上述したように、第１保護膜１８、第２保護膜２２、ソース電極１５Ａ１および１５Ａ２、ドレイン電極１７Ａ１および１７Ａ２、ならびに、画素電極を形成し、図４に示した半導体装置１００Ｂが製造される。 Next, as described above, the first protective film 18, the second protective film 22, the source electrodes 15A1 and 15A2, the drain electrodes 17A1 and 17A2, and the pixel electrode are formed, and the semiconductor device 100B shown in FIG. 4 is manufactured. Is done.
　次に、本発明によるさらに他の実施形態における半導体装置１００Ｃを説明する。なお、半導体装置１００Ｃの構造は、半導体装置１００Ｂの構造と同じであるので、半導体装置１００Ｃの断面図は省略している。 Next, a semiconductor device 100C according to still another embodiment of the present invention will be described. Note that since the structure of the semiconductor device 100C is the same as that of the semiconductor device 100B, a cross-sectional view of the semiconductor device 100C is omitted.
　半導体装置１００Ｃは、半導体装置１００Ｂのすべての結晶質半導体層３０Ａ１～３０Ａ３のチャネル領域３３Ａ１～３３Ａ３に、ｐ型不純物が含有されていない半導体装置である。 The semiconductor device 100C is a semiconductor device in which p-type impurities are not contained in the channel regions 33A1 to 33A3 of all the crystalline semiconductor layers 30A1 to 30A3 of the semiconductor device 100B.
　次に、図７を参照しながら半導体装置１００Ｃの製造方法を説明する。図７（ａ）～図７（ｅ）は、半導体装置１００Ｃの製造方法を説明する断面図である。また、半導体装置１００Ｃも半導体装置１００Ｂと同様に、画素用のＴＦＴ１０Ａ３の製造方法は省略する。 Next, a method for manufacturing the semiconductor device 100C will be described with reference to FIG. 7A to 7E are cross-sectional views illustrating a method for manufacturing the semiconductor device 100C. Similarly to the semiconductor device 100B, the manufacturing method of the pixel TFT 10A3 is also omitted in the semiconductor device 100C.
　上述した方法で、絶縁基板１１上に、遮光層４Ａ１、第１および第２下地絶縁膜１２および１４、島状の結晶質半導体層３０Ａ１および３０Ａ２、ならびに、ゲート絶縁膜１６を形成する。このとき、上述の遮光層４Ａ２および４Ａ３は、形成されない。また、ゲート絶縁膜１６を形成した後、ｐ型不純物（例えばボロン（Ｂ））をそれぞれの結晶質半導体層３０Ａ１～３０Ａ３の全面にドーピングしてもよい。 The light shielding layer 4A1, the first and second base insulating films 12 and 14, the island-shaped crystalline semiconductor layers 30A1 and 30A2, and the gate insulating film 16 are formed on the insulating substrate 11 by the method described above. At this time, the above-described light shielding layers 4A2 and 4A3 are not formed. Further, after forming the gate insulating film 16, a p-type impurity (for example, boron (B)) may be doped on the entire surface of each of the crystalline semiconductor layers 30A1 to 30A3.
　次に、図７（ａ）に示すように、結晶質半導体層３０Ａ１および結晶質半導体層３０Ａ２上に、ゲート電極１３Ａ１および１３Ａ２を公知の方法で形成する。ゲート電極１３Ａ１および１３Ａ２はそれぞれ、ゲート絶縁膜１６上に形成される。 Next, as shown in FIG. 7A, gate electrodes 13A1 and 13A2 are formed on the crystalline semiconductor layer 30A1 and the crystalline semiconductor layer 30A2 by a known method. Gate electrodes 13A1 and 13A2 are formed on gate insulating film 16, respectively.
　次に、図７（ｂ）に示すように、絶縁基板１１の全面に、ポジ型のフォトレジスト７７を公知の方法で形成する。その後、遮光層４Ａ１およびゲート電極１３Ａ２をマスクとして、絶縁基板１１の裏面から露光する（背面露光）。このとき、フォトマスクを用いない。 Next, as shown in FIG. 7B, a positive photoresist 77 is formed on the entire surface of the insulating substrate 11 by a known method. Thereafter, exposure is performed from the back surface of the insulating substrate 11 using the light shielding layer 4A1 and the gate electrode 13A2 as a mask (back surface exposure). At this time, a photomask is not used.
　次に、図７（ｃ）に示すように、背面露光の結果、遮光層４Ａ１およびゲート電極１３Ａ２をマスクとしているので、遮光層４Ａ１およびゲート電極１３Ａ２に対応して、ポジ型のフォトレジスト７７がパターニングされる。結晶質半導体層３０Ａ１は、ポジ型のフォトレジスト７７ａに覆われ、ゲート電極１３Ａ２上にポジ型のフォトレジスト７７ｂが形成されるようにパターニングされる。このとき、結晶質半導体層３０Ａ２のソース領域およびドレイン領域となる領域は、ポジ型のフォトレジスト７７ｂで覆われていない。 Next, as shown in FIG. 7C, as a result of the back exposure, the light shielding layer 4A1 and the gate electrode 13A2 are used as a mask, so that a positive photoresist 77 corresponding to the light shielding layer 4A1 and the gate electrode 13A2 is formed. Patterned. The crystalline semiconductor layer 30A1 is covered with a positive photoresist 77a, and is patterned so that a positive photoresist 77b is formed on the gate electrode 13A2. At this time, the regions to be the source region and the drain region of the crystalline semiconductor layer 30A2 are not covered with the positive photoresist 77b.
　次に、図７（ｄ）に示すように、ポジ型のフォトレジスト７７ａおよび７７ｂをマスクとして、ｐ型不純物ｐ１を結晶質半導体層３０Ａ２にドーピングする。ｐ型不純物ｐ１をドーピングする条件は、例えば、ドーピングガスとしてＰＨ3（フォスフィン）を用い、加速電圧４０ｋＶ以上９０ｋＶ以下で、ドーズ量１×１０15ｃｍ-2以上１×１０16ｃｍ-2以下（本実施形態において、加速電圧７５ｋＶ、ドーズ量３×１０15ｃｍ-2）が好ましい。結晶質半導体層３０Ａ１はポジ型のフォトレジスト７７ａに覆われているので、ｐ型不純物ｐ１が、結晶質半導体層３０Ａ１にドーピングされない。また、結晶質半導体層３０Ａ２の内、ゲート電極１３Ａ２に覆われている領域には、ｐ型不純物ｐ１が、ドーピングされない。その結果、結晶質半導体層３０Ａ２に、ソース領域３１Ａ２およびドレイン領域３５Ａ２が形成される。また、ソース領域３１Ａ２とドレイン領域３５Ａ２との間にチャネル領域３３Ａ２が形成される。チャネル領域３３Ａ２は、ゲート電極１３Ａ２に対して自己整合的に形成される。 Next, as shown in FIG. 7D, the crystalline semiconductor layer 30A2 is doped with a p-type impurity p1 using the positive photoresists 77a and 77b as a mask. The conditions for doping the p-type impurity p1 are, for example, PH 3 (phosphine) as a doping gas, an acceleration voltage of 40 kV to 90 kV, and a dose of 1 × 10 15 cm −2 to 1 × 10 16 cm −2 ( In this embodiment, an acceleration voltage of 75 kV and a dose amount of 3 × 10 15 cm −2 are preferable. Since the crystalline semiconductor layer 30A1 is covered with the positive photoresist 77a, the p-type impurity p1 is not doped into the crystalline semiconductor layer 30A1. Further, the region covered with the gate electrode 13A2 in the crystalline semiconductor layer 30A2 is not doped with the p-type impurity p1. As a result, the source region 31A2 and the drain region 35A2 are formed in the crystalline semiconductor layer 30A2. A channel region 33A2 is formed between the source region 31A2 and the drain region 35A2. The channel region 33A2 is formed in a self-aligned manner with respect to the gate electrode 13A2.
　次に、ポジ型のフォトレジスト７７ａおよび７７ｂを公知の方法で除去する。 Next, the positive photoresists 77a and 77b are removed by a known method.
　次に、図７（ｅ）に示すように、結晶質半導体層３０Ａ２を覆うようにポジ型のフォトレジスト７８を形成する。 Next, as shown in FIG. 7E, a positive photoresist 78 is formed so as to cover the crystalline semiconductor layer 30A2.
　次に、ポジ型のフォトレジスト７８をマスクとして、結晶質半導体層３０Ａ１にｎ型不純物ｎ３をドーピングする。ｎ型不純物ｎ３をドーピングする条件は、例えば、ドーピングガスとしてＰＨ3を用い、加速電圧６０ｋＶ以上９０ｋＶ以下で、ドーズ量１×１０15ｃｍ-2以上１×１０16ｃｍ-2以下（本実施形態において、加速電圧７０ｋＶ、ドーズ量５×１０15ｃｍ-2）が好ましい。その結果、結晶質半導体層３０Ａ１にソース領域３１Ａ１およびドレイン領域３５Ａ１が形成される。また、ソース領域３１Ａ１とドレイン領域３５Ａ１との間にチャネル領域３３Ａ１が形成される。チャネル領域３３Ａ１は、ゲート電極１３Ａ１に対して自己整合的に形成される。 Next, using the positive photoresist 78 as a mask, the crystalline semiconductor layer 30A1 is doped with an n-type impurity n3. The conditions for doping the n-type impurity n3 include, for example, PH 3 as a doping gas, an acceleration voltage of 60 kV to 90 kV, and a dose of 1 × 10 15 cm −2 to 1 × 10 16 cm −2 (this embodiment) In this case, an acceleration voltage of 70 kV and a dose of 5 × 10 15 cm −2 are preferable. As a result, the source region 31A1 and the drain region 35A1 are formed in the crystalline semiconductor layer 30A1. A channel region 33A1 is formed between the source region 31A1 and the drain region 35A1. The channel region 33A1 is formed in a self-aligned manner with respect to the gate electrode 13A1.
　次に、ポジ型のフォトレジスト７８を公知の方法で除去し、上述したように熱処理を行う。 Next, the positive photoresist 78 is removed by a known method, and heat treatment is performed as described above.
　次に、上述したように、第１保護膜１８、第２保護膜２２、ソース電極１５Ａ１および１５Ａ２、ドレイン電極１７Ａ１および１７Ａ２、ならびに、画素電極１９Ａ３を形成し、半導体装置１００Ｃが製造される。 Next, as described above, the first protective film 18, the second protective film 22, the source electrodes 15A1 and 15A2, the drain electrodes 17A1 and 17A2, and the pixel electrode 19A3 are formed, and the semiconductor device 100C is manufactured.
　次に、本発明による他の実施形態における半導体装置１００Ｄを説明する。 Next, a semiconductor device 100D according to another embodiment of the present invention will be described.
　図８は、半導体装置１００Ｄの模式的な断面図である。なお、半導体装置１００Ｄの構造は、半導体装置１００Ａが有するｐ型ＴＦＴ１０Ａ２および遮光層４Ａ２が形成されていない構造を有する。半導体装置１００Ｄは半導体装置１００Ａと同様の効果を有する。 FIG. 8 is a schematic cross-sectional view of the semiconductor device 100D. The semiconductor device 100D has a structure in which the p-type TFT 10A2 and the light shielding layer 4A2 included in the semiconductor device 100A are not formed. The semiconductor device 100D has the same effect as the semiconductor device 100A.
　次に、図９および図１０を参照しながら半導体装置１００Ｄの製造方法について説明する。図９（ａ）および図９（ｂ）、ならびに、図１０（ａ）～図１０（ｃ）は、半導体装置１００Ｄの製造方法を説明する断面図である。 Next, a method for manufacturing the semiconductor device 100D will be described with reference to FIGS. FIGS. 9A and 9B and FIGS. 10A to 10C are cross-sectional views illustrating a method for manufacturing the semiconductor device 100D.
　図９（ａ）に示すように、上述した方法で、絶縁基板１１上に、遮光層４Ａ１および４Ａ３、第１および第２下地絶縁膜１２および１４、島状の結晶質半導体層３０Ａ１および３０Ａ３、ならびに、ゲート絶縁膜１６を形成する。また、ゲート絶縁膜１６を形成した後、ｐ型不純物をそれぞれの結晶質半導体層の全面にドーピングしてもよい。 As shown in FIG. 9A, on the insulating substrate 11, the light shielding layers 4A1 and 4A3, the first and second base insulating films 12 and 14, the island-shaped crystalline semiconductor layers 30A1 and 30A3, In addition, the gate insulating film 16 is formed. Further, after the gate insulating film 16 is formed, a p-type impurity may be doped on the entire surface of each crystalline semiconductor layer.
　次に、ポジ型のフォトレジスト７９を絶縁基板１１の全面に公知の方法で形成する。 Next, a positive photoresist 79 is formed on the entire surface of the insulating substrate 11 by a known method.
　次に、遮光層４Ａ１をマスクとして、絶縁基板１１の裏面から露光する（背面露光）。このとき、フォトマスクを用いない。 Next, exposure is performed from the back surface of the insulating substrate 11 using the light shielding layer 4A1 as a mask (back surface exposure). At this time, a photomask is not used.
　その結果、図９（ｂ）に示すように、遮光層４Ａ１および４Ａ３をマスクとしているので、それぞれの遮光層４Ａ１および４Ａ３に対応して、ポジ型のフォトレジスト７９がパターニングされ、島状のポジ型のフォトレジスト８１ａおよび８１ｂが形成される。ポジ型のフォトレジスト８１ａおよび８１ｂは、それぞれ、遮光層４Ａ１および４Ａ３に対して自己整合的に形成される。また、結晶質半導体層３０Ａ３の内、補助容量Ｃｓの電極となる領域は、ポジ型のフォトレジスト８１ｂで覆われていない。 As a result, as shown in FIG. 9B, since the light shielding layers 4A1 and 4A3 are used as masks, a positive photoresist 79 is patterned corresponding to each of the light shielding layers 4A1 and 4A3 to form island-shaped positive electrodes. Mold photoresists 81a and 81b are formed. The positive photoresists 81a and 81b are formed in a self-aligned manner with respect to the light shielding layers 4A1 and 4A3, respectively. In addition, the region serving as the electrode of the auxiliary capacitance Cs in the crystalline semiconductor layer 30A3 is not covered with the positive photoresist 81b.
　次に、図１０（ａ）に示すように、ポジ型のフォトレジスト８１ａ、８１ｂをマスクとして、ｎ型不純物ｎ１を結晶質半導体層３０Ａ３の内、補助容量Ｃｓの電極となる領域にドーピングする。ｎ型不純物ｎ１をドーピングする条件は、例えば、ドーピングガスとしてＰＨ3（フォスフィン）を用い、加速電圧６０ｋＶ以上９０ｋＶ以下で、ドーズ量１×１０14ｃｍ-2以上１×１０16ｃｍ-2以下（本実施形態において、加速電圧７０ｋＶ、ドーズ量１×１０15ｃｍ-2）が好ましい。ポジ型のフォトレジスト８１ａで覆われた結晶質半導体層３０Ａ１、および、結晶質半導体層３０Ａ３の内、ポジ型のフォトレジスト８１ｂで覆われた領域にはｎ型不純物ｎ１はドーピングされない。その結果、結晶質半導体層３０Ａ３に中濃度領域３８Ａが形成される。 Next, as shown in FIG. 10A, n-type impurity n1 is doped in the crystalline semiconductor layer 30A3 in the region serving as the electrode of the auxiliary capacitor Cs using the positive photoresists 81a and 81b as a mask. Conditions for doping the n-type impurity n1 include, for example, using PH 3 (phosphine) as a doping gas, an acceleration voltage of 60 kV to 90 kV, and a dose of 1 × 10 14 cm −2 to 1 × 10 16 cm −2 ( In this embodiment, an acceleration voltage of 70 kV and a dose of 1 × 10 15 cm −2 are preferable. Of the crystalline semiconductor layer 30A1 covered with the positive photoresist 81a and the crystalline semiconductor layer 30A3, the region covered with the positive photoresist 81b is not doped with the n-type impurity n1. As a result, an intermediate concentration region 38A is formed in the crystalline semiconductor layer 30A3.
　次に、ポジ型のフォトレジスト８１ａおよび８１ｂを公知の方法で除去する。 Next, the positive photoresists 81a and 81b are removed by a known method.
　次に、図１０（ｂ）に示すように、結晶質半導体層３０Ａ１および３０Ａ３上にゲート電極１３Ａ１および１３Ａ３ａおよび１３Ａ３ｂ、ならびに、補助容量電極１３Ａ３ｃをそれぞれ公知の方法で形成する。また、補助容量電極１３Ａ３ｃは、中濃度領域３８Ａと重なるように形成される。 Next, as shown in FIG. 10B, gate electrodes 13A1, 13A3a and 13A3b, and auxiliary capacitance electrodes 13A3c are formed on the crystalline semiconductor layers 30A1 and 30A3 by a known method. Further, the auxiliary capacitance electrode 13A3c is formed so as to overlap the intermediate concentration region 38A.
　次に、ゲート電極１３Ａ１および１３Ａ３ａおよび１３Ａ３ｂ、ならびに、補助容量電極１３Ａ３ｃをマスクとして、結晶質半導体層３０Ａ１および３０Ａ３にｎ型不純物ｎ２をドーピングする。ｎ型不純物ｎ２をドーピングする条件は、例えば、ドーピングガスとしてＰＨ3（フォスフィン）を用い、加速電圧６０ｋＶ以上９０ｋＶ以下の範囲で、ドーズ量１×１０12ｃｍ-2以上１×１０14ｃｍ-2以下（本実施形態において、加速電圧７０ｋＶ、ドーズ量５×１０13ｃｍ-2）が好ましい。ｎ型不純物のドーピングによって、画素用のＴＦＴ１０Ａ３の低濃度領域（ＬＤＤ領域）となる領域が形成される。また、結晶質半導体層３０Ａ１および３０Ａ３の内、ゲート電極１３Ａ１、１３Ａ３ａおよび１３Ａ３ｂと重なる領域は、それぞれ、チャネル領域３３Ａ１、３３Ａａおよび３３Ａｂとなる。 Next, the crystalline semiconductor layers 30A1 and 30A3 are doped with an n-type impurity n2 using the gate electrodes 13A1 and 13A3a and 13A3b and the auxiliary capacitance electrode 13A3c as a mask. The conditions for doping the n-type impurity n2 are, for example, using PH 3 (phosphine) as a doping gas and a dose amount of 1 × 10 12 cm −2 or more and 1 × 10 14 cm −2 in an acceleration voltage range of 60 kV to 90 kV. The following (in this embodiment, acceleration voltage 70 kV, dose amount 5 × 10 13 cm −2 ) is preferable. A region to be a low concentration region (LDD region) of the pixel TFT 10A3 is formed by doping with the n-type impurity. In the crystalline semiconductor layers 30A1 and 30A3, regions overlapping with the gate electrodes 13A1, 13A3a, and 13A3b are channel regions 33A1, 33Aa, and 33Ab, respectively.
　次に、図１０（ｃ）に示すように、画素用のＴＦＴ１０Ａ３の低濃度領域（ＬＤＤ領域）となる領域を覆うように、ポジ型のフォトレジスト８２ａおよび８２ｂを公知の方法で形成する。 Next, as shown in FIG. 10C, positive photoresists 82a and 82b are formed by a known method so as to cover a region that becomes a low concentration region (LDD region) of the pixel TFT 10A3.
　次に、ポジ型のフォトレジスト８２ａおよび８２ｂ、ゲート電極１３Ａ１、ならびに、補助容量電極１３Ａ３ｃをマスクとして、ｎ型不純物ｎ３を結晶質半導体層３０Ａ１および３０Ａ３にドーピングする。ｎ型不純物ｎ３をドーピングする条件は、例えば、ドーピングガスとしてＰＨ3（フォスフィン）を用い、加速電圧６０ｋＶ以上９０ｋＶ以下で、ドーズ量１×１０15ｃｍ-2以上１×１０16ｃｍ-2以下（本実施形態において、加速電圧７０ｋＶ、ドーズ量５×１０15ｃｍ-2）が好ましい。その結果、結晶質半導体層３０Ａ１にソース領域３１Ａ１およびドレイン領域３５Ａ１が形成される。また、結晶質半導体層３０Ａ３にソース領域３１Ａ３、ドレイン領域３５Ａ３および高濃度領域３６Ａ３が形成される。 Next, the n-type impurity n3 is doped into the crystalline semiconductor layers 30A1 and 30A3 using the positive photoresists 82a and 82b, the gate electrode 13A1, and the auxiliary capacitance electrode 13A3c as a mask. The conditions for doping the n-type impurity n3 are, for example, using PH 3 (phosphine) as a doping gas, an acceleration voltage of 60 kV to 90 kV, and a dose of 1 × 10 15 cm −2 to 1 × 10 16 cm −2 ( In the present embodiment, an acceleration voltage of 70 kV and a dose of 5 × 10 15 cm −2 are preferable. As a result, the source region 31A1 and the drain region 35A1 are formed in the crystalline semiconductor layer 30A1. In addition, a source region 31A3, a drain region 35A3, and a high concentration region 36A3 are formed in the crystalline semiconductor layer 30A3.
　次に、ポジ型のフォトレジスト８２ａおよび８２ｂを公知の方法で除去し、上述したように熱処理を行う。 Next, the positive photoresists 82a and 82b are removed by a known method, and heat treatment is performed as described above.
　次に、上述したように、第１保護膜１８、第２保護膜２２、ソース電極１５Ａ１および１５Ａ３、ドレイン電極１７Ａ１、ならびに、画素電極１９Ａ３を形成し、図８に示した半導体装置１００Ｄが製造される。 Next, as described above, the first protective film 18, the second protective film 22, the source electrodes 15A1 and 15A3, the drain electrode 17A1, and the pixel electrode 19A3 are formed, and the semiconductor device 100D shown in FIG. 8 is manufactured. The
　以上、半導体装置１００Ａ～１００Ｄにより、多種類のＴＦＴを同一基板上に形成する場合における、製造コストが削減された半導体装置の製造方法およびそのような製造方法によって製造される半導体装置が提供される。 As described above, the semiconductor devices 100A to 100D provide a method for manufacturing a semiconductor device with reduced manufacturing costs and a semiconductor device manufactured by such a manufacturing method when many types of TFTs are formed on the same substrate. .
　本発明の適用範囲は極めて広く、ＴＦＴを備えた半導体装置、あるいは、そのような半導体装置を有するあらゆる分野の電子機器に適用することが可能である。例えば、本発明を実施して形成された回路や画素部はアクティブマトリクス型液晶表示装置や有機ＥＬ表示装置に用いることができる。このような表示装置は、例えば携帯電話や携帯ゲーム機の表示画面や、デジタルカメラのモニター等に利用され得る。従って、液晶表示装置や有機ＥＬ表示装置が組み込まれた電子機器のすべてに本発明を適用できる。 The applicable range of the present invention is extremely wide, and it can be applied to a semiconductor device provided with a TFT or an electronic device in any field having such a semiconductor device. For example, a circuit or a pixel portion formed by implementing the present invention can be used for an active matrix liquid crystal display device or an organic EL display device. Such a display device can be used for a display screen of a mobile phone or a portable game machine, a monitor of a digital camera, or the like. Therefore, the present invention can be applied to all electronic devices in which a liquid crystal display device or an organic EL display device is incorporated.
　１０Ａ１、１０Ａ２、１０Ａ３　　　ＴＦＴ
　４Ａ１、４Ａ２、４Ａ３　　　　遮光層
　１１　　　　絶縁基板
　１２、１４　　　　絶縁膜
　１３　　　　ゲート配線
　１３Ａ１、１３Ａ２、１３Ａ３ａ、１３Ａ３ｂ　　　　ゲート電極
　１３Ａ３ｃ　　　　補助容量電極
　１５Ａ１、１５Ａ２、１５Ａ３　　　　ソース電極
　１７Ａ１、１７Ａ２　　　　ドレイン電極
　１９Ａ３　　　　画素電極
　１６　　　　ゲート絶縁膜
　１８、２２　　　　保護膜
　３０Ａ１、３０Ａ２、３０Ａ３　　　　結晶質半導体層
　３１Ａ１、３１Ａ２、３１Ａ３　　　　ソース領域
　３２Ａａ、３２Ａｂ、３４Ａａ、３４Ａｂ　　　　低濃度領域
　３３Ａ１、３３Ａ２、３３Ａ３ａ、３３Ａ３ｂ　　　　チャネル領域
　３５Ａ１、３５Ａ２、３５Ａ３　　　　ドレイン領域
　３６Ａ　　　　高濃度領域
　３８Ａ　　　　中濃度領域（補助容量電極）
　Ｃｓ　　　　補助容量
　１００Ａ　　　　半導体装置 10A1, 10A2, 10A3 TFT
4A1, 4A2, 4A3 Light shielding layer 11 Insulating substrate 12, 14 Insulating film 13 Gate wiring 13A1, 13A2, 13A3a, 13A3b Gate electrode 13A3c Auxiliary capacitance electrode 15A1, 15A2, 15A3 Source electrode 17A1, 17A2 Drain electrode 19A3 Pixel electrode 16 Gate insulating film 18, 22 Protective film 30A1, 30A2, 30A3 Crystalline semiconductor layer 31A1, 31A2, 31A3 Source region 32Aa, 32Ab, 34Aa, 34Ab Low concentration region 33A1, 33A2, 33A3a, 33A3b Channel region 35A1, 35A2, 35A3 Drain region 36A High concentration Region 38A Medium concentration region (auxiliary capacitance electrode)
Cs Auxiliary capacitor 100A Semiconductor device

Claims (11)

  1. 　絶縁基板と、
    　前記絶縁基板上に形成された第１遮光層と、
    　前記絶縁基板に支持された、画素用のＴＦＴと、補助容量とを有し、
    　前記補助容量の電極は、前記画素用のＴＦＴの半導体層を形成する材料と同一の材料から形成されており、
    　前記画素用のＴＦＴの半導体層は、前記第１遮光層と重なるように形成され、
    　前記補助容量の電極は、前記第１遮光層と重ならないように形成されている、半導体装置。     An insulating substrate;
    A first light shielding layer formed on the insulating substrate;
    A pixel TFT supported by the insulating substrate, and an auxiliary capacitor;
    The auxiliary capacitor electrode is formed of the same material as that of the semiconductor layer of the pixel TFT,
    The pixel TFT semiconductor layer is formed to overlap the first light-shielding layer,
    The semiconductor device, wherein the auxiliary capacitance electrode is formed so as not to overlap the first light shielding layer.
  2. 　前記画素用のＴＦＴの半導体層は、低濃度領域を有する、請求項１に記載の半導体装置。 2. The semiconductor device according to claim 1, wherein the semiconductor layer of the pixel TFT has a low concentration region.
  3. 　前記絶縁基板上に形成された第２遮光層と、
    　前記絶縁基板に支持された、駆動回路用のｎ型ＴＦＴとをさらに有し、
    　前記駆動回路用のｎ型ＴＦＴの半導体層は、前記第２遮光層と重なるように形成されている、請求項１または２に記載の半導体装置。     A second light shielding layer formed on the insulating substrate;
    An n-type TFT for a drive circuit supported by the insulating substrate;
    The semiconductor device according to claim 1, wherein a semiconductor layer of the n-type TFT for the drive circuit is formed so as to overlap the second light shielding layer.
  4. 　前記絶縁基板上に支持された、駆動回路用のｐ型ＴＦＴをさらに有する、請求項１から３のいずれかに記載の半導体装置。 4. The semiconductor device according to claim 1, further comprising a p-type TFT for a drive circuit supported on the insulating substrate.
  5. 　前記絶縁基板上に形成された第３遮光層を有し、
    　前記第３遮光層は、前記駆動回路用のｐ型ＴＦＴの半導体層と重なるように形成されている、請求項４に記載の半導体装置。     A third light shielding layer formed on the insulating substrate;
    The semiconductor device according to claim 4, wherein the third light shielding layer is formed so as to overlap with a semiconductor layer of the p-type TFT for the drive circuit.
  6. 　前記駆動回路用のｐ型ＴＦＴの半導体層のチャネル領域におけるｐ型不純物の濃度は、前記駆動回路用のｎ型ＴＦＴの半導体層のチャネル領域におけるｐ型不純物の濃度より大きい、請求項４または５に記載の半導体装置。 6. The concentration of the p-type impurity in the channel region of the semiconductor layer of the p-type TFT for the drive circuit is higher than the concentration of the p-type impurity in the channel region of the semiconductor layer of the n-type TFT for the drive circuit. A semiconductor device according to 1.
  7. 　前記駆動回路用のｐ型ＴＦＴの半導体層のチャネル領域におけるｐ型不純物の濃度は、前記駆動回路用のｎ型ＴＦＴの半導体層のチャネル領域におけるｐ型不純物の濃度と等しい、請求項４または５に記載の半導体装置。 6. The concentration of the p-type impurity in the channel region of the semiconductor layer of the p-type TFT for the drive circuit is equal to the concentration of the p-type impurity in the channel region of the semiconductor layer of the n-type TFT for the drive circuit. A semiconductor device according to 1.
  8. 　駆動回路用のｎ型ＴＦＴと、画素用のＴＦＴと、補助容量とを同一絶縁基板上に形成する半導体装置の製造方法であって、
    　前記絶縁基板上に遮光層を形成する工程（Ａ）と、
    　前記遮光層と重なるように半導体層を形成する工程（Ｂ）と、
    　前記遮光層に対して自己整合的にフォトレジストを形成する工程（Ｃ）と、
    　前記フォトレジストをマスクとして、前記半導体層に不純物をドーピングする工程（Ｄ）とを包含する、半導体装置の製造方法。     A method of manufacturing a semiconductor device in which an n-type TFT for a drive circuit, a TFT for a pixel, and an auxiliary capacitor are formed on the same insulating substrate,
    Forming a light shielding layer on the insulating substrate (A);
    A step (B) of forming a semiconductor layer so as to overlap the light shielding layer;
    Forming a photoresist in a self-aligned manner with respect to the light shielding layer (C);
    And (D) a step of doping impurities into the semiconductor layer using the photoresist as a mask.
  9. 　前記工程（Ｄ）は、前記補助容量の電極を、前記画素用のＴＦＴの半導体層を形成する材料と同じ材料で形成する工程（Ｄ１）を包含する、請求項８に記載の半導体装置の製造方法。 9. The manufacturing of a semiconductor device according to claim 8, wherein the step (D) includes a step (D <b> 1) of forming an electrode of the auxiliary capacitor with the same material as a material for forming a semiconductor layer of the pixel TFT. Method.
  10. 　前記画素用のＴＦＴの結晶質半導体層に、低濃度領域を形成する工程（Ｅ）を包含する、請求項８または９に記載の半導体装置の製造方法。 10. The method for manufacturing a semiconductor device according to claim 8, further comprising a step (E) of forming a low concentration region in a crystalline semiconductor layer of the pixel TFT.
  11. 　前記駆動回路用のｐ型ＴＦＴと、前記駆動回路用のｎ型ＴＦＴと、前記画素用のＴＦＴと、前記補助容量とを前記同一絶縁基板上に形成する、請求項８から１０のいずれかに記載の半導体装置の製造方法。 The p-type TFT for the driving circuit, the n-type TFT for the driving circuit, the TFT for the pixel, and the auxiliary capacitor are formed on the same insulating substrate. The manufacturing method of the semiconductor device of description.
PCT/JP2011/076785 2010-11-24 2011-11-21 Semiconductor device and method for manufacturing same WO2012070521A1 (en)

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000196093A (en) * 1998-12-25 2000-07-14 Semiconductor Energy Lab Co Ltd Semiconductor device and method of producing thereof
JP2000269511A (en) * 1999-01-11 2000-09-29 Semiconductor Energy Lab Co Ltd Semiconductor device and its forming method

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000196093A (en) * 1998-12-25 2000-07-14 Semiconductor Energy Lab Co Ltd Semiconductor device and method of producing thereof
JP2000269511A (en) * 1999-01-11 2000-09-29 Semiconductor Energy Lab Co Ltd Semiconductor device and its forming method

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