JP4666710B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device having a circuit composed of thin film transistors (hereinafter referred to as TFTs). For example,The present invention relates to a configuration of an electro-optical device typified by a liquid crystal display device or an EL (electroluminescence) display device, a semiconductor circuit, and an electric appliance (electronic device) using the electro-optical device or the semiconductor circuit of the present invention.
[0002]
Note that in this specification, a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics, and an electro-optical device, a semiconductor circuit, and an electric appliance are all semiconductor devices.
[0003]
[Prior art]
Since a thin film transistor (hereinafter referred to as TFT) can be formed on a transparent substrate, application development to an active matrix liquid crystal display (hereinafter referred to as AM-LCD) has been actively promoted. Since a TFT using a crystalline semiconductor film (typically a polysilicon film) has high mobility, a high-definition image display can be realized by integrating functional circuits on the same substrate. Yes.
[0004]
The AM-LCD is basically a pixel unit that displays images.(Also called pixel matrix circuit)And driving the TFT of each pixel arranged in the pixel portionGate drive circuit (also called gate driver circuit),eachPixelSend image signal to TFTSource drive circuit (also called source driver circuit) or data drive circuit (also called data driver circuit)It is formed on the same substrate.Note that a region where the gate driver circuit and the source driver circuit are formed is referred to as a driver circuit portion.
[0005]
In recent years, a system on panel has been proposed in which signal processing circuits such as a signal dividing circuit and a γ correction circuit are provided on the same substrate in addition to the pixel portion and the drive circuit portion.
[0006]
However, since the performance required by the circuit differs between the pixel portion and the drive circuit portion, it is difficult to satisfy all circuit specifications with TFTs having the same structure. That is, shift register circuits that emphasize high-speed operationDrive circuit unit includingAt present, no TFT structure has been established that satisfies both the TFTs constituting the pixel portion that places importance on high breakdown voltage characteristics (hereinafter referred to as pixel TFTs).
[0007]
Therefore, the present applicant has applied for a configuration in which the thickness of the gate insulating film is made different between the TFT constituting the drive circuit portion (hereinafter referred to as drive TFT) and the pixel TFT (Japanese Patent Laid-Open No. 10-056184, corresponding). No. 08 / 862,895). Specifically, the gate insulating film of the driving TFT is made thinner than the gate insulating film of the pixel TFT.
[0008]
[Problems to be solved by the invention]
In the present invention, further improvements relating to the pixel portion are made based on the configuration described in the above publication. Specifically, a structure for forming a storage capacitor capable of securing a large capacity with a small area is provided.
[0009]
It is another object of the present invention to provide an electro-optical device having high reliability by forming each circuit of an electro-optical device typified by an AM-LCD with a TFT having an appropriate structure according to the function. By extension, such an electro-optical deviceDisplay sectionIt is an object of the present invention to improve the reliability of a semiconductor device (electric appliance) that is included.
[0010]
[Means for Solving the Problems]
The configuration of the invention disclosed in this specification is as follows.
In a semiconductor device including a pixel portion having a pixel TFT and a storage capacitor in each pixel,
The active layer of the pixel TFT is formed above the light shielding film with an insulating film laminated in at least two layers interposed therebetween,
The storage capacitor is formed of a semiconductor film having the same composition as the electrode, dielectric, and drain region of the pixel TFT formed in the same layer as the light shielding film,
The dielectric is composed of a part of the insulating film laminated in at least two layers.
[0011]
In addition, the configuration of other inventions is as follows:
In a semiconductor device including a pixel portion having a pixel TFT and a storage capacitor in each pixel,
The active layer of the pixel TFT is formed above the light shielding film with an insulating film laminated in at least two layers interposed therebetween,
The storage capacitor is formed of a semiconductor film having the same composition as the electrode, dielectric, and drain region of the pixel TFT formed in the same layer as the light shielding film,
The dielectric is composed of a remaining layer obtained by removing a part of the insulating film laminated in at least two layers.
[0012]
In addition, the configuration of other inventions is as follows:
In a semiconductor device including a pixel portion having a pixel TFT and a storage capacitor in each pixel,
The active layer of the pixel TFT is formed above the light shielding film with the first insulating film in contact with the light shielding film and the second insulating film in contact with the active layer interposed therebetween,
The storage capacitor is formed of a semiconductor film having the same composition as the electrode formed in the same layer as the light shielding film, the second insulating film, and the drain region of the pixel TFT.
[0013]
In addition, the configuration of other inventions is as follows:
In a semiconductor device including a pixel portion having a pixel TFT and a storage capacitor in each pixel,
The active layer of the pixel TFT is formed above the light shielding film with the first insulating film in contact with the light shielding film and the second insulating film in contact with the active layer interposed therebetween,
The storage capacitor is formed of a semiconductor film having the same composition as the electrode formed in the same layer as the light shielding film, the second insulating film, and the drain region of the pixel TFT.
[0014]
In the above configuration,The film thickness of the second insulating film is not more than 1/5 times (preferably 1/100 to 1/10 times) the film thickness of the laminated film composed of the first insulating film and the second insulating film.It is desirable to do.
[0015]
In addition, the configuration of other inventions is as follows:
A method of manufacturing a semiconductor device including a pixel portion having a pixel TFT and a storage capacitor in each pixel,
Forming a light shielding film and an electrode made of the same material as the light shielding film on a substrate;
Forming a first insulating film covering the light shielding film and the electrode;
Etching the first insulating film to form an opening on the electrode;
Forming a second insulating film covering the first insulating film and the opening;
Forming a semiconductor film on the second insulating film;
It is characterized by having.
[0016]
In addition, the configuration of other inventions is as follows:
A method for manufacturing a semiconductor device including a driver circuit portion and a pixel portion having a pixel TFT and a storage capacitor in each pixel,
Forming a light shielding film and an electrode made of the same material as the light shielding film on a substrate;
Forming a first insulating film covering the light shielding film and the electrode;
Etching the first insulating film to form an opening on the electrode;
Forming a second insulating film covering the first insulating film and the opening;
Forming a semiconductor film on the second insulating film;
Forming a gate insulating film covering the semiconductor film;
Etching a part of the gate insulating film to expose a part of the semiconductor film of the driving circuit part and the semiconductor film of the pixel part;
Forming a thermal oxide film on the surface of the semiconductor film exposed by etching of the gate insulating film by thermal oxidation;
It is characterized by having.
[0017]
In addition, the configuration of other inventions is as follows:
A method for manufacturing a semiconductor device including a driver circuit portion and a pixel portion having a pixel TFT and a storage capacitor in each pixel,
Forming a light shielding film and an electrode made of the same material as the light shielding film on a substrate;
Forming a first insulating film covering the light shielding film and the electrode;
Etching the first insulating film to form an opening on the electrode;
Forming a second insulating film covering the first insulating film and the opening;
Forming a semiconductor film on the second insulating film;
Forming a gate insulating film covering the semiconductor film;
Etching a part of the gate insulating film to expose a part of the semiconductor film of the driving circuit part and the semiconductor film of the pixel part;
Forming a thermal oxide film on the surface of the semiconductor film exposed by etching of the gate insulating film by thermal oxidation;
Forming an LDD region in the semiconductor film of the drive circuit portion and the semiconductor film of the pixel portion, and
The drive circuit portion and the pixel portion have different LDD region lengths.
[0018]
DETAILED DESCRIPTION OF THE INVENTION
An embodiment of the present invention will be described with reference to FIG. FIG. 1 is a cross-sectional view of an AM-LCD in which a drive circuit portion and a pixel portion are integrally formed on the same substrate. Here, a CMOS circuit is shown as a basic circuit constituting the drive circuit portion, and a double-gate TFT is shown as a pixel TFT. Of course, not only a double gate structure but also a triple gate structure or a single gate structureMulti-gate structure.
[0019]
In FIG. 1, reference numeral 101 denotes a substrate having heat resistance, and a quartz substrate, a silicon substrate, a ceramic substrate, or a metal substrate (typically a stainless steel substrate) may be used. Regardless of which substrate is used, a base film (preferably an insulating film containing silicon as a main component) may be provided as necessary.
[0020]
Reference numeral 102 denotes a light shielding film, and 103 denotes a lower electrode of a storage capacitor, which are formed of the same material in the same layer. As a material for forming the light shielding film 102 and the lower electrode 103 of the storage capacitor, a heat conductive film that can withstand a temperature of 800 to 1150 ° C. (preferably 900 to 1100 ° C.) is used.
[0021]
Typically, a conductive silicon film (eg, phosphorus-doped silicon film, boron-doped silicon film, etc.), a metal film (eg, tungsten film, tantalum film, molybdenum film, titanium film, etc.) or a combination of the above metal film components An alloy film may be used. Further, a silicide film obtained by siliciding the metal film or a nitrided nitride film (a tantalum nitride film, a tungsten nitride film, a titanium nitride film, or the like) may be used. Moreover, you may laminate | stack combining these freely.
[0022]
When the metal film is used, it is desirable to have a laminated structure with a silicon film in order to prevent oxidation of the metal film. In terms of preventing oxidation, a structure in which a metal film is covered with an insulating film containing silicon as a main component is also effective. Note that in this specification, “an insulating film containing silicon as a main component refers to a silicon oxide film, a silicon nitride film, or an insulating film containing silicon, oxygen, and nitrogen in a predetermined component ratio.
[0023]
104 is a base film formed with a film thickness of 0.3 to 1 μm (preferably 0.6 to 0.8 μm).(Hereinafter referred to as the first insulating film)And formed of an insulating film containing silicon as a main component. The first insulating film 104 is provided with an opening in a portion serving as a storage capacitor, and again an insulating film containing silicon as a main component.(Hereinafter referred to as the second insulating film)105 is provided.
[0024]
Note that although a two-layer structure is formed here, the first insulating film 104 in contact with the light shielding film and the second insulating film 105 in contact with the active layer of the pixel TFT, a multilayer structure may be used. Therefore, finally, the active layer of the pixel TFT has a structure formed above the light shielding film 102 with an insulating film laminated in at least two layers interposed therebetween. In addition, a part of the insulating film stacked in at least two layers (a single layer or a plurality of layers) may be a dielectric of the storage capacitor. In other words, the remaining layer obtained by removing a part of the insulating film laminated in at least two layers becomes the dielectric of the storage capacitor.
[0025]
In the present embodiment, the second insulating film 105 functions as a dielectric of the storage capacitor (particularly indicates a portion indicated by 106). The film thickness of the second insulating film 105 (the storage capacitor dielectric 106) may be 5 to 75 nm (preferably 20 to 50 nm). The thinner the capacitor, the larger the capacity of the storage capacitor. However, if the breakdown voltage is not taken into account, a leakage current is generated. The idea of stacking the film in two steps is effective for improving the breakdown voltage.
[0026]
First insulating film104 needs to have a sufficiently thick film thickness so that the light-shielding film 102 does not form a parasitic capacitance with the upper TFT. In this way, by providing an opening in the storage capacitor portion, the dielectric of the storage capacitor Can be made thinner. Therefore, the capacity can be earned without increasing the area for forming the capacity. The configuration of this storage capacitor is not in the above-mentioned Japanese Patent Laid-Open No. 10-056184.
[0027]
1 is characterized by an insulating film (between the active layer of the pixel TFT and the light shielding film 102).First insulating film104 andSecond insulating film105Consist ofLayered film) and between the upper electrode 118 of the storage capacitor made of a semiconductor film and the lower electrode 103 of the storage capacitor.Second insulating film105 (dielectric 106 of the storage capacitor) has a different film thickness. Specifically, the film thickness of the latter is not more than 1/5 times that of the former (preferably1/100 to 1/10 times).
[0028]
Thus, a storage capacitor having a large capacity can be formed without forming a parasitic capacitance between the pixel TFT and the light shielding film 102.
[0029]
Note that the light-shielding film 102 provided under the pixel TFT may be in a floating state or set at a fixed potential. As the fixed potential, it is desirable to set at least a potential lower than the lowest potential of the video signal, preferably the lowest power supply potential of the entire circuit formed on the substrate or a potential lower than the lowest power supply potential.
[0030]
For example, in the case of an AM-LCD, various power supply lines are formed by a driving circuit portion, other signal processing circuits, and a pixel portion, and a predetermined potential is applied to each of them. That is, there is a certain reference minimum potential, and various voltages are generated based on the reference minimum potential.
The lowest power supply potential refers to the lowest potential that serves as a reference in all the circuits.
[0031]
In this way, the light shielding film 102 is in a floating state or a fixed potential.By doing so, it is possible to obtain a light-shielding film that does not affect the TFT operation (forms almost no parasitic capacitance or the like).
[0032]
As described above, by providing the light shielding film under the pixel TFT, it is possible to prevent the occurrence of light leakage current due to stray light from the substrate side. It is not necessary to provide a light-shielding film because the drive circuit portion side does not originally receive light. This is preferable in the sense that the parasitic capacitance is reduced even a little.
[0033]
Also,First insulating film104 andSecond insulating filmA semiconductor film serving as an active layer of the driving TFT, an active layer of the pixel TFT, and an upper electrode of the storage capacitor is formed on 105. Note that in this specification, an “electrode” is a part of “wiring” and refers to a portion that performs electrical connection with another wiring or a portion that intersects with a semiconductor film. Therefore, for convenience of explanation, “wiring” and “electrode” are properly used, but it is assumed that “electrode” is always included in the term “wiring”.
[0034]
In FIG. 1, the active layer of the driving TFT includes a source region 107, a drain region 108, an LDD (lightly doped drain) region 109, a channel forming region 110, and a P-channel TFT of an N-channel TFT (hereinafter referred to as NTFT). The source region 111 (hereinafter referred to as PTFT), the drain region 112 and the channel formation region 113 are formed.
[0035]
The active layer of the pixel TFT (here, NTFT is used) is formed of a source region 114, a drain region 115, LDD regions 116a and 116b, and channel formation regions 117a and 117b. Further, a semiconductor film extended from the drain region 115 is used as the upper electrode 118 of the storage capacitor. That is, the upper electrode 118 of the storage capacitor is made of a semiconductor film having the same composition as the drain region 115.
[0036]
As described above, the storage capacitor according to the present invention includes the electrode (here, the lower electrode 103 of the storage capacitor), the dielectric (here, the second insulating film 105), and the pixel TFT formed in the same layer as the light shielding film 102. A semiconductor film having the same composition as the drain region (here, the drain region 115 of the pixel TFT) is formed.
[0037]
However, the drain region and the upper electrode of the storage capacitor are not necessarily connected directly, and may be electrically connected by other wiring. In addition, the same composition is not necessarily required, and a semiconductor film having another conductivity type or a semiconductor film containing the same impurity as the drain region at a different concentration may be used.
[0038]
Here, in the case of FIG. 1, the width (length) of the LDD region is different between the drive TFT and the pixel TFT. Since driving TFTs place emphasis on the operating speed, they are provided as narrowly as possible so as not to provide a resistance component, and pixel TFTs place importance on the reduction of off-current (drain current that flows when the TFT is in the off state), so a somewhat long LDD region is required. is there. Therefore, the LDD region of the driving TFT is preferably provided to be equal to or narrower than the LDD region of the pixel TFT.
[0039]
A gate insulating film is formed to cover the active layer and the upper electrode of the storage capacitor. In the present invention, the gate insulating film 119 of the driving TFT is formed.Film thicknessIs the gate insulating film 120 of the pixel TFT.Film thicknessIt is formed thinner. Typically, the thickness of the gate insulating film 120 may be 50 to 200 nm (preferably 100 to 150 nm), and the thickness of the gate insulating film 119 may be 5 to 50 nm (preferably 10 to 30 nm).
[0040]
Note that the gate insulating film of the driving TFT does not need to have a single film thickness. That is, different in the drive circuit sectionFilm thicknessThere may be a driving TFT having an insulating film. In that case, different on the same substrateFilm thicknessThere are at least three or more types of TFTs having a gate insulating film. That is, it can be said that the thickness of the gate insulating film of at least some of the driving TFTs included in the driving circuit portion is thinner than the thickness of the gate insulating film of the pixel TFT.
[0041]
Next, on the gate insulating films 119 and 120, gate wirings 121 and 122 of the driving TFT and gate wirings 123a and 123b of the pixel TFT are formed. As a material for forming the gate wirings 121, 122, 123a, and 123b, a conductive film having heat resistance that can withstand a temperature of 800 to 1150 ° C. (preferably 900 to 1100 ° C.) is used. Specifically, a material similar to that of the light shielding film 102 or the lower electrode 103 of the storage capacitor may be selected.
[0042]
That is, a conductive silicon film (for example, a phosphorus-doped silicon film, a boron-doped silicon film, etc.), a metal film (for example, a tungsten film, a tantalum film, a molybdenum film, a titanium film, etc.), or an alloy film in which components of the above metal films are combined. But it ’s okay. Alternatively, a silicide film obtained by siliciding the metal film or a nitrided nitride film (such as a tantalum nitride film, a tungsten nitride film, or a titanium nitride film) may be used. Moreover, you may laminate | stack combining these freely.
[0043]
When the metal film is used, it is desirable to have a laminated structure with a silicon film in order to prevent oxidation of the metal film. In terms of preventing oxidation, a structure in which a metal film is covered with an insulating film containing silicon as a main component is effective. In FIG. 1, a protective film 124 is provided to prevent oxidation of the gate wiring.
[0044]
Next, reference numeral 125 denotes a first interlayer insulating film, which is formed of an insulating film (single layer or stacked layer) containing silicon as a main component. As an insulating film containing silicon as a main component, a silicon oxide film, a silicon nitride film, a silicon oxynitride film (a nitrogen content is higher than oxygen), a silicon nitride oxide film (an oxygen content is higher than nitrogen) Can be used).
[0045]
Then, contact holes are provided in the first interlayer insulating film 125, and source wirings 126 and 127 for the driving TFT, a drain wiring 128, a source wiring 129 for the pixel TFT, and a drain wiring 130 are formed. A passivation film 131 and a second interlayer insulating film 132 are formed thereon, and a light shielding film (black mask) 133 is further formed thereon. Further, a third interlayer insulating film 134 is formed on the light shielding film 133, and after the contact hole is provided, the pixel electrode 135 is formed.
[0046]
As the second interlayer insulating film 132 and the third interlayer insulating film 134, a resin film having a small relative dielectric constant is preferable. As the resin film, a polyimide film, an acrylic film, a polyamide film, a BCB (benzocyclobutene) film, or the like can be used.
[0047]
Further, as the pixel electrode 135, a transparent conductive film typified by an ITO film is used if a transmissive AM-LCD is manufactured, and a reflectivity typified by an aluminum film is used if a reflective AM-LCD is manufactured. A high metal film may be used.
[0048]
In FIG. 1, the pixel electrode 135 is electrically connected to the drain region 115 of the pixel TFT via the drain electrode 130. However, the pixel electrode 135 and the drain region 115 may be directly connected. good.
[0049]
In the AM-LCD having the above-described structure, the gate insulating film of the driving TFT is thinner than the gate insulating film of the pixel TFT, and the first insulating film is selectively removed at a portion serving as a storage capacitor and the thin TFT The two insulating films function as a dielectric for the storage capacitor. At this time, there is no problem of parasitic capacitance because the sufficiently thick first insulating film is provided between the light shielding film 102 provided under the pixel TFT and the active layer.
[0050]
In this way, it is possible to arrange an optimum TFT according to the performance of the circuit, and at the same time, it is possible to realize a storage capacitor that can secure a large capacitance with a small area.
[0051]
The present invention having the above-described configuration will be described in more detail with the following examples.
[0052]
【Example】
[Example 1]
In this example, a manufacturing process for realizing the structure of FIG. 1 described in the “Embodiment Mode of the Invention” will be described. 2-5 is used for description.
[0053]
First, a quartz substrate 201 is prepared as a substrate, and a light shielding film 202 using a laminated film of silicon film / tungsten nitride film / tungsten film from the lower layer (or silicon film / tungsten silicide film / silicon film from the lower layer) is held thereon. A capacitor lower electrode 203 is formed. Of course, other conductive films described in the “Embodiments of the Invention” can be used. In this embodiment, the film thickness is 200 nm.
[0054]
next,Covering the light shielding film 202 and the lower electrode 203 of the storage capacitorMade of 0.6 μm thick silicon oxide filmFirst insulating film204 forming the storage capacitor(On the lower electrode 203 of the storage capacitor)Is selectively etched to form an opening 205. AndCovering the first insulating film 204 and the opening 205,A silicon oxide film (second insulating film) 206 having a thickness of 20 nm and an amorphous silicon film 207 are continuously formed by a low pressure thermal CVD method without opening to the atmosphere. By doing so, impurities such as boron contained in the atmosphere can be prevented from being adsorbed on the lower surface of the amorphous silicon film.
[0055]
In this embodiment, an amorphous silicon film is used, but another semiconductor film may be used. A microcrystalline silicon (microcrystal silicon) film or an amorphous silicon germanium film may be used.
[0056]
The second insulating film 206 is an insulating film that functions as a dielectric of the storage capacitor. Therefore, in this embodiment, silane (SiH) is used as a film forming gas._Four) And nitrous oxide (N₂O) is used to form a high-quality silicon oxide film (dielectric) at a film forming temperature of 800 ° C.
[0057]
Next, the amorphous silicon film 207 is crystallized. A known technique can be used as this crystallization means. In this embodiment, the technique described in JP-A-9-31260 is used as the crystallization means. The technology described in the publication uses an element selected from nickel, cobalt, palladium, germanium, platinum, iron, and copper as a catalyst element to promote crystallization.The amorphous silicon film is crystallized by the solid phase growth used.
[0058]
In this embodiment, nickel is selected as a catalyst element, and a layer (not shown) containing nickel is formed on the amorphous silicon film 207. Then, heat treatment is performed at 550 ° C. for 4 hours to crystallize, and a crystalline silicon (polysilicon) film 208 is formed. In this way, the state of FIG.
[0059]
Here, an impurity element (phosphorus or boron) for controlling the threshold voltage of the TFT may be added to the crystalline silicon film 208. Phosphorus or boron may be divided, or only one of them may be added.
[0060]
Next, a mask film 209 made of a 100 nm thick silicon oxide film is formed on the crystalline silicon film 208, and a resist mask 210 is formed thereon. Further, the mask film 209 is etched using the resist mask 210 as a mask to form openings 211a to 211c.
[0061]
In this state, an element belonging to Group 15 of the periodic table (phosphorus in this embodiment) is added to form phosphorus-added regions (phosphorus-doped regions) 212a to 212c. The concentration of phosphorus to be added is 5 × 10¹⁸~ 1x10²⁰atoms / cm^Three(Preferably 1 × 10¹⁹~ 5x10¹⁹atoms / cm^Three) Is preferred. However, the concentration of phosphorus to be added is not limited to this concentration range because it varies depending on the temperature and time of the subsequent gettering step and the area of the phosphorus-doped region. (Fig. 2 (C))
[0062]
Next, the resist mask 210 is removed and a heat treatment at 450 to 650 ° C. (preferably 500 to 600 ° C.) is applied for 2 to 16 hours to perform a gettering step of nickel remaining in the crystalline silicon film. In order to achieve the gettering action, a temperature of about ± 50 ° C. from the maximum temperature of the thermal history is necessary, but since the heat treatment for crystallization is performed at 550 to 600 ° C., the heat treatment at 500 to 650 ° C. is sufficient. The gettering action can be achieved.
[0063]
In this embodiment, nickel is moved in the direction of the arrow by applying a heat treatment at 600 ° C. for 8 hours, and gettered (captured) in the phosphorus addition regions 212a to 212c. Thus, the concentration of nickel remaining in the crystalline silicon film indicated by 213 and 214 is 2 × 10.¹⁷atoms / cm^ThreeThe following (preferably 1 × 10¹⁶atoms / cm^ThreeOr less). However, this concentration is a measurement result by mass secondary ion analysis (SIMS), and a concentration below this cannot be confirmed at present due to the measurement limit. (Fig. 3 (A))
[0064]
After the nickel gettering step is completed, the crystalline silicon films 213 and 214 are patterned to obtain an active layer of the driving TFT.(Semiconductor film)215, an active layer 216 of the pixel TFT is formed. At this time, it is desirable to completely remove the phosphorus-added region that has captured nickel.
[0065]
Then, a gate insulating film is formed by plasma CVD or sputtering.217Form. This gate insulating film is an insulating film that functions as a gate insulating film of the pixel TFT, and has a thickness of 50 to 200 nm. In this embodiment, a 100 nm thick silicon oxide film is used. Further, not only the silicon oxide film but also a stacked structure in which a silicon nitride film is provided over the silicon oxide film, or a silicon oxynitride film in which nitrogen is added to the silicon oxide film may be used.
[0066]
Gate insulation film217Then, a resist mask (not shown) is provided to form a gate insulating film.Etching is performed to expose a part of the active layer of the driver circuit portion and the active layer of the pixel portion. That is,The gate insulating film 217 is left on the pixel TFT, and the region above the driving TFT is removed. In this way, the state of FIG.
[0067]
Next, a heat treatment step at a temperature of 800 to 1150 ° C. (preferably 900 to 1100 ° C.) for 15 minutes to 8 hours (preferably 30 minutes to 2 hours) is performed in an oxidizing atmosphere (thermal oxidation step). In this example, 950 ° C. for 30 minutes in an oxygen atmosphere.Thermal oxidation treatmentI do.
[0068]
Note that the oxidizing atmosphere may be either a dry oxygen atmosphere or a wet oxygen atmosphere, but a dry oxygen atmosphere is suitable for reducing crystal defects in the semiconductor film. Alternatively, an atmosphere in which a halogen element is included in an oxygen atmosphere may be used. Thermal oxidation in an atmosphere containing this halogen elementprocessingThen, since the effect of removing nickel can also be expected, it is effective.
[0069]
By performing the thermal oxidation process in this manner, a silicon oxide film (thermal oxide film) 218 having a thickness of 5 to 50 nm (preferably 10 to 30 nm) is formed on the surface of the semiconductor film exposed by the etching of the gate insulating film. Finally, the silicon oxide film 218 functions as a gate insulating film of the driving TFT.
[0070]
The oxidation reaction also proceeds at the interface between the gate insulating film 217 made of a silicon oxide film remaining in the pixel TFT and the semiconductor film 216 therebelow. Therefore, the film thickness of the gate insulating film 219 of the pixel TFT is finally 50 to 200 nm (preferably 100 to 150 nm).
[0071]
When the thermal oxidation process is thus completed, the gate wiring 220 (NTFT side) of the driving TFT, 221 (PTFT side), and the gate wirings 222a and 222b of the pixel TFT are formed. Note that although two gate wirings 222a and 222b are shown because the pixel TFT has a double gate structure, they are actually the same wiring.
[0072]
In this embodiment, as the gate wirings 220 to 222a and 222b, a laminated film of silicon film / tungsten nitride film / tungsten film from the lower layer (or silicon film / tungsten silicide film from the lower layer) is used. Of course, it is needless to say that other conductive films described in the “Embodiments of the Invention” can be used. In this embodiment, the thickness of each gate wiring is 250 nm.
[0073]
In this embodiment, the lowermost silicon film is formed by using a low pressure thermal CVD method. Since the gate insulating film of the driver circuit is as thin as 5 to 50 nm, there is a risk of damaging the semiconductor film (active layer) depending on the conditions when sputtering or plasma CVD is used. Therefore, a thermal CVD method capable of forming a film by a chemical vapor reaction is preferable.
[0074]
Next, a SiNxOy (typically x = 0.5 to 2, y = 0.1 to 0.8) film 223 having a thickness of 25 to 50 nm is formed to cover the gate wirings 220 to 222a and 222b. The SiNxOy film 223 prevents the gate wirings 220 to 222 from being oxidized, and also functions as an etching stopper when a side wall made of a silicon film is removed later. Note that performing film formation in two steps is effective and effective in reducing pinholes.
[0075]
At this time, it is effective to perform plasma treatment using a gas containing hydrogen (ammonia gas in this embodiment) as a pretreatment for forming the SiNxOy film 213. Since hydrogen activated (excited) by the plasma by this pretreatment is confined in the active layer (semiconductor film), hydrogen termination is effectively performed.
[0076]
Further, when a nitrous oxide gas is added in addition to a gas containing hydrogen, the surface of the object to be processed is cleaned by the generated moisture, and contamination by boron or the like contained in the atmosphere can be effectively prevented.
[0077]
In this way, the state of FIG. Next, an amorphous silicon film (not shown) is formed, and anisotropic etching using a chlorine-based gas is performed to form sidewalls 224, 225, 226a, and 226b. After the sidewalls are formed, resist masks 227a and 227b are formed. Thereafter, an addition process of an element belonging to Group 15 of the periodic table (phosphorus in this embodiment) is performed on the semiconductor films 215 and 216.
[0078]
At this time, the gate wirings 220 to 222a and 222b, the side walls 224 to 226, and the resist masks 227a and 227b are used as masks, and impurity regions 228 to 232 are formed. The concentration of phosphorus added to the impurity regions 228 to 232 is 5 × 10¹⁹~ 1x10^{twenty one}atoms / cm^ThreeAdjust so that In this specification, the phosphorus concentration at this time is represented by (n +). (Fig. 4 (A))
[0079]
This process may be performed separately for the region where the driving TFT and the storage capacitor with a thin gate insulating film are formed, and the region where the pixel TFT with a thick gate insulating film is formed, or may be performed simultaneously. . In addition, the phosphorus addition step may use an ion implantation method in which mass separation is performed, or a plasma doping method in which mass separation is not performed. The practitioner may set optimum values for the acceleration voltage, the dose amount, and the like.
[0080]
When the state of FIG. 4A is thus obtained, the resist masks 227a and 227b and the sidewalls 224 to 226a and 226b are removed, and a phosphorus addition step is performed again. This step is performed with a lower dose than the previous phosphorus addition step. Thus, a low concentration impurity region is formed in a region where phosphorus is not added in the previous step. The concentration of phosphorus added to this low concentration impurity region is 5 × 10¹⁷~ 5x10¹⁸atoms / cm^ThreeAdjust so that In this specification, the phosphorus concentration at this time is represented by (n−). (Fig. 4 (B))
[0081]
Of course, this step may be performed separately for the region where the driving TFT and the storage capacitor with the thin gate insulating film are formed and the region where the pixel TFT with the thick gate insulating film is formed. good. In addition, the phosphorus addition step may use an ion implantation method in which mass separation is performed, or a plasma doping method in which mass separation is not performed. The practitioner may set optimum values for the acceleration voltage, the dose amount, and the like.
[0082]
However, since this low concentration impurity region functions as an LDD region, it is necessary to carefully control the concentration of phosphorus. Therefore, in this embodiment, the plasma doping method is used, and the concentration distribution (concentration profile) of the added phosphorus is set as shown in FIG.
[0083]
In FIG. 9, the gate insulating film 901 on the driver circuit portion side and the gate insulating film 902 on the pixel portion side have different thicknesses. For this reason, the concentration distribution of the added phosphorus in the depth direction is different.
[0084]
In this embodiment, the phosphorus addition conditions (acceleration voltage and the like) are adjusted so as to have a concentration distribution indicated by 903 on the drive circuit portion side and a concentration distribution indicated by 904 on the pixel portion side. In this case, although the concentration distribution in the depth direction is different, the phosphorus concentrations of the low-concentration impurity regions 905 and 906 formed as a result are substantially equal.
[0085]
The process shown in FIG. 9 can be used in all impurity addition processes described in this specification.
[0086]
This step defines the NTFT source region 233, LDD region 234, and channel formation region 235 that form the CMOS circuit. In addition, a source region 236, a drain region 237, an LDD region 238a and 238b, and channel formation regions 239a and 239b of the pixel TFT are defined.
[0087]
Further, a lower electrode 240 of the storage capacitor is defined. In this embodiment, phosphorus is added to the lower electrode 240 of the storage capacitor at the same concentration as the source region or the drain region in both the first phosphorus addition (n +) step and the second phosphorus addition (n−) step. . Therefore, it becomes a semiconductor region having the same composition as the source region or drain region of the NTFT.
[0088]
In this step, a low-concentration impurity region 241 is also formed in the region that becomes the PTFT of the CMOS circuit, similarly to the NTFT.
[0089]
Next, the region other than the region that becomes the PTFT of the CMOS circuit is hidden by the resist masks 242a and 242b, and an element belonging to group 13 of the periodic table (boron in this embodiment) is added. In this step, boron having a higher concentration than phosphorus already added is added. Specifically, 1 × 10²⁰~ 3x10^{twenty one}atoms / cm^ThreeAdjust the concentration so that boron is added. In this specification, the boron concentration at this time is represented by (p ++). As a result, all of the impurity regions exhibiting N-type conductivity formed in the region to be PTFT are inverted in conductivity type by boron, and become impurity regions exhibiting P-type conductivity. (Figure 3 (C))
[0090]
Of course, in this step, an ion implantation method that performs mass separation may be used, or a plasma doping method that does not perform mass separation may be used. The practitioner may set optimum values for the acceleration voltage, the dose amount, and the like.
[0091]
By this step, a source region 244, a drain region 245, and a channel formation region 246 of the PTFT forming the CMOS circuit are defined. In addition, the drain region 243 of the NTFT of the CMOS circuit is defined.
[0092]
When all the impurity regions are thus formed, the resist masks 242a and 242b are removed. And the heat processing process for 20 minutes-12 hours is performed in the temperature range of 750-1150 degreeC. In this embodiment, heat treatment is performed at 950 ° C. for 2 hours in an inert atmosphere. (Fig. 5 (A))
[0093]
In this process, phosphorus or boron added to each impurity region is activated, and at the same time, the LDD region is expanded inward (in the direction of the channel formation region).Sandwiching the gate insulating filmRealize the overlapping structure.
[0094]
That is, phosphorus contained in the LDD region 247 diffuses toward the channel formation region 248 in the LDD region 247 of the driving TFT. As a result, the LDD region 247 is connected to the gate wiring 220.With a gate insulating film in betweenOverlapping state. Such a structure is very effective in preventing deterioration due to hot carrier injection.
[0095]
Similarly, in the PTFT of the driving TFT, the source region 249 and the drain region 250 are diffused in the direction of the channel formation region 251 and overlap the gate wiring 221. In the pixel TFT, the LDD regions 252a and 252b diffuse in the direction of the channel formation regions 253a and 253b, respectively, and overlap the gate wirings 222a and 222b, respectively.
[0096]
The impurity diffusion distance can be controlled by the temperature and time of the heat treatment.
Therefore, the distance (length) at which the LDD region (or the source region and drain region of the PTFT) overlaps with the gate wiring can be freely controlled. In this embodiment, the overlap distance is adjusted to be 0.05 to 1 μm (preferably 0.1 to 0.3 μm).
[0097]
In addition, phosphorus added to the upper electrode 254 of the storage capacitor is activated by this process, and becomes a region exhibiting N-type conductivity. That is, the voltage is applied to the lower electrode 103 of the storage capacitor.In addition, without inducing carriersThe semiconductor film can function as the upper electrode 254.
[0098]
When the state of FIG. 5A is thus obtained, a first interlayer insulating film 255 is formed.
In this embodiment, a 1 μm thick silicon oxide film formed by plasma CVD is used. Then, after forming the contact holes, source wirings 256 to 258 and drain wirings 259 and 260 are formed. These wirings are formed by a laminated film in which a conductive film mainly composed of aluminum is sandwiched between titanium films.
[0099]
When the source wiring and the drain wiring are formed, hydrogenation is performed here. In this step, the entire substrate is exposed to hydrogen excited (activated) by plasma or heat. The temperature of the hydrogenation treatment may be 350 to 450 ° C. (preferably 380 to 420 ° C.) when excited by heat.
[0100]
Thereafter, a passivation film 261 is formed. As the passivation film 261, a silicon nitride film, a silicon oxynitride film, a silicon nitride oxide film, or a stacked film of these insulating films and a silicon oxide film can be used. In this embodiment, a silicon nitride film having a thickness of 300 nm is used as a passivation film.
[0101]
In this embodiment, as a pretreatment for forming the silicon nitride film, a plasma treatment using ammonia gas is performed, and the passivation film 261 is formed as it is. Hydrogen activated (excited) by the plasma by this pretreatment is confined by the passivation film 261. Further, when a nitrous oxide gas is added in addition to a gas containing hydrogen, the surface of the object to be processed is cleaned by the generated moisture, and contamination by boron or the like contained in the atmosphere can be effectively prevented.
[0102]
After the passivation film 261 is formed in this way, a heat treatment step of about 400 to 420 ° C. is performed here. The treatment atmosphere may be an inert atmosphere or an atmosphere containing hydrogen. In this step, hydrogen released from the silicon nitride film 261 and hydrogen contained in a large amount in the first interlayer insulating film 255 by the previous hydrogenation step diffuse downward (the passivation film 261 is in the upward direction). It becomes the blocking layer) and the active layer(Semiconductor film)Is hydrogen terminated. As a result, the dangling bonds in the active layer can be inactivated efficiently.
[0103]
When this hydrogenation process is completed, an acrylic film having a thickness of 1 μm is formed as the second interlayer insulating film 262. Then, a titanium film having a thickness of 200 nm is formed thereon and patterned to form a black mask 263.
[0104]
Next, an acrylic film having a thickness of 1 μm is formed again as the third interlayer insulating film 264 to form a contact hole, and a pixel electrode 265 made of an ITO film is formed. Thus, an AM-LCD having a structure as shown in FIG. 5B is completed.
[0105]
In the AM-LCD of the present invention, the thickness of the gate insulating film differs between the drive circuit portion (or signal processing circuit portion) and the pixel portion formed on the same substrate. Typically, the driving TFT used in the driving circuit portion has a thinner gate insulating film than the pixel TFT used in the pixel portion.
[0106]
Furthermore, in the pixel portion, a light shielding film is provided below the pixel TFT, and a thick base film is formed.(First insulation film)The formation of the parasitic capacitance is prevented by providing the gap between them. In addition, the underlying film is selectively removed at the portion that becomes the storage capacitor, and a thin dielectric is again formed.(Second insulating film)A storage capacity having a large capacity is formed.
[0107]
Further, according to the manufacturing process of this embodiment, the final active layer (semiconductor film) of the TFT is formed of a crystalline silicon film having a unique crystal structure having continuity in the crystal lattice. The features will be described below.
[0108]
FirstThe first feature is that of this embodiment.The microcrystalline silicon film formed in accordance with the manufacturing process has a crystal structure in which a plurality of needle-like or rod-like crystals (hereinafter abbreviated as rod-like crystals) are gathered and arranged. This can be easily confirmed by observation with TEM (transmission electron microscopy).
[0109]
Also,The second feature is that the surface of the crystalline silicon film formed according to the manufacturing process of this embodiment (the part where the channel is formed) is slightly misaligned in the crystal axis when electron diffraction is used. {110} plane can be confirmed. This means that the spot diameter is about 1.35μ. m Is observed from the fact that diffraction spots having regularity specific to the {110} plane appear. It has also been confirmed that each spot has a concentric distribution.
[0110]
As a third feature, when the orientation ratio is calculated using an X-ray diffraction method (strictly, an X-ray diffraction method using the θ-2θ method), the orientation ratio of the {220} plane is 0.7. It is confirmed that it is above (typically 0.85 or more). In addition, the method described in Unexamined-Japanese-Patent No. 7-321339 is used for the calculation method of orientation ratio.
[0111]
Also,As the fourth feature,The present applicant observes a crystal grain boundary formed by contact of individual rod-like crystals with HR-TEM (high resolution transmission electron microscopy), and confirms that the crystal lattice has continuity at the crystal grain boundary. . This can be easily confirmed because the observed lattice fringes are continuously connected at the grain boundaries.
[0112]
Note that the continuity of the crystal lattice at the crystal grain boundary results from the fact that the crystal grain boundary is a grain boundary called a “planar grain boundary”. The definition of the planar grain boundary in this specification is “Characterization of High-Efficiency Cast-Si Solar Cell Wafers by MBIC Measurement; Ryuichi Shimokawa and Yutaka Hayashi, Japanese Journal of Applied Physics vol.27, No.5, pp.751”. -758, 1988 ”is the“ Planar boundary ”.
[0113]
According to the above paper, planar grain boundaries include twin grain boundaries, special stacking faults, and special twist grain boundaries. This planar grain boundary is characterized by being electrically inactive. That is, although it is a crystal grain boundary, it does not function as a trap that inhibits the movement of carriers, and thus can be regarded as substantially nonexistent.
[0114]
In particular, when the crystal axis (axis perpendicular to the crystal plane) is the <110> axis, the {211} twin grain boundary is also called a corresponding grain boundary of Σ3. The Σ value is a parameter that serves as a guideline indicating the degree of consistency of the corresponding grain boundary. It is known that the smaller the Σ value, the better the grain boundary.For example, in a crystal grain boundary formed between two crystal grains, if the plane orientation of both crystals is {110}, θ = the angle formed by lattice fringes corresponding to the {111} plane is θ = 70.5 It is known that it becomes a corresponding grain boundary of Σ3 when it is °.
[0115]
In the crystalline silicon film obtained by carrying out this example, when a crystal grain boundary formed between two crystal grains having a crystal axis <110> is observed by HR-TEM, each of adjacent crystal grains is observed. About plaid 70.5 Many are continuous at an angle of °. Therefore, it can be inferred that the grain boundary is the corresponding grain boundary of Σ3, that is, the {211} twin boundary.
[0116]
Such a crystal structure (exactly, the structure of the crystal grain boundary) indicates that two different crystal grains are joined with extremely good consistency at the crystal grain boundary. That is, the crystal lattice is continuously connected at the crystal grain boundary, and the trap level caused by crystal defects or the like is very difficult to create. Therefore, the semiconductor thin film having such a crystal structure can be regarded as having substantially no grain boundary.
[0117]
Furthermore, a heat treatment step at a high temperature of 700 to 1150 ° C. (in this exampleIn the thermal oxidation process), It has been confirmed by TEM observation that almost all defects present in the crystal grains have disappeared. This is also clear from the fact that the number of defects is greatly reduced before and after this heat treatment step.
[0118]
The difference in the number of defects appears as a difference in spin density by electron spin resonance analysis (Electron Spin Resonance: ESR). At present, the spin density of the crystalline silicon film fabricated according to the fabrication process of this example is at least 5 × 10¹⁷spins / cm^ThreeBelow (preferably 3 × 10¹⁷spins / cm^ThreeThe following): However, since this measured value is close to the detection limit of existing measuring devices, the actual spin density is expected to be even lower.
[0119]
From the above, the crystalline silicon film obtained by carrying out this embodiment is considered to be a single crystal silicon film or a substantially single crystal silicon film because there are substantially no crystal grains and no crystal grain boundaries. Good.
[0120]
(Knowledge about electrical characteristics of TFT)
The TFT fabricated using this example showed electrical characteristics comparable to a MOSFET. The following data is obtained from the TFT manufactured by the applicant of the present invention (however, the thickness of the active layer is 35 nm and the thickness of the gate insulating film is 80 nm).
[0121]
(1) Sub-threshold coefficient, which is an index of switching performance (agility of on / off operation switching), is 80 to 150 mV / decade for both N-channel and P-channel TFTs (typically 100 to 120 mV / decade) And small.
(2) Field-effect mobility (μ_FE) 150-650cm for N-channel TFT²/ Vs (typically 200-500cm²/ Vs), 100-300cm with P-channel TFT²/ Vs (typically 120-200cm²/ Vs).
(3) Threshold voltage (V_th) Is as low as -0.5 to 1.5 V for N-channel TFTs and -1.5 to 0.5 V for P-channel TFTs.
[0122]
As described above, it has been confirmed that extremely excellent switching characteristics and high-speed operation characteristics can be realized.
[0123]
[Example 2]
In this embodiment, a specific structure of TFTs arranged in which circuit will be described with reference to FIG.
[0124]
The minimum required operating voltage (power supply voltage) varies depending on the circuit of the AM-LCD.
For example, when considering the voltage applied to the liquid crystal and the voltage for driving the pixel TFT in the pixel portion, the operating voltage is 14 to 20V. Therefore, a TFT that can withstand such a high voltage must be used.
[0125]
An operation voltage of about 5 to 10 V is sufficient for a shift resist circuit used for a source driving circuit and a gate driving circuit. The lower the operating voltage, the more compatible with external signals, and the further advantage is that power consumption can be reduced. However, the high breakdown voltage TFT described above is not suitable for a circuit that requires high-speed operation, such as a shift register circuit, because the operation speed is sacrificed instead of good breakdown voltage characteristics.
[0126]
As described above, the circuit formed on the substrate is divided into a circuit for obtaining a TFT with an emphasis on breakdown voltage characteristics and a circuit for obtaining a TFT with an emphasis on operation speed according to the purpose.
[0127]
Here, the configuration of this embodiment is specifically shown in FIG. FIG. 6A shows a top view of the block diagram of the AM-LCD. Reference numeral 601 denotes a pixel portion, and each pixel includes a pixel TFT and a storage capacitor,imageFunctions as a display unit. Further, 602a is a shift register circuit, 602b is a level shifter circuit, and 602c is a buffer circuit. These circuits as a whole form a gate drive circuit.
[0128]
Note that in the AM-LCD shown in FIG. 6A, a gate driving circuit is provided with a pixel portion interposed therebetween and shares the same gate wiring, that is, one of the gate drives has a defect. However, redundancy is provided such that a voltage can be applied to the gate wiring.
[0129]
Reference numeral 603a denotes a shift register circuit, reference numeral 603b denotes a level shifter circuit, reference numeral 603c denotes a buffer circuit, and reference numeral 603d denotes a sampling circuit. These circuits form a source drive circuit as a whole. A precharge circuit 604 is provided on the opposite side of the source driver circuit across the pixel portion.
[0130]
In the AM-LCD configured as described above, the shift register circuits 602a and 603a are circuits that require high-speed operation, and the operation voltage is as low as 3.3 to 10 V (typically 3.3 to 5 V), and the high withstand voltage is high. No special properties are required. Therefore, the gate insulating film should be as thin as 5 to 50 nm (preferably 10 to 30 nm).
[0131]
FIG. 6B is a schematic diagram of a CMOS circuit to be used mainly for a circuit that requires high-speed operation, such as a shift register circuit or other signal processing circuits. In FIG. 6B, reference numeral 605a denotes an NTFT gate insulating film, and reference numeral 605b denotes a PTFT gate insulating film, which is designed to be as thin as 5 to 50 nm (preferably 10 to 30 nm).
[0132]
The length of the LDD region 606 is preferably 0.1 to 0.5 μm (typically 0.2 to 0.3 μm). If the operating voltage is sufficiently low, such as 2 to 3 V, the LDD region can be omitted.
[0133]
Next, the CMOS circuit illustrated in FIG. 6C is suitable mainly for the level shifter circuits 602b and 603b, the buffer circuits 602c and 603c, the sampling circuit 603d, and the precharge circuit 604. Since these circuits require a large current to flow, the operating voltage is as high as 14 to 16V. In particular, on the gate driving side, an operating voltage of 19V may be required depending on circumstances. Therefore, a TFT having a very good breakdown voltage characteristic (high breakdown voltage characteristic) is required.
[0134]
At this time, in the CMOS circuit shown in FIG. 6C, the film thicknesses of the NTFT gate insulating film 607a and PTFT gate insulating film 607b are designed to be 50 to 200 nm (preferably 100 to 150 nm). In such a circuit that requires good breakdown voltage characteristics, it is preferable that the gate insulating film be thicker than a TFT such as the shift register circuit shown in FIG.
[0135]
The length of the LDD region 608 is preferably 0.5 to 3 μm (typically 2 to 2.5 μm). Since the CMOS circuit shown in FIG. 6C is applied with a high voltage similar to that of a pixel like a buffer circuit or the like, it is desirable that the length of the LDD region be the same as or close to that of the pixel.
[0136]
Next, FIG. 6D is a schematic diagram of the pixel portion 601. Since the pixel TFT takes into account the voltage applied to the liquid crystal, an operating voltage of 14 to 16 V is required. In addition, since the charge accumulated in the liquid crystal and the storage capacitor must be held for one frame period, the off current must be as small as possible.
[0137]
For this reason, in this embodiment, a double gate structure using NTFT is used, and the thickness of the gate insulating film 609 is 50 to 200 nm (preferably 100 to 150 nm). This film thickness may be the same film thickness as the CMOS circuit shown in FIG. 6C, or may be a different film thickness.
[0138]
Note that the thickness of the storage capacitor dielectric 610 may be 5 to 75 nm (preferably 20 to 50 nm).
[0139]
The length of the LDD regions 611a and 611b is preferably 1 to 4 μm (typically 2 to 3 μm). Since a high voltage of 14 to 16 V is applied to the pixel TFT shown in FIG. 6D, the length of the LDD region needs to be increased.
[0140]
In addition, since it is necessary for the pixel TFT to reduce off current (drain current that flows when the TFT is in an off state) as much as possible, a region that does not overlap with the gate wiring in the LDD regions 611a and 611b (functions as a normal LDD region). It is desirable to secure 1 to 3 μm.
[0141]
As described above, even with an AM-LCD as an example, various circuits are provided on the same substrate, and the required operating voltage (power supply voltage) may differ depending on the circuit. In this case, as in the present inventionIn the drive circuit section and the pixel sectionGate insulation film thicknessOr the length of the LDD regionIt is effective to arrange TFTs having different values.
[0142]
In order to realize the configuration of this embodiment, it is effective to use the circuit shown in Embodiment 1.
[0143]
Example 3
In the first embodiment, in the step of selectively removing the gate insulating film, the removal in the region to be the driving TFT is desirably performed as shown in FIG. In FIG. 7, reference numeral 701 denotes an active layer, 702 denotes an end portion of a gate insulating film 217, and 703 and 704 denote gate wirings. As shown in FIG. 7, it is desirable to leave a gate insulating film at the end of the active layer 701 in the portion 705 where the gate wiring crosses the active layer.
[0144]
A phenomenon called edge thinning occurs at the end of the active layer 701 when a thermal oxidation process is performed later. This is a phenomenon in which the oxidation reaction proceeds so as to sink under the edge of the active layer, and the edge becomes thinner and rises at the same time. Therefore, when the edge thinning phenomenon occurs, there arises a problem that the gate wiring easily breaks when the gate wiring is overcome.
[0145]
However, if the gate insulating film is removed so that the structure as shown in FIG. 7 is obtained, the edge thinning phenomenon can be prevented in the portion 705 where the gate wiring crosses over. Therefore, problems such as disconnection of the gate wiring can be prevented in advance. Note that it is effective to use the configuration of this embodiment in the first embodiment.
[0146]
Example 4
In this embodiment, a structure in which the capacitor wiring formed simultaneously with the gate wiring is used as the electrode of the storage capacitor in the AM-LCD having the structure shown in FIG. 1 will be described with reference to FIG.
[0147]
In the case of the structure of FIG. 8, the first storage capacitor is formed by the first electrode 801, the first dielectric 802 and the second electrode 803, and the second is formed by the second electrode 803, the second dielectric 804 and the third electrode 805. Is formed. At this time, the second dielectric 804 is an extension of the gate insulating film, and the third electrode 805 is formed simultaneously with the gate wiring.
[0148]
By connecting the two holding capacitors in parallel in this way, a holding capacitor having a larger capacity can be realized. In this case, the first electrode 801 and the third electrode 805 may be set at a fixed potential. Both fixed potentials may be set to the same potential.
[0149]
The structure of the present embodiment can be realized only by providing the third electrode in the first embodiment, and the configuration of the present embodiment and the configurations of the second and third embodiments may be combined in any way.
[0150]
Example 5
In this embodiment, a case will be described in which a TFT is formed on a substrate in the manufacturing process shown in Embodiment 1 and an AM-LCD is actually manufactured.
[0151]
When the state of FIG. 5B is obtained, an alignment film is formed on the pixel electrode 265 to a thickness of 80 nm. Next, a glass substrate with a color filter, a transparent electrode (counter electrode), and an alignment film formed thereon is prepared as a counter substrate, and each alignment film is rubbed and a sealing material (sealing material) is used. The substrate on which the TFT is formed is bonded to the counter substrate. In the meantime, the liquid crystal is held. Since this cell assembling process may use a known means, a detailed description thereof will be omitted.
[0152]
In addition, what is necessary is just to provide the spacer for maintaining a cell gap as needed.
Therefore, when the cell gap can be maintained without the spacer as in the AM-LCD having a diagonal of 1 inch or less, it is not particularly necessary.
[0153]
Next, the appearance of the AM-LCD manufactured as described above is shown in FIG. An active matrix substrate (referred to as a substrate on which a TFT is formed) 11 includes a pixel portion 12, a source drive circuit 13, a gate drive circuit 14, a signal processing circuit (signal division circuit, D / A converter circuit, γ correction circuit, differential) Amplifying circuit or the like) 15 is formed, and an FPC (flexible printed circuit) 16 is attached. Reference numeral 17 denotes a counter substrate.
[0154]
In addition, a present Example can be freely combined with any Example of Examples 1-4.
[0155]
Example 6
In this embodiment, a case where another means is used for forming the crystalline silicon film in Embodiment 1 will be described.
[0156]
Specifically, the technique described in Example 2 of Japanese Patent Laid-Open No. 7-130652 (corresponding to US Pat. No. 08 / 329,644) is used for crystallization of the amorphous silicon film. In the technique described in the publication, a catalyst element (typically nickel) that promotes crystallization is selectively held on the surface of an amorphous silicon film, and that portion is used as a seed for nucleus growth for crystallization. Technology.
[0157]
According to this technique, since the crystal growth can have a specific direction, it is possible to form a crystalline silicon film having very high crystallinity.
[0158]
It is also possible to use a mask insulating film provided for selectively holding the catalytic element as a phosphorus mask added for gettering. By doing so, the number of steps can be reduced. This technique is detailed in Japanese Patent Application Laid-Open No. 10-247735 (corresponding to US Application No. 09 / 034,041) by the present applicant.
[0159]
In addition, the structure of a present Example can be freely combined with any structure of Examples 1-5.
[0160]
Example 7
In this embodiment, an example in which a storage capacitor having a structure different from that in Embodiment 1 is formed will be described with reference to FIG. Specifically, an oxide film obtained by oxidizing the lower electrode of the storage capacitor is used as the dielectric of the storage capacitor.
[0161]
First, the light shielding film 21 and the lower electrode 22 of the storage capacitor are formed on the substrate. As the material, a material similar to that described in Embodiment 1 can be used. However, in this embodiment, a material capable of forming a high-quality insulating film by oxidizing at least the upper surface is preferable.
[0162]
In this embodiment, a laminated film having a three-layer structure of silicon film / tungsten film (or tungsten silicide film) / silicon film is used from the lower layer. In addition, a three-layer structure of tantalum film / tantalum nitride film / tantalum film from the lower layer is effective.
[0163]
When the light shielding film 21 and the lower electrode 22 of the storage capacitor are thus formed, oxide films 23 and 24 are formed on the surface by heat treatment, plasma treatment or anodizing treatment. In this embodiment, this oxide film is a silicon oxide film and is formed by heat treatment at 900 ° C. for 30 minutes. The formation conditions of the oxide films 23 and 24 may be selected appropriately depending on the required film thickness and film quality of the oxide film.
[0164]
Thus, the storage capacitor of this embodiment is formed by the lower electrode 22 of the storage capacitor, the thermal oxide film (silicon oxide film) 24 and the upper electrode (semiconductor film) 25 of the storage capacitor.
[0165]
When a three-layer structure of tantalum film / tantalum nitride film / tantalum film is used as the lower electrode 22 of the storage capacitor from the lower layer, the formed oxide film 24 is a tantalum oxide film and has a very high relative dielectric constant. A dielectric is obtained. Therefore, it is possible to secure a capacity with a very large capacity even in a small area.
[0166]
The present embodiment configured as described above can be freely combined with any of the first to sixth embodiments.
[0167]
Example 8
In this embodiment, an example in which a storage capacitor having a structure different from that in Embodiment 1 is formed will be described with reference to FIG. Specifically, a tantalum oxide film is used as the dielectric of the storage capacitor.
[0168]
In FIG. 12, 26 is a light shielding film, 27 is a lower electrode of a storage capacitor, and 28 is a base film made of a silicon oxide film. These materials may be referred to Example 1. In this embodiment, after providing an opening in the base film 28, a tantalum oxide film 29 is formed by sputtering. The film thickness may be 10 to 100 nm (preferably 30 to 50 nm).
[0169]
Note that after the opening is provided, the exposed lower electrode 27 of the storage capacitor may be oxidized by heat treatment, plasma treatment or anodizing treatment to form a tantalum oxide film.
[0170]
When the tantalum oxide film 29 is thus formed, a thin silicon oxide film 30 having a thickness of about 10 nm and an upper electrode 31 having a storage capacitor are formed. At this time, it is desirable that the silicon oxide film 30 and the amorphous silicon film (semiconductor film to be an upper electrode of the storage capacitor later) be continuously formed without being released to the atmosphere. As a result, it is possible to prevent the lower surface of the active layer connected to the upper electrode of the storage capacitor from being contaminated with boron or the like in the atmosphere.
[0171]
The silicon oxide film 30 also serves as a barrier layer that prevents the tantalum oxide film 29 and the upper electrode 31 of the storage capacitor made of a semiconductor film (specifically, a silicon film) from interacting with each other.
[0172]
As described above, in the structure of this embodiment, the laminated film of the tantalum oxide film 29 and the silicon oxide film 30 is used as the dielectric of the storage capacitor. Moreover, since the relative dielectric constant of the tantalum oxide film 29 is as large as about 25, a sufficiently large capacity can be obtained even when the film thickness is about 100 nm. However, if it is made as thin as possible in consideration of the withstand voltage, it is preferably 30 to 50 nm.
[0173]
The present embodiment having the above configuration can be freely combined with any of the first to seventh embodiments.
[0174]
Example 9
In this embodiment, an example in which a storage capacitor having a structure different from that in Embodiment 1 is formed will be described with reference to FIG. Specifically, an insulating film serving as an etching stopper is provided before forming the dielectric of the storage capacitor.
[0175]
In FIG. 13, 32 is a light shielding film, 33 is a lower electrode of a storage capacitor, and a tantalum oxide film 34 having a thickness of 20 nm is formed so as to cover them. The materials of the light shielding film 32 and the lower electrode 33 of the storage capacitor may be in accordance with the first embodiment. The tantalum oxide film may be obtained by oxidizing the lower electrode 33 of the storage capacitor or may be formed by sputtering.
[0176]
A base film 35 made of a silicon oxide film is formed thereon, and an opening is formed in the base film 35. At this time, since the etching of the base film 35 is completely stopped by the tantalum oxide film 34, the underlying electrode 33 is not etched, and the film thickness at the opening of the tantalum oxide film 34 may be uniform. it can.
[0177]
When the opening is thus formed, a storage capacitor dielectric (silicon oxide film in this embodiment) 36 is formed thereon, and a storage capacitor upper electrode (semiconductor film) 37 is formed thereon.
[0178]
In this embodiment, an example in which a tantalum oxide film is used as an etching stopper and a silicon oxide film is used as a base film is shown. ), Other combinations of insulating films can be used.
[0179]
For example, when a silicon oxide film is used as the base film, a silicon nitride film can be used as an etching stopper.
[0180]
In this embodiment, after an opening is formed in the base film 35, a silicon oxide film is provided again as a dielectric for the storage capacitor. However, only a tantalum oxide film used as an etching stopper serves as a dielectric for the storage capacitor. It is also possible. However, in this case, it is desirable to provide a thin silicon oxide film as a barrier layer between the tantalum oxide film and the upper electrode of the storage capacitor made of the semiconductor film.
[0181]
Of course, even when a silicon nitride film is used as an etching stopper, it is possible to use the silicon nitride film alone as a dielectric for a storage capacitor without forming any other dielectric.
[0182]
The present embodiment configured as described above can be freely combined with any of the first to eighth embodiments.
[0183]
Example 10
Phosphorus was used to getter nickel (catalyst element used to crystallize the silicon film) described in the first embodiment. In this embodiment, nickel is gettered using other elements. explain.
[0184]
First, according to the process of Example 1, the state of FIG. In FIG. 2B, reference numeral 208 denotes a crystalline silicon film. However, in this embodiment, the concentration of nickel used for crystallization is made as low as possible. Specifically, a layer containing nickel of 0.5 to 3 ppm in terms of weight is formed on the amorphous silicon film, and heat treatment for crystallization is performed. The nickel concentration contained in the crystalline silicon film thus formed is 1 × 10¹⁷~ 1x10¹⁹atoms / cm^Three(Typically 5 × 10¹⁷~ 1x10¹⁸atoms / cm^Three)
[0185]
After the crystalline silicon film is formed, heat treatment is performed in an oxidizing atmosphere containing a halogen element. The temperature is 800 to 1150 ° C. (preferably 900 to 1000 ° C.), and the treatment time is 10 minutes to 4 hours (preferably 30 minutes to 1 hour).
[0186]
In this embodiment, heat treatment is performed at 950 ° C. for 30 minutes in an atmosphere containing 3 to 10% by volume of hydrogen chloride with respect to the oxygen atmosphere.
[0187]
By this step, nickel in the crystalline silicon film becomes volatile nickel chloride and is released into the processing atmosphere. That is, nickel can be removed by the gettering action of the halogen element. However, if the concentration of nickel present in the crystalline silicon film is too high, there arises a problem that oxidation proceeds abnormally at the segregated portion of nickel.
Therefore, it is necessary to reduce the concentration of nickel used in the crystallization stage as much as possible.
[0188]
In addition, the structure of a present Example can be freely combined with any structure of Example 1- Example 9. FIG.
[0189]
Example 11
In this embodiment, a case where the CMOS circuit and the pixel portion shown in Embodiment 1 are different in structure will be described. Specifically, an example is shown in which the arrangement of the LDD regions is varied according to the specifications required by the circuit.
[0190]
Since the basic structure of the CMOS circuit and the pixel portion has already been shown in FIG. 1, in the present embodiment, only necessary portions will be described with reference numerals.
[0191]
First, the circuit shown in FIG. 14A is a CMOS circuit for a buffer circuit in which NTFT has a double gate structure and PTFT has a single gate structure. In this embodiment, the source-side LDD regions 41a and 41b are formed in a self-aligned manner using only the sidewalls as a mask, and the drain-side LDD regions 42a and 42b are formed using a resist mask to form the source-side LDD regions 41a and 41b. It is characterized in that the width (length) is larger than 41b.
[0192]
Since a CMOS circuit used for a drive circuit or a signal processing circuit is required to operate at high speed, it is necessary to eliminate as much as possible a resistance component that may cause a decrease in the operation speed.
However, since the LDD region necessary for increasing the hot carrier resistance acts as a resistance component, the operation speed is sacrificed.
[0193]
However, hot carrier injection occurs at the end of the channel formation region on the drain region side, and if there is an LDD region overlapping the gate electrode with the gate insulating film in between, sufficient countermeasures against hot carriers are sufficient. Therefore, it is not always necessary to provide an LDD region more than necessary at the end of the channel formation region on the source region side.
[0194]
Note that the structure of FIG. 14A cannot be applied to the case of operation like a pixel TFT in which a source region and a drain region are interchanged. In the case of a CMOS circuit, since the source region and the drain region are usually fixed, a structure as shown in FIG. 14A can be realized.
[0195]
With such a structure, the resistance component due to the LDD region on the source region side is eliminated, and the double gate structure has an effect of dispersing and relaxing the electric field applied between the source and the drain.
[0196]
Next, the structure of FIG. 14B is an embodiment of a pixel portion. In the case of the structure of FIG. 14B, the LDD regions 43a and 43b are provided only on one side close to the source region or the drain region. That is, the LDD region is not provided between the two channel forming regions 44a and 44b.
[0197]
In the case of the pixel TFT, the source region and the drain region are frequently switched because an operation of repeating charging and discharging is performed. Therefore, the structure shown in FIG. 14B has a structure in which an LDD region is provided on the drain region side of the channel formation region regardless of which is the drain region. Conversely, since there is no electric field concentration in the region between the channel formation regions 44a and 44b, it is effective to increase the on-current (current that flows when the TFT is in the on state) by eliminating the LDD region that is a resistance component. is there.
[0198]
In addition, the structure of a present Example can be freely combined with any structure of Examples 1-10.
[0199]
Example 12
In this embodiment, an embodiment relating to a position where a storage capacitor is formed in the pixel portion will be described. 15A and 15B are used for the description. FIG. 15B is a cross-sectional view taken along A-A ′ of FIG. Further, the same reference numerals are used for the same portions in FIGS.
[0200]
In FIG. 15A, 51 is a lower electrode of a storage capacitor formed simultaneously with the light shielding film, 52 is a semiconductor film, 53 is a gate wiring, 54 is a source wiring, and 55 is a drain wiring (drain electrode).
[0201]
The lower electrode 51 of the storage capacitor is formed so as to overlap below the gate wiring 53 and the source wiring 54, and has a mesh (matrix) pattern shape. That is, the entire lower electrode 51 of the storage capacitor is at the same potential (preferably the lowest power supply potential).
[0202]
A semiconductor film 52 is formed thereon via a base film 56 and an insulating film 57 serving as a dielectric of a storage capacitor. In the storage capacitor portion, the base film 56 is removed, and the storage capacitor is formed by the lower electrode 51 of the storage capacitor, the insulating film 57, and the semiconductor film 52.
[0203]
This embodiment is characterized in that the storage capacitor portion is formed below the gate wiring 53 and below the source wiring 54. By doing so, the aperture ratio is improved and bright image display is possible. In addition, since it is possible to prevent light from being applied to the storage capacitor, leakage of electric charge from the storage capacitor can be prevented.
[0204]
In this embodiment, the semiconductor film is patterned so that the pixel TFT has a triple gate structure, but this embodiment is not limited to this.
[0205]
In addition, the configuration of this embodiment can be freely combined with any embodiment of Embodiments 1-11.
[0206]
Example 13
In this embodiment, an embodiment relating to a position where a storage capacitor is formed in the pixel portion will be described. 16A and 16B are used for the description. Note that FIG. 16B is a cross-sectional view taken along A-A ′ of FIG. Further, the same reference numerals are used for the same portions in FIGS.
[0207]
In FIG. 16A, 61 is a lower electrode of a storage capacitor formed simultaneously with the light shielding film, 62 is a semiconductor film, 63 is a gate wiring, 64 is a source wiring, and 65 is a drain wiring (drain electrode).
[0208]
The lower electrode 61 of the storage capacitor is formed so as to overlap below the source wiring 64 and has a mesh pattern (matrix shape). That is, the entire lower electrode 61 of the storage capacitor is at the same potential (preferably the lowest power supply potential).
[0209]
A semiconductor film 62 is formed thereover via a base film 66 and an insulating film 67 serving as a dielectric of a storage capacitor. In the storage capacitor portion, the base film 66 is removed, and a storage capacitor is formed by the lower electrode 61 of the storage capacitor, the insulating film 67, and the semiconductor film 62.
[0210]
This embodiment is characterized in that this storage capacitor portion is formed below the source wiring 64. By doing so, the aperture ratio is improved and bright image display is possible. In addition, since it is possible to prevent light from being applied to the storage capacitor, leakage of electric charge from the storage capacitor can be prevented.
[0211]
In this embodiment, the semiconductor film is patterned so that the pixel TFT has a triple gate structure, but this embodiment is not limited to this.
[0212]
In addition, the configuration of this embodiment can be freely combined with any embodiment of Embodiments 1-11.
[0213]
Example 14
In this embodiment, an embodiment relating to a position where a storage capacitor is formed in the pixel portion will be described. FIG. 17 is used for the description.
[0214]
In FIG. 17, reference numeral 71 denotes a lower electrode of a storage capacitor, 72 denotes a semiconductor film, 73a and 73b denote gate wirings, 74 denotes a source wiring, and 75 denotes a drain wiring.
[0215]
The lower electrode 71 of the storage capacitor is formed so as to overlap below the gate wirings 73a and 73b and the source wiring 74, and has a mesh pattern (matrix shape). That is, the entire lower electrode 71 of the storage capacitor is at the same potential (preferably the lowest power supply potential).
[0216]
On top of this, a semiconductor film 72 is formed via a base film and a storage capacitor dielectric. In the storage capacitor portion, the base film is removed, and the storage capacitor is formed by the lower electrode 71 of the storage capacitor, the storage capacitor dielectric, and the semiconductor film 72.
[0217]
This embodiment is characterized in that the storage capacitor portion is formed below the second wiring 73 b and below the source wiring 74. The difference from the twelfth and thirteenth embodiments is that, when a storage capacitor is formed under the gate wiring, the lower part of the unselected gate wiring (the gate wiring 73b adjacent to the selected gate wiring 73a) is used.
[0218]
In the case of the present embodiment, when the charge is stored in the storage capacitor portion, the gate wiring thereon is not selected, so that it is possible to prevent the charge stored in the storage capacitor from fluctuating due to the parasitic capacitance.
[0219]
In addition, with such a structure, the aperture ratio is improved and bright image display is possible. In addition, since it is possible to prevent light from being applied to the storage capacitor, leakage of electric charge from the storage capacitor can be prevented.
[0220]
In this embodiment, the semiconductor film is patterned so that the pixel TFT has a triple gate structure, but this embodiment is not limited to this.
[0221]
In addition, the configuration of this embodiment can be freely combined with any embodiment of Embodiments 1-11.
[0222]
Example 15
In this embodiment, an example in which the first interlayer insulating film is formed by a method different from that in Embodiment 1 will be described. FIG. 18 is used for the description.
[0223]
First, the process up to the activation process shown in FIG. Next, a silicon nitride oxide film (A) 1801 having a thickness of 50 to 100 nm (70 nm in this embodiment) is formed, and 600 nm to 1 μm is formed thereon. m A silicon nitride oxide film (B) 1802 is formed (800 nm in this embodiment). Further, a resist mask 1803 is formed thereon. (FIG. 18 (A))
[0224]
Note that the silicon nitride oxide film (A) 1801 and the silicon nitride oxide film (B) 1802 have different composition ratios of nitrogen, oxygen, hydrogen, and silicon. The silicon nitride oxide film (A) 1801 is 7% nitrogen, 59% oxygen, 2% hydrogen, and 32% silicon, and the silicon nitride oxide film (B) 1802 is 33% nitrogen, 15% oxygen, 23% hydrogen, Silicon is 29%. Of course, it is not limited to this composition ratio.
[0225]
Further, since the resist mask 1803 is thick, the surface undulation of the silicon nitride oxide film (B) 1802 can be completely planarized.
[0226]
Next, the resist mask 1803 and the silicon nitride oxide film (B) 1802 are etched by a dry etching method using a mixed gas of carbon tetrafluoride and oxygen. In the case of this embodiment, in dry etching using a mixed gas of carbon tetrafluoride and oxygen, the etching rates of the silicon nitride oxide film (B) 1802 and the resist mask 1803 are substantially equal.
[0227]
By this etching step, the resist mask 1803 is completely removed as shown in FIG. 18B, and a part of the silicon nitride oxide film (B) 1802 (from the surface to a depth of 300 nm in this embodiment) is etched. As a result, the flatness of the surface of the resist mask 1803 is directly reflected in the flatness of the surface of the etched silicon nitride oxide film (B).
[0228]
In this way, the first interlayer insulating film 1804 having extremely high flatness is obtained. In this embodiment, the thickness of the first interlayer insulating film 1804 is 500 nm. For the subsequent steps, the manufacturing steps of Embodiment 1 may be referred to.
[0229]
In addition, the structure of a present Example can be freely combined with any Example of Examples 1-14.
[0230]
Example 16
The present invention can also be used when an interlayer insulating film is formed on a conventional MOSFET and a TFT is formed thereon. That is, it is also possible to realize a three-dimensional semiconductor device in which a reflective AM-LCD is formed on a semiconductor circuit.
[0231]
The semiconductor circuit may be formed on an SOI substrate such as SIMOX, Smart-Cut (registered trademark of SOITEC), ELTRAN (registered trademark of Canon Inc.), or the like.
[0232]
In addition, when implementing a present Example, you may combine any structure of Examples 1-14.
[0233]
Example 17
The present invention can also be applied to an active matrix EL display. An example is shown in FIG.
[0234]
FIG. 19 is a circuit diagram of an active matrix EL display. Reference numeral 81 denotes a display area, and an X direction (gate) drive circuit 82 and a Y direction (source) drive circuit 83 are provided around the display area. Each pixel in the display area 81 includes a switching TFT 84, a capacitor 85, a current control TFT 86, and an EL element 87. The switching TFT 84 has an X direction (gate) signal line 88a (or 88b) and a Y direction (source). ) The signal line 89a (or 89b, 89c) is connected. Further, power supply lines 90 a and 90 b are connected to the current control TFT 86.
[0235]
Note that the switching TFT 84 may be an n-channel TFT or a p-channel TFT. The current control TFT 86 may be an n-channel TFT or a p-channel TFT. When an n-channel TFT is used, the EL element 87 is used as a cathode. When a p-channel TFT is used, an EL element 87 is used as an anode. Connect. Note that a resistor or a TFT may be provided between the EL element 87 and the current control TFT 86.
[0236]
In the active matrix EL display of this embodiment, the gate insulating films of TFTs used in the X direction driving circuit 82 and the Y direction driving circuit 83 are thinner than the gate insulating films of the switching TFT 84 and the current control TFT 86. . Further, the capacitor 85 is formed with a storage capacitor having the structure described in the first, fourth, and seventh to ninth embodiments.
[0237]
In addition, you may combine any structure of Examples 1-16 with respect to the active matrix type EL display of a present Example.
[0238]
Example 18
In this example, an example in which an EL (electroluminescence) display device is manufactured using the present invention will be described. 20A is a top view of the EL display device of the present invention, and FIG. 20B is a cross-sectional view thereof.
[0239]
20A, reference numeral 4001 denotes a substrate, 4002 denotes a pixel portion, 4003 denotes a source side driver circuit, and 4004 denotes a gate side driver circuit. Each driver circuit reaches an FPC (flexible printed circuit) 4006 through a wiring 4005 Connected to an external device.
[0240]
At this time, a first sealant 4101, a cover material 4102, a filler 4103, and a second sealant 4104 are provided so as to surround the pixel portion 4002, the source side driver circuit 4003, and the gate side driver circuit 4004.
[0241]
20B corresponds to a cross-sectional view taken along line AA ′ of FIG. 20A. A driving TFT included in the source side driver circuit 4003 over the substrate 4001 (here, an n-channel type is used here). TFTs and p-channel TFTs are illustrated) 4201 and pixel TFTs included in the pixel portion 4002 (however, here, TFTs for controlling current to EL elements are illustrated) 4202 are formed. .
[0242]
In this embodiment, a TFT having the same structure as that of the drive circuit in FIG. Further, a TFT having the same structure as that of the pixel portion in FIG.
[0243]
An interlayer insulating film (planarization film) 4301 made of a resin material is formed on the driving TFT 4201 and the pixel TFT 4202, and a pixel electrode (cathode) 4302 electrically connected to the drain of the pixel TFT 4202 is formed thereon. As the pixel electrode 4302, a conductive film having a light-blocking property (typically, a conductive film containing aluminum, copper, or silver as its main component or a stacked film of these and another conductive film) can be used. In this embodiment, an aluminum alloy is used as the pixel electrode.
[0244]
An insulating film 4303 is formed over the pixel electrode 4302, and an opening is formed in the insulating film 4303 over the pixel electrode 4302. In this opening, an EL (electroluminescence) layer 4304 is formed on the pixel electrode 4302. A known organic EL material or inorganic EL material can be used for the EL layer 4304. The organic EL material includes a low molecular (monomer) material and a high molecular (polymer) material, either of which may be used.
[0245]
A known technique may be used for forming the EL layer 4304. The EL layer may have a stacked structure or a single layer structure by freely combining a hole injection layer, a hole transport layer, a light emitting layer, an electron transport layer, or an electron injection layer.
[0246]
An anode 4305 made of a transparent conductive film is formed on the EL layer 4304. As the transparent conductive film, a compound of indium oxide and tin oxide or a compound of indium oxide and zinc oxide can be used. In addition, it is desirable to remove moisture and oxygen present at the interface between the anode 4305 and the EL layer 4304 as much as possible. Accordingly, it is necessary to devise such that the both are continuously formed in a vacuum, or the EL layer 4304 is formed in a nitrogen or rare gas atmosphere, and the anode 4305 is formed without being exposed to oxygen or moisture. In this embodiment, the above-described film formation is possible by using a multi-chamber type (cluster tool type) film formation apparatus.
[0247]
The anode 4305 is electrically connected to the wiring 4005 in the region indicated by 4306. A wiring 4005 is a wiring for applying a predetermined voltage to the anode 4305 and is electrically connected to the FPC 4006 through a conductive material 4307.
[0248]
As described above, an EL element including the pixel electrode (cathode) 4302, the EL layer 4304, and the anode 4305 is formed. The EL element is surrounded by a first sealing material 4101 and a cover material 4102 bonded to the substrate 4001 by the first sealing material 4101 and enclosed by a filler 4103.
[0249]
As the cover material 4102, a glass plate, an FRP (Fiberglass-Reinforced Plastics) plate, a PVF (polyvinyl fluoride) film, a mylar film, a polyester film, or an acrylic film can be used. In the case of this embodiment, a light-transmitting material is used because the radiation direction of light from the EL element is directed toward the cover material 4102.
[0250]
However, it is not necessary to use a light-transmitting material when the light emission direction from the EL element is opposite to the cover material, and a metal plate (typically a stainless steel plate), a ceramic plate, or an aluminum foil is used. A sheet having a structure sandwiched between PVF films or mylar films can be used.
[0251]
Further, as the filler 4103, an ultraviolet curable resin or a thermosetting resin can be used, and PVC (polyvinyl chloride), acrylic, polyimide, epoxy resin, silicone resin, PVB (polyvinyl butyral), or EVA (ethylene vinyl acetate) is used. Can be used. When a hygroscopic substance (preferably barium oxide) is provided inside the filler 4103, deterioration of the EL element can be suppressed. In this embodiment, a transparent material is used so that light from the EL element can pass through the filler 4103.
[0252]
Further, the filler 4103 may contain a spacer. At this time, if the spacer is formed of barium oxide, the spacer itself can be hygroscopic. In the case where a spacer is provided, it is also effective to provide a resin film on the anode 4305 as a buffer layer that relieves pressure from the spacer.
[0253]
The wiring 4005 is electrically connected to the FPC 4006 through a conductive material 4305. The wiring 4005 transmits a signal sent to the pixel portion 4002, the source side driver circuit 4003, and the gate side driver circuit 4004 to the FPC 4006 and is electrically connected to an external device by the FPC 4006.
[0254]
In this embodiment, the second sealing material 4104 is provided so as to cover the exposed portion of the first sealing material 4101 and a part of the FPC 4006, and the EL element is thoroughly shielded from the outside air. Thus, an EL display device having the cross-sectional structure of FIG. Note that the EL display device of this embodiment may be manufactured by combining any of the configurations of Embodiments 1 to 4 or 6 to 16.
[0255]
Example 19
In this embodiment, examples of a pixel structure that can be used for the pixel portion of the EL display device shown in Embodiment 18 are shown in FIGS. In this embodiment, 4401 is a source wiring of the switching TFT 4402, 4403 is a gate wiring of the switching TFT 4402, 4404 is a current control TFT, 4405 is a capacitor, 4406 and 4408 are current supply lines, and 4407 is an EL element. .
[0256]
FIG. 21A shows an example in which the current supply line 4406 is shared between two pixels. That is, there is a feature in that two pixels are formed so as to be symmetrical with respect to the current supply line 4406. In this case, since the number of power supply lines can be reduced, the pixel portion can be further refined.
[0257]
FIG. 21B illustrates an example in which the current supply line 4408 is provided in parallel with the gate wiring 4403. Note that in FIG. 21B, the current supply line 4408 and the gate wiring 4403 are provided so as not to overlap with each other. However, if the wirings are formed in different layers, they overlap with each other through an insulating film. It can also be provided. In this case, since the exclusive area can be shared by the power supply line 4408 and the gate wiring 4403, the pixel portion can be further refined.
[0258]
In FIG. 21C, a current supply line 4408 is provided in parallel with the gate wiring 4403 as in the structure of FIG. 21B, and two pixels are symmetrical with respect to the current supply line 4408. It is characterized in that it is formed. It is also effective to provide the current supply line 4408 so as to overlap any one of the gate wirings 4403. In this case, since the number of power supply lines can be reduced, the pixel portion can be further refined.
[0259]
Example 20
In addition to the nematic liquid crystal, various liquid crystals can be used for the electro-optical device of the present invention, specifically, the liquid crystal display device of the present invention. For example, 1998, SID, "Characteristics and Driving Scheme of Polymer-Stabilized Monostable FLCD Exhibiting Fast Response Time and High Contrast Ratio with Gray-Scale Capability" by H. Furue et al. Or 1997, SID DIGEST, 841, "A Full-Color Thresholdless Antiferroelectric LCD Exhibiting Wide Viewing Angle with Fast Response Time" by T. Yoshida et al. Or 1996, J. Mater. Chem. 6 (4), 671-673, "Thresholdless antiferroelectricity in liquid crystals and its application to displays" by S. Inui et al. And U.S. Patent No. 5594569 Can be used.
[0260]
In addition, a ferroelectric liquid crystal (FLC) showing an isotropic phase-cholesteric phase-chiral smectic phase transition series is used, and a cholesteric phase-chiral smectic phase transition is applied while applying a DC voltage, and the cone edge is substantially in the rubbing direction. The electro-optical characteristics of the matched monostable FLC are shown in FIG.
[0261]
The display mode using the ferroelectric liquid crystal as shown in FIG. 22 is called “Half-V-shaped switching mode”. The vertical axis of the graph shown in FIG. 22 is the transmittance (arbitrary unit), and the horizontal axis is the applied voltage. Regarding “Half-V-shaped switching mode”, Terada et al., “Half-V-shaped switching mode FLCD”, Proceedings of the 46th Joint Physics Related Conference, March 1999, p. 1316, and Yoshihara et al. "Time-division full-color LCD using ferroelectric liquid crystal", Liquid Crystal, Vol. 3, No. 3, page 190.
[0262]
As shown in FIG. 22, it can be seen that when such a ferroelectric mixed liquid crystal is used, low voltage driving and gradation display are possible. For the liquid crystal display device of the present invention, ferroelectric liquid crystal exhibiting such electro-optical characteristics can also be used.
[0263]
A liquid crystal exhibiting an antiferroelectric phase in a certain temperature range is called an antiferroelectric liquid crystal (AFLC). Among mixed liquid crystals having antiferroelectric liquid crystals, there is a so-called thresholdless antiferroelectric mixed liquid crystal that exhibits electro-optic response characteristics in which transmittance continuously changes with respect to an electric field. This thresholdless antiferroelectric mixed liquid crystal has a so-called V-shaped electro-optic response characteristic, and a drive voltage of about ± 2.5 V (cell thickness of about 1 μm to 2 μm) is also found. Has been.
[0264]
In general, the thresholdless antiferroelectric mixed liquid crystal has a large spontaneous polarization, and the dielectric constant of the liquid crystal itself is high. For this reason, when a thresholdless antiferroelectric mixed liquid crystal is used in a liquid crystal display device, a relatively large storage capacitor is required for the pixel. Therefore, it is preferable to use a thresholdless antiferroelectric mixed liquid crystal having a small spontaneous polarization.
[0265]
In addition, since such a thresholdless antiferroelectric mixed liquid crystal is used for the liquid crystal display device of the present invention, low voltage driving is realized, so that low power consumption is realized.
[0266]
Note that the liquid crystal shown in this embodiment can be used in a liquid crystal display device having any of the configurations of Embodiments 1 to 16.
[0267]
Example 21
The electro-optical device and the semiconductor circuit of the present invention can be used as a display unit or a signal processing circuit of an electric appliance. Such electric appliances include video cameras, digital cameras, projectors, projection TVs, goggles type displays (head mounted displays), navigation systems, sound reproduction devices, notebook personal computers, game machines, portable information terminals (mobile computers, Mobile phones, portable game machines, electronic books, etc.), image playback devices equipped with recording media, and the like. Specific examples of these electric appliances are shown in FIGS.
[0268]
FIG. 23A illustrates a mobile phone, which includes a main body 2001, an audio output portion 2002, an audio input portion 2003, a display portion 2004, operation switches 2005, and an antenna 2006. The electro-optical device of the present invention can be used for the display portion 2004, and the semiconductor circuit of the present invention can be used for the sound output portion 2002, the sound input portion 2003, or a CPU or memory.
[0269]
FIG. 23B shows a video camera, which includes a main body 2101, a display portion 2102, an audio input portion 2103, operation switches 2104, a battery 2105, and an image receiving portion 2106. The electro-optical device of the present invention can be used for the display portion 2102, and the semiconductor circuit of the present invention can be used for the audio input portion 2103, CPU, memory, or the like.
[0270]
FIG. 23C illustrates a mobile computer, which includes a main body 2201, a camera unit 2202, an image receiving unit 2203, operation switches 2204, and a display unit 2205. The electro-optical device of the present invention can be used for the display portion 2205, and the semiconductor circuit of the present invention can be used for a CPU, a memory, or the like.
[0271]
FIG. 23D illustrates a goggle type display which includes a main body 2301, a display portion 2302, and an arm portion 2303. The electro-optical device of the present invention can be used for the display portion 2302, and the semiconductor circuit of the present invention can be used for a CPU, a memory, or the like.
[0272]
FIG. 23E shows a rear projector (projection TV), which includes a main body 2401, a light source 2402, a liquid crystal display device 2403, a polarization beam splitter 2404, reflectors 2405 and 2406, and a screen 2407. The present invention can be used for the liquid crystal display device 2403, and the semiconductor circuit of the present invention can be used for a CPU, a memory, and the like.
[0273]
FIG. 23F illustrates a front projector which includes a main body 2501, a light source 2502, a liquid crystal display device 2503, an optical system 2504, and a screen 2505. The present invention can be used for the liquid crystal display device 2502, and the semiconductor circuit of the present invention can be used for a CPU, a memory, and the like.
[0274]
FIG. 24A illustrates a personal computer, which includes a main body 2601, a video input portion 2602, a display portion 2603, a keyboard 2604, and the like. The electro-optical device of the present invention can be used for the display portion 2603, and the semiconductor circuit of the present invention can be used for a CPU, a memory, or the like.
[0275]
FIG. 24B illustrates an electronic game machine (game machine), which includes a main body 2701, a recording medium 2702, a display portion 2703, and a controller 2704. Audio and video output from the electronic gaming machine are reproduced on a display including a housing 2705 and a display unit 2706. As a communication means between the controller 2704 and the main body 2701 or a communication means between the electronic gaming machine and the display, wired communication, wireless communication or optical communication can be used. In this embodiment, infrared rays are detected by the sensor units 2707 and 2708. The electro-optical device of the present invention can be used for the display portions 2703 and 2706, and the semiconductor circuit of the present invention can be used for a CPU, a memory, and the like.
[0276]
FIG. 24C shows a player (image playback device) that uses a recording medium (hereinafter referred to as a recording medium) on which a program is recorded. A main body 2801, a display portion 2802, a speaker portion 2803, a recording medium 2804, and an operation switch 2805 are provided. Including. This image reproducing apparatus uses a DVD (Digital Versatile Disc), a CD, or the like as a recording medium, and can perform music appreciation, movie appreciation, games, and the Internet. The electro-optical device of the present invention can be used for the display portion 2802, a CPU, a memory, and the like.
[0277]
FIG. 24D illustrates a digital camera, which includes a main body 2901, a display portion 2902, an eyepiece portion 2903, operation switches 2904, and an image receiving portion (not shown). The electro-optical device of the present invention can be used for the display portion 2902, a CPU, a memory, and the like.
[0278]
FIG. 25 shows a detailed description of an optical engine that can be used for the rear projector of FIG. 23E and the front projector of FIG. FIG. 25A shows an optical engine, and FIG. 25B shows a light source optical system built in the optical engine.
[0279]
The optical engine shown in FIG. 25A includes a light source optical system 3001, mirrors 3002, 3005 to 3007, dichroic mirrors 3003 and 3004, and an optical lens 3008. a ~ 3008 c , Prism 3011, liquid crystal display device 3010, and projection optical system 3012. The projection optical system 3012 is an optical system that includes a projection lens. In this embodiment, an example of a three-plate type using three liquid crystal display devices 3010 is shown, but a single-plate type may be used. In addition, an optical lens, a film having a polarization function, a film for adjusting a phase difference, an IR film, or the like may be provided in the optical path indicated by an arrow in FIG.
[0280]
As shown in FIG. 25B, the light source optical system 3001 includes light sources 3013 and 3014, a combining prism 3015, collimator lenses 3016 and 3020, lens arrays 3017 and 3018, and a polarization conversion element 3019. Note that the light source optical system illustrated in FIG. 25B uses two light sources, but may be one, or may be three or more. Further, an optical lens, a film having a polarization function, a film for adjusting a phase difference, an IR film, or the like may be provided somewhere in the optical path of the light source optical system.
[0281]
As described above, the application range of the present invention is extremely wide and can be applied to electric appliances in various fields. Moreover, the electric appliance of a present Example is realizable even if it uses the structure which consists of what combination of Examples 1-20.
[0282]
【The invention's effect】
By using the present invention, TFTs having gate insulating films with different thicknesses can be formed over the same substrate. Therefore, in a semiconductor device including an electro-optical device typified by an AM-LCD or an electric appliance having such an electro-optical device as a display unit, a circuit having an appropriate performance is arranged according to the specifications required by the circuit. Therefore, the performance and reliability of the semiconductor device can be greatly improved.
[0283]
In addition, in the pixel portion of the electro-optical device, the dielectric of the storage capacitor can be thinned, and a storage capacitor having a large capacity with a small area can be formed. Further, the storage capacitor can be hidden under the gate wiring or the source wiring. Therefore, even in an electro-optical device having a diagonal of 1 inch or less, a sufficient storage capacity can be secured without reducing the aperture ratio.
[Brief description of the drawings]
FIG. 1 shows a cross-sectional structure of an AM-LCD.
FIGS. 2A and 2B are diagrams illustrating a manufacturing process of an AM-LCD. FIGS.
3A and 3B are diagrams illustrating a manufacturing process of an AM-LCD.
4A and 4B are diagrams illustrating a manufacturing process of an AM-LCD.
FIGS. 5A and 5B are diagrams illustrating a manufacturing process of an AM-LCD. FIGS.
FIG. 6 is a block diagram and a circuit arrangement of an AM-LCD.
FIG. 7 shows a structure of a driving TFT (CMOS circuit).
FIG. 8 shows a cross-sectional structure of an AM-LCD.
FIG. 9 is a graph showing the relationship of concentration distribution when an impurity element is added.
FIG. 10 is a diagram showing an external appearance of an AM-LCD.
FIG. 11 shows a cross-sectional structure of an AM-LCD.
FIG. 12 shows a cross-sectional structure of an AM-LCD.
FIG. 13 shows a cross-sectional structure of an AM-LCD.
FIG 14 illustrates a cross-sectional structure of a driver circuit and a pixel portion.
FIG. 15 is a diagram showing a top structure of a pixel portion.
FIG. 16 is a diagram showing a top structure of a pixel portion.
FIG. 17 illustrates a top structure of a pixel portion.
18A and 18B are diagrams illustrating a manufacturing process of an AM-LCD.
FIG 19 illustrates a circuit configuration of an EL display device.
20A and 20B are a top view and a cross-sectional view of an EL display device.
FIG. 21 illustrates a structure of a pixel portion of an EL display device.
FIG. 22 is a graph showing optical response characteristics of liquid crystal.
FIG. 23 shows an example of an electric appliance.
FIG 24 shows an example of an electric appliance.
FIG. 25 is a diagram showing a configuration of an optical engine.

Claims (8)

A semiconductor device having a pixel portion and a drive circuit portion on the same quartz substrate,
The pixel portion is
A first light-shielding film on the quartz substrate and a first electrode of a first storage capacitor;
A first active layer made of a crystalline silicon film on the first light shielding film, and a second electrode of the first storage capacitor and the second storage capacitor;
A first gate insulating film on the first active layer;
A first TFT having a first gate electrode on the first gate insulating film and a third electrode of the second storage capacitor; and having the first storage capacitor and the second storage capacitor. And
The drive circuit unit is
A second light-shielding film on the quartz substrate;
A second active layer comprising a crystalline silicon film on the second light shielding film;
A second gate insulating film on the second active layer;
A second TFT having a second gate electrode on the second gate insulating film,
A dielectric having a thickness of 20 to 50 nm including a silicon nitride film is provided between the first electrode and the second electrode,
A first interlayer insulating film having a flat surface is provided to cover the first TFT, the second TFT, the first storage capacitor, and the second storage capacitor,
A third light shielding film is provided on the first interlayer insulating film so as to overlap the first TFT, the first storage capacitor, and the second storage capacitor,
A second interlayer insulating film having a flat surface is provided to cover the third light shielding film;
A semiconductor device, wherein a pixel electrode made of a transparent conductive film electrically connected to the first active layer is provided on the second interlayer insulating film. A semiconductor device having a pixel portion and a drive circuit portion on the same quartz substrate,
The pixel portion is
A first light shielding film on the quartz substrate and a first electrode of a storage capacitor;
A first active layer made of a crystalline silicon film on the first light shielding film and a second electrode of the storage capacitor;
A first gate insulating film on the first active layer;
A first TFT having a first gate electrode on the first gate insulating film, and the storage capacitor,
The drive circuit unit is
A second light-shielding film on the quartz substrate;
A second active layer comprising a crystalline silicon film on the second light shielding film;
A second gate insulating film on the second active layer;
A second TFT having a second gate electrode on the second gate insulating film,
A dielectric having a thickness of 20 to 50 nm including a silicon nitride film is provided between the first electrode and the second electrode,
A first interlayer insulating film having a flat surface is provided to cover the first TFT, the second TFT, and the storage capacitor;
A third light-shielding film is provided on the first interlayer insulating film so as to overlap the first TFT and the storage capacitor,
A second interlayer insulating film having a flat surface is provided to cover the third light shielding film;
A semiconductor device, wherein a pixel electrode made of a transparent conductive film electrically connected to the first active layer is provided on the second interlayer insulating film. 3. The semiconductor device according to claim 1, wherein the second gate insulating film is thinner than the first gate insulating film. 4. The first light-shielding film, the second light-shielding film, and the first electrode are formed of a phosphorus-doped silicon film, a boron-doped silicon film, a tungsten film, a tantalum film, and molybdenum, according to claim 1. A semiconductor device comprising a film, a titanium film, a silicide film, a tantalum nitride film, a tungsten nitride film, or a titanium nitride film. 5. The semiconductor device according to claim 1, wherein the first active layer and the second active layer have an LDD region. 6. The semiconductor device according to claim 1, wherein the first interlayer insulating film includes a polyimide film, an acrylic film, a polyamide film, or a BCB film. 7. The semiconductor device according to claim 1, wherein the second interlayer insulating film includes a polyimide film, an acrylic film, a polyamide film, or a BCB film.   An electric appliance using the semiconductor device according to claim 1 as a display portion.

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