JP7467976B2 - Thin film transistor, its manufacturing method, and semiconductor device including the same - Google Patents

Description

The present invention relates to a thin-film transistor, a method for manufacturing the same, and a semiconductor device including the same.

In recent years, wireless communication systems that use RFID (Radio Frequency Identification) technology as contactless tags have been developed. In RFID systems, wireless communication is carried out between a wireless transceiver called a reader/writer and an RFID tag.

RFID tags are expected to be used for a variety of purposes, including logistics management, product management, and shoplifting prevention, and are already being introduced in some IC cards such as transportation cards and product tags. RFID tags have an IC chip and an antenna for wireless communication with a reader/writer. The antenna installed inside the tag receives the carrier wave transmitted from the reader/writer, which activates the drive circuit inside the IC chip.

It is expected that RFID tags will be used in a wide variety of products and situations. To achieve this, it is essential to reduce manufacturing costs, and studies are underway to move away from manufacturing processes that use vacuums and high temperatures and to develop cheaper ones that use coating and printing techniques.

For example, the use of thin-film transistors (hereinafter referred to as TFTs) that use organic semiconductors with excellent formability as the semiconductor layer has been proposed for the driving circuits in IC chips. By using organic semiconductors as ink, it becomes possible to form circuit patterns directly on flexible substrates using inkjet technology or the like (see, for example, Patent Document 1). The use of this technology makes it possible to apply the so-called roll-to-roll process, and it is expected that it will become possible to manufacture IC chips at reduced manufacturing costs.

JP 2011-187750 A

However, the size of TFTs made using coating and printing techniques, and the circuit patterns that use them, depend on the processing accuracy of the coating and printing techniques. Furthermore, such TFTs have the problem that they are larger in area than transistors made from so-called silicon semiconductors.

For example, in the technology described in Patent Document 1, the drain electrode and source electrode, which are components of a TFT, are processed and formed by photolithography, and an organic semiconductor ink is supplied between them by an inkjet method to form an organic semiconductor layer. Here, the size of the organic semiconductor layer formed by the inkjet method is larger than the minimum processing dimensions of each electrode processed and formed by photolithography. Therefore, the area per TFT depends on the area of the organic semiconductor layer, resulting in a large chip area.

In addition, in general, TFTs often use a channel length that is short relative to the channel width due to the required electrical characteristics. For example, the TFT described in Patent Document 1 uses a channel length of 5 μm and a channel width of 50 μm to 100 μm. In this case, the difference between the channel width and the channel length is 10 times or more, and the wasted area is large for the organic semiconductor layer, which is relatively close to a circle.

In addition, organic semiconductors, particularly those that use coating techniques, have the problem that the variability between individual semiconductor elements is greater than that of inorganic crystalline semiconductor elements, due to the crystallinity of the semiconductor layer and the state of network formation in the nanowires. This makes it difficult to stabilize the characteristics of current mirror circuits and differential pairs that take advantage of the small relative variability in a pair of semiconductor elements, making it difficult to design analog circuits.

The present invention aims to provide a TFT that has a small area, reduces manufacturing costs, and has small relative variation between adjacent channels, and a semiconductor device using the same.

The present invention has been made in view of the above problems,
1. A thin film transistor having at least two channel regions,
A substrate;
At least three electrodes serving as drains or sources;
at least two gate electrodes;
a gate insulating layer in contact with each of the at least two gate electrodes;
an island-shaped semiconductor layer spanning the at least two channel regions;
The thin film transistor is characterized by having

The present invention provides a TFT that is small in area, reduces manufacturing costs, and has small relative variations between adjacent channels, and a semiconductor device that uses the TFT.

FIG. 1 is a schematic plan view showing a TFT according to a first embodiment of the present invention; FIG. 2 is a schematic cross-sectional view showing a cross section taken along line AB of the plan view shown in FIG. 1. FIG. 11 is a schematic plan view showing a TFT according to a second embodiment of the present invention; FIG. 11 is a schematic plan view showing a TFT according to a third embodiment of the present invention. FIG. 11 is a schematic plan view showing a TFT according to a fourth embodiment of the present invention; FIG. 13 is a schematic plan view showing a TFT according to a fifth embodiment of the present invention. 1 is a schematic cross-sectional view showing an example of a method for manufacturing a TFT according to an embodiment of the present invention; 1 is a schematic cross-sectional view showing an example of a method for manufacturing a TFT according to an embodiment of the present invention; FIG. 13 is a schematic plan view showing a semiconductor device according to a sixth embodiment of the present invention. FIG. 13 is a schematic plan view showing a conventional semiconductor device according to a sixth embodiment of the present invention; FIG. 13 is a schematic plan view showing a semiconductor device according to a seventh embodiment of the present invention. FIG. 13 is a schematic plan view showing a semiconductor device according to an eighth embodiment of the present invention. FIG. 13 is a schematic plan view showing a semiconductor device according to a ninth embodiment of the present invention.

Below, a mode for carrying out the present invention (hereinafter referred to as "embodiment") will be described with reference to the attached drawings. Note that the drawings are schematic. Furthermore, the present invention is not limited to the embodiment described below.

In the following, a multi-gate TFT refers to a thin-film transistor (TFT) that has multiple gate electrodes and multiple channel regions for one semiconductor layer.

<Thin film transistor>
(Embodiment 1)
FIG. 1 is a schematic plan view showing a TFT according to a first embodiment of the present invention, and FIG. 2 is a schematic cross-sectional view showing a cross section taken along line AB of the schematic plan view shown in FIG.

In Figures 1 and 2, a TFT is formed on a film substrate 10 made of PET (polyethylene terephthalate) or the like, the TFT having two gate electrodes 200 and 201, a gate insulating layer 50 in contact with both of them, three electrodes 110, 111, and 112 that serve as source or drain, two channel regions 300 and 301, and an island-shaped semiconductor layer 400 that spans the channel regions.

With the above configuration, a TFT (called TFT-R) formed of the gate electrode 200, the electrodes 110 and 111 serving as the source or drain, and the portion of the semiconductor layer 400 that overlaps with the channel region 300, and a TFT (called TFT-L) formed of the gate electrode 201, the electrodes 111 and 112 serving as the source or drain, and the portion of the semiconductor layer 400 that overlaps with the channel region 301 are connected in series via the electrode 111. In this state, two TFTs are formed in an area covered by the semiconductor layer 400 that forms an island. In other words, the TFT according to the first embodiment can be said to be an assembly of two TFTs.

According to the first embodiment, the area required to form the TFTs is roughly half that required when two TFTs each have their own island-shaped semiconductor layer. As a result, it is possible to reduce the chip area and manufacturing costs.

Here, as shown in FIG. 1, from the viewpoint of area efficiency, it is preferable that the semiconductor layer 400 encompasses both ends in the width direction of each channel region (the boundary between the channel region 300 and the electrode 110, the boundary between the channel region 300 and the electrode 111, the boundary between the channel region 301 and the electrode 111, and the boundary between the channel region 301 and the electrode 112). In addition, if there is a region of the semiconductor layer between the source electrode and the drain electrode whose conductive state is not controlled by the gate electrode, there is a concern that the leakage current may increase. Therefore, in order to suppress the leakage current, it is preferable that the planar shape of the gate electrodes 200 and 201 protrudes in at least two directions from the island-shaped semiconductor layer 400.

In the first embodiment, a so-called bottom gate structure is shown in which the gate electrode is on the substrate side of the channel region, but as long as the desired characteristics and effects are obtained, a so-called top gate structure in which the gate electrode is on the opposite side of the substrate to the channel region may be used. Similarly, in the first embodiment, a so-called bottom contact type configuration is shown in which the semiconductor layer is in contact with the source electrode and drain electrode on the opposite side of the substrate, but as long as the desired characteristics and effects are obtained, a so-called top contact type configuration in which the semiconductor layer is on the substrate side of the source electrode and drain electrode may be used.

TFT-R and TFT-L do not necessarily need to be connected in series; the electrode 111 placed between the two TFTs may be connected to another wiring, and the two TFTs may be connected in parallel.

In the first embodiment, the number of gate electrodes is two, and the number of drain or source electrodes is three, but the number of these electrodes may be increased. For example, the number of gate electrodes may be three (or more), and the number of drain or source electrodes may be four (or more), resulting in a configuration including three (or more) TFTs.

Although there are no particular limitations on the electrical connection of each gate electrode, it is desirable that they are electrically independent from the viewpoint of controllability of the TFT and applicability to circuits. Having two or more electrodes electrically independent is particularly desirable from the viewpoint of being able to individually control multiple TFT channels with little variation. In addition, in a TFT that includes three or more gate electrodes, some of the gate electrodes can be electrically connected to connect the channels in parallel, and the remaining electrodes can be electrically independent, thereby obtaining a pair of TFTs with a size ratio based on the sum of the channel widths formed by the electrically independent gate electrodes. Since the electrical characteristics of this TFT pair are proportional to the size ratio, the electrical characteristics are easy to control, and a circuit with good characteristics can be formed, particularly in a circuit configuration that uses a current ratio, such as a current mirror circuit.

The planar shape of the island-shaped semiconductor layer 400 is preferably circular. As described below, from the viewpoint of reducing the manufacturing cost of the TFT, it is desirable to form the island-shaped semiconductor layer using a so-called coating/printing method. Furthermore, in order to minimize the amount of material used to form the semiconductor layer, it is preferable to coat/print the semiconductor layer only on the portions where elements such as TFTs are to be formed. From this viewpoint, the inkjet method is particularly preferably used. And the fact that the planar shape of the semiconductor layer is circular is a configuration that is particularly suitable for formation by the inkjet method.

Note that the circle referred to here is not limited to a perfect circle. In other words, the planar shape of the semiconductor layer does not have to be a perfect circle as long as it is close to the planar projection shape of the semiconductor ink droplets. Because the semiconductor layer is formed by the free fall of the semiconductor ink droplets, the planar projection shape of the droplets is not always a perfect circle. Therefore, as long as the process is reproducible and the variation in shape and characteristics is within the desired range, there is no problem if the shape is a deviation from a perfect circle.

In the first embodiment, the materials used for the gate electrode, source electrode, and drain electrode may be any conductive material that can be generally used as an electrode. Examples include indium tin oxide (ITO), gold, silver, copper, aluminum, polysilicon, conductive polymers, and carbon materials. These electrode materials may be used alone, or multiple materials may be stacked or mixed.

In the first embodiment, a film made of PET is exemplified as the substrate, but the substrate may be made of any material as long as at least the surface on which the electrode system is disposed is insulated. Examples include silicon wafer, glass, polyimide, etc. The substrate may also be a laminate of multiple materials. In consideration of application to inexpensive manufacturing processes such as roll-to-roll, it is preferable for the substrate to be a highly flexible material such as a film, and further, it is preferable for the substrate to be as thin as possible as long as the desired functionality and characteristics such as insulation and protection can be ensured.

In the first embodiment, the material contained in the gate insulating layer is not particularly limited as long as the desired insulating properties are obtained. Examples include silicon oxide, alumina, polyimide, and the like. Considering application to inexpensive manufacturing processes such as roll-to-roll, a material that can be applied to coating methods, printing methods, and the like is preferable.

In the present embodiment 1, the material contained in the semiconductor layer 400 is not particularly limited as long as it provides the desired electrical characteristics, is applicable to an inexpensive manufacturing process, and has excellent processability. In particular, it is more preferable that the material contained in the semiconductor layer is one or more selected from organic semiconductors, graphene, and carbon nanotubes (CNTs), in that high electrical characteristics are realized and formation by coating is easy. In particular, CNTs are preferable, and from the viewpoint of processability such as the dispersibility of the CNTs themselves, CNTs having a conjugated polymer attached to at least a part of the surface are even more preferable.

In addition, by configuring multiple CNTs into a network, it is possible to achieve both electrical properties and ease of manufacturing, which is more preferable than manufacturing and arranging individual CNTs or orienting multiple CNTs. The state in which multiple CNTs are configured into a network can be observed using an atomic force microscope (AFM) or a transmission electron microscope (TEM).

Furthermore, in order to suppress the variation in the characteristics of the TFTs and to suppress the leakage current paths across multiple channels, it is more preferable that the CNTs contain 80% by weight or more of semiconducting CNTs. Even more preferable is that the CNTs contain 90% by weight or more of semiconducting CNTs, and particularly preferable is that the CNTs contain 95% by weight or more of semiconducting CNTs.

The TFT according to the first embodiment described above has an island-shaped semiconductor layer 400 that spans two channel regions, so the semiconductor layer is shared between TFT-R and TFT-L. Therefore, compared to when TFT-R and TFT-L each have an independent semiconductor layer, the characteristic variation between TFTs caused by the semiconductor layer is reduced. In addition, because the physical distance between TFT-R and TFT-L is short, the variation in TFT characteristics caused by factors other than the semiconductor layer is reduced. As a result, it is possible to form TFTs with less mutual variation in electrical characteristics.

By applying the TFT according to the first embodiment to a semiconductor circuit known as an analog circuit, it is possible to improve the operational stability of the circuit and the yield. More specifically, for example, the TFTs of the reference current generating section and the current mirror section of a current mirror circuit can be located in the same island-shaped semiconductor layer, or the TFTs used in the differential input section of a differential amplifier circuit can be located in the same island-shaped semiconductor layer.

(Embodiment 2)
3 is a schematic plan view showing a TFT according to a second embodiment of the present invention. The TFT according to the second embodiment has the same configuration as that of the first embodiment, except that the width of the gate electrode 201 is smaller than that of the first embodiment, and the width of the electrode 112, which is one of the electrodes serving as the source or drain, in the direction in which the gate electrode runs is smaller. Due to this configuration, the channel length and channel width of the TFT-L in the second embodiment are different from those in the first embodiment. Thus, the shape, channel length, channel width, etc. of each element constituting the two TFTs may be different as long as the effects of the present invention can be obtained.

(Embodiment 3)
4 is a schematic plan view showing a TFT according to a third embodiment of the present invention. The TFT according to the third embodiment has the same structure as that shown in FIG. 1, except that the width of the electrode 110 serving as the source or drain in the direction in which the gate electrode runs is smaller.

The channel width of TFT-R is the smaller of the length of the contact surface between gate electrode 200 and electrode 110 and the length of the contact surface between gate electrode 200 and electrode 111. In the case of the third embodiment, it is the length of the side where electrode 110 and gate electrode 200 are in contact.

It is desirable that the size of the semiconductor layer 400 on a plane corresponds to the maximum value of the channel width (maximum channel width Wm). In the third embodiment, the size of the semiconductor layer 400 on a plane is an appropriate size that can completely cover the maximum channel width Wm, but is not too large.

It is preferable that the maximum distance between the two gate electrodes (maximum distance dm) is smaller than the maximum channel width Wm. This makes it possible to include the desired TFTs in the same island-shaped semiconductor layer 400, and thus reduces the chip area and manufacturing costs by reducing the TFT area.

(Embodiment 4)
FIG. 5 is a schematic plan view showing a TFT according to the fourth embodiment of the present invention. The fourth embodiment has the same configuration as the third embodiment except that the gate electrode 201 has a bend. In the fourth embodiment, the maximum channel width Wm of the TFT (TFT-L) on the side including the gate electrode 201 having a bend is the shorter side of the lengths of the left and right ends of the channel region 301 (the shorter side of the sum of the lengths of the sides of the electrode 111 or the electrode 112 that are in contact with the channel region 301) as shown in FIG. 5. In the example shown in FIG. 5, the gate electrode 201 has a right-angle bend, but this is not limited to a right angle, and the angle of the bend is not limited as long as the desired electrical characteristics and shape are obtained, and the number of bends is not particularly limited. In addition, the bend is not limited to a straight angle, and may be an arc or a cycloid curve.

(Embodiment 5)
6 is a schematic plan view showing a TFT according to a fifth embodiment of the present invention. The fifth embodiment has the same configuration as the first embodiment, except that the shapes of the gate electrodes 200 and 201, the electrodes 110, 111, and 112 serving as the source and drain, and the island-like semiconductor layer 400 are different.

In this fifth embodiment, both the gate electrodes 200 and 201 have a bend, and the semiconductor layer 400 has an elliptical shape. Comparing the TFT-R and TFT-L, the channel width of the TFT-L is longer. Therefore, the maximum channel width Wm is as shown in FIG. 6. On the other hand, the distance between the channels of the two TFTs is maximum at the point indicated by dm in FIG. 6. Therefore, the TFT according to this fifth embodiment has a relationship of Wm>dm, and it is possible to provide a semiconductor device with good area efficiency, a small chip area, and reduced manufacturing costs. In this fifth embodiment, the case where two gate electrodes and two TFTs are arranged is shown, but even if three or more gate electrodes are present, it is sufficient that each gate electrode independently has a desired shape, and the correlation between each gate electrode is not particularly limited.

As for the semiconductor layer 400, the drawing shows a case where the long axis of the ellipse is in the vertical direction, but the material and method of formation are not particularly limited as long as the semiconductor layer is formed in the desired area by an appropriate method depending on the shape of the gate electrode and source/drain electrodes, the coating/printing method of the semiconductor layer, etc. However, it is more preferable to cover the area that will become the channel of the TFT and form it in a shape similar to a circle, as this reduces manufacturing costs and allows for efficient use of the semiconductor layer.

(Embodiment 6)
Fig. 8(a) is a schematic plan view showing a layout of a semiconductor device according to a sixth embodiment of the present invention, and Fig. 8(b) is a circuit diagram showing this configuration.

In this sixth embodiment, a NAND gate is constructed using two multi-gate TFTs, each having two gate electrodes and three source or drain electrodes. The two TFTs are a p-type TFT 500 and an n-type TFT 510, respectively, and constitute a CMOS circuit. The two gate electrodes in the p-type TFT 500 have potentials independent of each other. Similarly, the two gate electrodes in the n-type TFT 510 have potentials independent of each other.

The method for fabricating the p-type TFT 500 and the n-type TFT 510 on the same substrate is not particularly limited, but examples include a method of directly adding impurities to the semiconductor material, a method of injecting and diffusing impurities using ion implantation or doping paste, and a method of introducing a carrier material by covering the channel region with an overcoat material. In particular, introducing the carrier using an overcoat material is more preferable because it is easier to apply low-temperature processes and does not require a vacuum process, making it easier to apply to roll-to-roll.

The sixth embodiment is similar to the first embodiment, except that the semiconductor device is constructed by connecting two TFTs to wiring, and that a p-type TFT and an n-type TFT are formed on the same substrate. The TFT configuration may be any of the configurations shown in the second to fifth embodiments. In addition, the shapes of the electrodes that become the gate electrode, source, or drain are not limited as long as the desired electrical characteristics can be ensured.

In the p-type TFT 500, one gate is connected to wiring 530, which is input 1, and the other gate is connected to wiring 531, which is input 2. The wiring for input 1 and input 2 are each controlled by independent potentials. Of the three drain or source electrodes, one drain electrode sandwiched between two gate electrodes is a common terminal for the two channels and is connected to wiring 536, which is the output. The other two source electrodes are both connected to wiring 540, which is a power source.

In the n-type TFT 510, one gate is connected to wiring 530, which is input 1, and the other gate is connected to wiring 531, which is input 2. The wiring for input 1 and input 2 are each controlled by independent potentials. Of the three drain or source electrodes, one drain electrode is connected to wiring 536, which is the output. The one source or drain electrode sandwiched between the two gate electrodes is a common terminal for the two channels, and serves as the source of the output channel and the drain of the GND channel. The remaining source electrode is connected to wiring 545, which is GND.

By configuring as above, a two-input, one-output NAND gate circuit is formed, which has two p-type TFT channels connected in parallel and two n-type TFT channels connected in series.

Figure 9(a) is a schematic plan view showing a layout in which a circuit electrically equivalent to that shown in Figure 8(a) is formed using a single-gate TFT having only one gate electrode and two source or drain electrodes, for comparison with the conventional method. The circuit diagram is shown in Figure 9(b), which is the same as Figure 8(b) when a multi-gate TFT is used. In the conventional form shown in Figure 9(a), two p-type semiconductor layers and two n-type semiconductor layers are arranged, and the source electrodes of p-type TFTs 501 and 502 are both connected to the power supply electrode 541, the drain electrodes of p-type TFTs 501 and 502 are both connected to the output electrode 537, the source electrode of n-type TFT 511 is connected to the GND electrode 546, and the drain electrode of n-type TFT 512 is connected to the output electrode 537. The drain electrode of n-type TFT 511 and the source electrode of n-type TFT 512 are connected to the wiring 538 as a common terminal. Therefore, the source and drain electrodes of the p-type TFTs 501 and 502 are configured in parallel, and the source and drain electrodes of the n-type TFTs 511 and 512 are configured in series.

Here, FIG. 8(a) and FIG. 9(a) are logically equivalent circuit configurations, but the combined area of the TFT and surrounding wiring in this example is less than half that of FIG. 9(a) in FIG. 8(a), and the use of multi-gate TFTs allows for a significant reduction in circuit area. In addition, the area of the semiconductor layer itself is also halved, allowing for a significant reduction in material costs for the substrate and semiconductor layer. Furthermore, a circuit configuration using multi-gate TFTs is advantageous from the standpoint of increasing the number of semiconductor devices that can be obtained through integration and miniaturizing manufacturing equipment. Furthermore, since there is no need to route wiring for the common electrode in a series connection, this is also preferable from the standpoint of increasing the design freedom of the wiring layout.

In the sixth embodiment, an example of a NAND circuit is shown, but the circuit configuration is not particularly limited as long as at least one TFT in the semiconductor device includes two or more gate electrodes and three or more source or drain electrodes, and the potentials of at least two of the gate electrodes are independently controlled. Examples include a NOR circuit, an inverter circuit, a clocked inverter circuit, a flip-flop circuit, and composite gates thereof.

In this embodiment 6, the power supply wiring, GND wiring, input 1, input 2, and output terminals are given as examples of input/output electrodes, but as long as the desired electrical characteristics of the circuit are obtained, there are no limitations on where each input/output electrode is connected. For example, the power supply wiring and GND wiring can be replaced with GND wiring and negative power supply wiring, respectively.

(Seventh embodiment)
Fig. 10(a) is a schematic plan view showing a layout of a semiconductor device according to a seventh embodiment of the present invention. Fig. 10(b) is a circuit diagram of the semiconductor device and peripheral circuits of this embodiment, in which a current mirror circuit 590 corresponds to the semiconductor device according to the seventh embodiment, i.e., the semiconductor device in Fig. 10(a). A power supply line 600, a current source 601, and a load R _L 602 are peripheral circuit components that control the semiconductor device according to the seventh embodiment.

In this seventh embodiment, a single-output current mirror circuit is constructed using a p-type TFT having two gate electrodes and three source or drain electrodes.

The seventh embodiment is similar to the first embodiment, except that the semiconductor device is configured by connecting two TFTs to wiring. The configuration of the TFT is not limited to this, and may be any of the configurations shown in the second to fifth embodiments.

In the p-type TFT 503, a pair of adjacent gate electrodes are electrically connected by a common electrical wiring 580. The source electrode sandwiched between the two gate electrodes is a common electrode. The common electrode is an electrode that serves as the source or drain electrodes of two or more TFT channels by a single electrical wiring. The two outer drain electrodes of both channels are connected to different electrical wiring. One of the drain electrodes is connected to the gate electrode wiring through an interlayer via 550 to form a diode connection.

The above configuration results in a current mirror circuit using two p-type TFT channels. The common electrode of this current mirror circuit is connected to the power supply wiring 542, the drain electrode on the diode connection side is connected to the current source 601 via the input wiring 570, and the output wiring 571 is connected to the GND wiring via the load 602, so that the current of the current source 601 is mirrored to the load current. At this time, the on-current 560 of the TFT flows from the source electrode to the drain electrode in both of the two TFT channels, that is, from the common source electrode to the outer drain electrode.

When fabricating a circuit in which the relative variation between two channels needs to be small, such as the current mirror circuit or differential pair circuit shown in the seventh embodiment, it is preferable to use multiple channels on a multi-gate TFT from the viewpoint of suppressing variations due to the particle size, film thickness, and network structure of the semiconductor layer, and positional variations in processing accuracy, such as channel length and channel width.

In the seventh embodiment, an example of a current mirror circuit using two p-type TFT channels has been shown, but a similar current mirror circuit can also be configured using n-type TFTs. In this case, the direction of the on-current flowing through the TFT channel is opposite to that in the case of a p-type TFT, and flows from the drain electrode to the source electrode, i.e., from the outer drain electrode to the common source electrode.

(Embodiment 8)
Fig. 11(a) is a schematic plan view showing a layout of a semiconductor device according to an eighth embodiment of the present invention. Fig. 11(b) is a circuit diagram of the semiconductor device according to the eighth embodiment and peripheral circuits, in which a current mirror circuit 591 corresponds to the semiconductor device according to the eighth embodiment, i.e., the semiconductor device in Fig. 11(a). A power supply line 603, a current source 604, and loads R _L 605-606 are peripheral circuit components that control the semiconductor device according to the eighth embodiment.

In this eighth embodiment, a two-output current mirror circuit is configured using a p-type multi-gate TFT 504 having six gate electrodes and seven source or drain electrodes.

This embodiment 8 is the same as embodiment 7, except that the channel of the TFT that is the current mirror source and the channel of the TFT that is the current mirror destination are each connected in parallel for two channels, and the current mirror destination has two outputs.

In the p-type TFT 504, all six gate electrodes are electrically connected by wiring 581, and the drain or source electrodes sandwiched between two adjacent gate electrodes are each a common electrode. There are three common drain electrodes, which are connected to wiring 572 as input, wiring 573 as output 1, and wiring 574 as output 2, respectively. These drain electrodes are not directly connected to each other and are electrically independent. In addition, the drain electrode connected to wiring 572 as input is also connected to wiring 581 of the gate electrode through an interlayer via 551 to form a diode connection.

There are four source electrodes in total: two common electrodes and two separate electrodes on either side of the channel, all connected to the power supply wiring 543.

The above configuration results in a current mirror circuit using six p-type TFT channels. The input wiring 572 is connected to a current source, and output 1 and output 2 wirings 573 and 574 are connected to GND wiring via loads 605 and 606, respectively, so that the current of the current source 604 is mirrored to the load current. At this time, the TFT on-current 561 flows from the source electrode to the drain electrode in both of the two TFT channels, that is, from the common source electrode to the outer drain electrode.

In this embodiment 8, an example of a current mirror circuit using six p-type TFT channels has been shown, but a similar current mirror circuit can also be configured using n-type TFTs. In this case, the direction of the on-current flowing through the TFT channel is opposite to that in the case of a p-type TFT, and flows from the drain electrode to the source electrode, i.e., from the outer drain electrode to the common source electrode.

(Embodiment 9)
Fig. 12(a) is a schematic plan view showing a layout of a semiconductor device according to a ninth embodiment of the present invention. Fig. 12(b) is a circuit diagram of the semiconductor device and peripheral circuits according to the ninth embodiment, in which a cascode-type current mirror circuit 592 corresponds to the semiconductor device according to the ninth embodiment, i.e., the semiconductor device in Fig. 12(a). A power supply line 607, a current source 608, and a load R _L 609 are peripheral circuit components that control the semiconductor device of this embodiment. In this ninth embodiment, a cascode-type current mirror circuit with one output is configured using a p-type multi-gate TFT 505 having four gate electrodes and five source or drain electrodes.

The ninth embodiment is the same as the seventh embodiment, except that the channel of the TFT that is the current mirror source and the channel of the TFT that is the current mirror destination are each connected in series with two channels.

In the p-type TFT 505, of the four gate electrodes, the two on the outside are electrically connected by wiring 582, and the two on the inside are electrically connected by wiring 583.

The source electrode sandwiched between two adjacent gate electrodes connected to the inner wiring 583 is a common electrode, and is connected to the power supply wiring 544. The two electrodes sandwiched between the outer gate electrode and the inner gate electrode are each a common electrode, the drain electrode of the channel created by the inner gate electrode, and the source electrode of the channel created by the outer gate electrode. These two electrodes are electrically independent and have different potentials. Of these, the side that is the source of the current mirror is connected to the two inner gate electrodes through wiring via 553 and wiring 583 to form a diode connection.

The two outermost electrodes are drain electrodes of the channels created by the outer gate electrodes, with the electrode that is the source of the current mirror connected to input wiring 575 and the electrode that is the destination of the current mirror connected to output wiring 576. The electrode that is the source of the current mirror is connected to the two outer gate electrodes through wiring via 552 and wiring 582 to form a diode connection.

The above configuration results in a cascode-type current mirror circuit using four p-type TFT channels. The input wiring 575 is connected to a current source, and the output wiring 576 is connected to a GND wiring via a load, so that the current of the current source is mirrored to the load current. At this time, the TFT on-current 562 flows from the source electrode to the drain electrode in both of the two inner TFT channels, that is, from the common source electrode to the outer drain electrode.

In the present embodiment 9, an example of a current mirror circuit using four p-type TFT channels has been shown, but a similar current mirror circuit can also be configured using n-type TFTs. In this case, the direction of the on-current flowing through the TFT channel is opposite to that in the case of a p-type TFT, and flows from the drain electrode to the source electrode, i.e., from the outer drain electrode to the common source electrode.

<Method of Manufacturing Thin Film Transistor>
Next, a method for manufacturing a TFT according to the embodiment of the present invention will be described in detail with reference to FIG. 7, taking as an example a method for manufacturing the semiconductor device according to the first embodiment.

First, as shown in FIG. 7(a), a film of, for example, metal is formed on a substrate 10 made of a PET film to become the gate electrodes 200 and 201, and the film is processed into a desired shape using a so-called photolithography process including resist coating, exposure, development, and etching. Note that the materials and film formation methods of the gate electrodes 200 and 201, and the detailed conditions of each photolithography process are not particularly limited as long as the desired shape is obtained.

Next, as shown in FIG. 7B, an insulating film that will become the gate insulating layer 50 is formed. The gate insulating layer 50 can be formed of any material or by any method, but for example, forming the film by coating has the advantage of being inexpensive to manufacture. The gate insulating layer 50 can be processed, for example, by a photolithography process so that only the semiconductor element portion remains, or it can be left unprocessed and the gate insulating layer can remain on the entire surface. However, in one of the steps, a step for electrically connecting the gate electrode 200 and the gate electrode 201 is required, although this is omitted in this example of the manufacturing method.

Next, as shown in FIG. 7(c), the source electrode or drain electrode 110, 111, 112 is formed and processed into the desired shape, for example, by using the above-mentioned photolithography process. Here again, for example, using a coatable material as the electrode material has the advantage of enabling cheaper manufacturing, but the material, film formation method, and processing method are not particularly limited as long as the desired shape and characteristics can be obtained.

Next, as shown in FIG. 7(d), a semiconductor layer is formed. By forming the semiconductor layer by a coating method, it is possible to form the semiconductor layer only in the area where it is to be formed. Specific examples of coating methods include the inkjet method, nozzle coating method, screen printing method, offset printing method, and drop cast coating method. However, when forming the minimum necessary area of the semiconductor layer in a specific area, the inkjet method is preferred.

When forming a semiconductor layer using the inkjet method, the semiconductor layer is applied and printed by ejecting, from an inkjet head, a semiconductor ink containing a semiconductor material to which a solvent or the like has been added as necessary. In this case, the shape of the ejected semiconductor ink changes depending on various factors such as the surface energy at the landing point, the viscosity of the semiconductor ink, and the operating speed of the inkjet head. From the viewpoint of controllability of the manufacturing process, it is desirable for the shape of the semiconductor layer to be relatively uniform between TFTs, and it is preferable for the semiconductor layer formed by the landing of the semiconductor ink to be close to the planar projection shape of the semiconductor ink droplets.

In this example of the manufacturing method, the semiconductor is formed after the source and drain electrodes are formed, but the semiconductor layer may be formed before the source and drain electrodes are formed, and this order is not particularly limited.

The temperature of the manufacturing process is not particularly limited, but it is desirable to set it as low as possible from the viewpoint of ease of application of roll-to-roll and coating processes, so long as the desired electrical characteristics and shape of the thin-film transistors to be formed can be obtained. In particular, by setting the process temperature at 200°C or less, it becomes possible to apply inexpensive and highly flexible substrates such as PET and PP (polypropylene). Note that the manufacturing process temperature here refers to the maximum temperature in the region where the substrate and thin-film transistors are formed during manufacturing. In addition, it is preferable that the glass transition temperature of the substrate is 200°C or less. The glass transition temperature is analyzed by thermomechanical analysis (TMA).

As a result of the above, it is possible to manufacture TFTs with the configuration shown in embodiment 1 of the present invention and chips using those TFTs, and because the TFT area is small, the chip area is also small, making it possible to realize highly functional or high-performance circuits at low manufacturing costs.

One specific example of the present invention is shown below. Note that the present invention is not limited to the following example.

Example 1
(1) Preparation of Semiconductor Solution 1.5 mg of CNT1 (manufactured by CNI, single-walled CNT) with a purity of 95% and 1.5 mg of sodium dodecyl sulfate (manufactured by Wako Pure Chemical Industries, Ltd.) were added to 30 ml of water, and ultrasonic stirring was performed for 3 hours with an output of 250 W using an ultrasonic homogenizer while cooling on ice, to obtain a CNT composite dispersion with a CNT composite concentration of 0.05 g/l relative to the solvent. The obtained CNT composite dispersion was centrifuged at 21000 G for 30 minutes using a centrifuge (manufactured by Hitachi Koki, CT15E), and then 80 volume % of the supernatant was removed to obtain semiconductor solution A.

(2) Preparation of Gate Insulation Layer Material 61.29 g (0.45 mol) of methyltrimethoxysilane (hereinafter referred to as MTMSi), 12.31 g (0.05 mol) of β-(3,4-epoxycyclohexyl)ethyltrimethoxysilane (hereinafter referred to as β-EpETMSi), and 99.15 g (0.5 mol) of phenyltrimethoxysilane (hereinafter referred to as PhTMSi) were dissolved in propylene glycol monobutyl ether having a volume of 203.36 g and a boiling point of 170°C. 54.90 g of water and 0.864 g of phosphoric acid were added to this while stirring. The resulting solution was heated for 2 hours at a bath temperature of 105°C, and the internal temperature was raised to 90°C, and a component mainly consisting of by-produced methanol was distilled off. Next, the bath temperature was set to 130° C. and the mixture was heated for 2.0 hours, the internal temperature was raised to 118° C., and components mainly consisting of water and propylene glycol monobutyl ether were distilled out. The mixture was then cooled to room temperature, and a gate insulating layer material A having a solid content concentration of 26.0 mass % was obtained.

(3) Fabrication of Semiconductor Element In this example, as shown in the first embodiment, a multi-gate TFT was fabricated which included two gate electrodes and three electrodes serving as source or drain, and had an L/W of 10/1200 μm per channel.

A 100 nm thick aluminum thin film was vacuum-deposited on a 1 mm thick glass substrate by resistance heating. A photoresist (product name "LC100-10cP", manufactured by Rohm and Haas Co., Ltd.) was spin-coated (1000 rpm x 20 seconds) on top of the substrate and dried by heating at 100°C for 10 minutes. The photoresist film thus produced was pattern-exposed through a mask using a parallel light mask aligner (PLA-501F manufactured by Canon Inc.), and then developed with ELM-D (product name, manufactured by Mitsubishi Gas Chemical Co., Ltd.), a 2.38 wt% aqueous solution of tetramethylammonium hydroxide, for 30 seconds while stirring, and then washed with water for 30 seconds. The film was then etched with mixed acid (product name SEA-5, manufactured by Kanto Chemical Co., Ltd.) for 6 minutes, and then washed with water for 30 seconds. The resist was removed by immersing the substrate in AZ Remover 100 (product name, manufactured by AZ Electronic Materials Co., Ltd.) for 2 minutes, washed with water for 30 seconds, and then heated and dried at 120°C for 20 minutes to form a gate electrode.

Gate insulating layer material A, which will become the gate insulating layer, was then dropped onto the substrate and rotated with a spin coater at 200 rpm for 5 seconds, followed by 700 rpm for 15 seconds to coat the substrate evenly. The insulating layer was then hardened by applying a certain amount of heat to the substrate through an annealing process, resulting in a gate insulating layer with a thickness of 350 nm. Furthermore, after pattern exposure through a mask using a parallel light mask aligner, the gate insulating layer in a specified position was developed by dip development in ELM-D for 40 seconds, and then washed with water for 30 seconds to expose the electrode in the contact hole.

Next, a 60 nm-thick gold thin film was vacuum-deposited by resistance heating. A photoresist was spin-coated (1000 rpm x 20 seconds) on top of it, and dried by heating at 100°C for 10 minutes. The photoresist film thus produced was pattern-exposed through a mask using a parallel light mask aligner, and then developed with ELM-D using an automatic developing device (Takizawa Sangyo Co., Ltd. AD-2000) while stirring for 30 seconds, and then washed with water for 30 seconds. After that, the film was etched for 6 minutes with AURUM-302 (product name, Kanto Chemical Co., Ltd.), and then washed with water for 30 seconds. The resist was peeled off by immersion in AZ Remover 100 for 2 minutes, washed with water for 30 seconds, and then dried by heating at 120°C for 20 minutes to form source and drain electrodes.

Next, 1 μL of semiconductor solution A containing CNTs was dropped between the source electrode and the drain electrode by the inkjet method, and the solution was air-dried at 30°C for 10 minutes. After that, the solution was heat-treated at 150°C for 30 minutes under a nitrogen stream on a hot plate to form a semiconductor layer for a p-type FET and a semiconductor layer for an n-type FET.

Through the above process, a total of 21 pairs of semiconductor elements each containing two gate electrodes and three source or drain electrodes were fabricated on three substrates under the same conditions. The element area for one pair is 101,736 square μm, which corresponds to a circle with a diameter of 360 μm. Dividing this by the channel length W = 1,200 μm gives a length per 1 μm of channel length of 84.78 μm.

(4) Evaluation of Semiconductor Element The Vg (gate voltage)-Id (drain current) characteristics of the TFT in each of the two channel portions of the element were measured using a semiconductor parameter analyzer (Keysight Technology B1500A), and the characteristic difference between the two TFTs was evaluated.

When the relative variation of the 21 pairs was expressed as a frequency distribution in 10% increments, the variation value where the cumulative frequency distribution exceeded 90% was +110%, and the maximum variation was +160%.

The relative variation value here is the value obtained by dividing the larger value of the drain current Id for two TFTs by the smaller value when the gate voltage Vg = 5V and the drain current Vd = 5V, and is expressed as a percentage.

<Comparative Example 1>
A total of 19 single-gate TFTs each including one gate electrode and two source or drain electrodes and each having an L/W of 10/1400 μm per channel were fabricated on three substrates identical to those shown in Example 1. In this Comparative Example 1, the items in which no particular clear difference is noted are the same as those in Example 1.

The element area for one pair is 141,300 square μm, which is equivalent to two circles with a diameter of 300 μm. When this is divided by the channel length W = 1,400 μm, the length per 1 μm of channel length is 100.94 um.

The Vg-Id characteristics of the TFTs of each of these 19 semiconductor elements were measured using a semiconductor parameter analyzer (Keysight Technology B1500A), and the difference in characteristics between the two TFTs was evaluated for 15 pairs of two semiconductor elements that were physically adjacent to each other.

When the relative variation of the 21 pairs was frequency-distributed in 10% increments, the variation value where the cumulative frequency distribution exceeded 90% and the maximum variation were both greater than +500%.

The ratio of channel length per 1 μm in Example 1 and Comparative Example 1 showed an improvement in area efficiency of 18.2%. Furthermore, the relative variation in adjacent TFTs was also shown to be superior in Example 1 to Comparative Example 1.

10 Substrate 50 Gate insulating layer 110, 111, 112 Source or drain electrode 200, 201 Gate electrode 300, 301 Channel region 400 Semiconductor layer Wm Maximum channel width dm of TFT Maximum inter-channel space of TFT 500, 503, 504, 505 Multi-gate p-type TFT
501, 502 Single gate p-type TFT
510 Multi-gate n-type TFT
511, 512 Single gate TFT
580, 581, 582, 583 Gate wiring 571, 572, 575 Input wiring 530, 532 Input 1 wiring 531, 533 Input 2 wiring 536, 537, 576 Output wiring 538 Wiring 573 Output 1 wiring 574 Output 2 wiring 540, 541, 542, 543, 544 Power supply wiring 545, 546 GND wiring 550, 551, 552, 553 Interlayer vias 560, 561, 562 Channel on current 590, 591 Current mirror circuit 592 Cascode type current mirror circuit 600, 603, 607 Power supply lines 601, 604, 608 Current sources 602, 605, 606, 609 Load

Claims (14)

1. A thin film transistor having at least two channel regions,
A substrate;
At least three electrodes serving as drains or sources;
at least two gate electrodes;
a gate insulating layer in contact with each of the at least two gate electrodes;
an island-shaped semiconductor layer spanning the at least two channel regions;
having
A thin film transistor, wherein a maximum value Wm of a channel width of the thin film transistor and a maximum value dm of a distance between the two or more gate electrodes satisfy a relationship of Wm>dm . 1. A thin film transistor having at least two channel regions,
A substrate;
At least three electrodes serving as drains or sources;
at least two gate electrodes;
a gate insulating layer in contact with each of the at least two gate electrodes;
an island-shaped semiconductor layer spanning the at least two channel regions;
having
The semiconductor layer is a thin film transistor having a shape in which a plurality of carbon nanotubes are arranged in a network shape. 3. The thin film transistor according to claim 2 , wherein a maximum value Wm of the channel width of the thin film transistor and a maximum value dm of the distance between the two or more gate electrodes satisfy the relationship Wm>dm . 4. The thin film transistor according to claim 1, wherein the island-shaped semiconductor layer has a circular planar shape . The thin film transistor according to claim 1 , wherein the semiconductor layer contains at least one material selected from the group consisting of an organic semiconductor, graphene, and a carbon nanotube . The thin-film transistor according to any one of claims 1 to 5, wherein the semiconductor layer contains carbon nanotubes having a conjugated polymer attached to at least a portion of the surface. A thin-film transistor according to any one of claims 1 to 6, wherein the substrate is flexible. 8. The thin film transistor according to claim 1, wherein at least two of all the gate electrodes included in the thin film transistor are electrically independent from each other . A semiconductor device including a thin-film transistor according to any one of claims 1 to 8. A semiconductor device including the thin film transistor according to claim 8,
The semiconductor device is configured such that the potentials of at least two of the gate electrodes of the thin film transistors are independently controlled. 1. A thin film transistor having at least two channel regions,
A substrate;
At least three electrodes serving as drains or sources;
at least two gate electrodes;
a gate insulating layer in contact with each of the at least two gate electrodes;
an island-shaped semiconductor layer spanning the at least two channel regions;
A thin film transistor having
A semiconductor device comprising:
Among all the gate electrodes included in the thin film transistor, at least one pair of adjacent two gate electrodes are connected by a common electrical wiring;
One drain or source electrode sandwiched between the two adjacent gate electrodes is a common electrode,
Two drain or source electrodes disposed outside the two adjacent gate electrodes are connected to different electrical wirings;
An on-current flowing through two channel regions controlled by the two gate electrodes is
from the common electrode towards the two outer drain or source electrodes; or
A semiconductor device in which current flows from the two drain or source electrodes disposed on the outside toward the common electrode. 1. A method for manufacturing a thin film transistor having at least two channel regions, comprising the steps of:
The thin film transistor is a thin film transistor according to any one of claims 1 to 8,
The method for producing a thin film transistor is characterized in that the island-shaped semiconductor layer is formed by a coating method. The method for manufacturing a thin film transistor according to claim 12, wherein the coating method is one of an inkjet method, a nozzle coating method, a screen printing method, an offset printing method, and a drop cast coating method, in which the material containing the semiconductor layer is formed. The method for manufacturing a thin-film transistor according to claim 12 or 13, wherein the glass transition temperature of the substrate is 200°C or less.

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