JP2015207704A - Thin film transistor array and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a thin film transistor array of large accumulation capacity, with less power consumption, and high display quality, and to provide a method of manufacturing the thin film transistor array at a high throughput with good alignment precision.SOLUTION: A thin film transistor array includes a plurality of thin film transistors containing an insulation substrate, a source electrode, a drain electrode formed with a predetermined interval against the source electrode, a pixel electrode connected to the drain electrode, and a semiconductor pattern formed at least in a gap between the source electrode and the drain electrode. It also includes a plurality of source wirings connected to the source electrode and a plurality of liquid repellent insulation layer patterns that contain a material which repels the semiconductor pattern, being formed in stripe with the semiconductor pattern in between.

Description

  The present invention relates to a thin film transistor array and a method for manufacturing the same.

  Due to the remarkable development of information technology, information is frequently sent and received at notebook computers and portable information terminals. It is a well-known fact that in the near future, a ubiquitous society that can exchange information regardless of location will come. In such a society, a lighter and thinner information terminal is desired.

  Among electronic members used for such information terminals, the mainstream of semiconductor materials currently used for thin film transistors is silicon-based. Since formation of a thin film transistor using a silicon-based material includes a high temperature process, the substrate material of the thin film transistor is required to be able to withstand the process temperature. For this reason, glass is generally used as a substrate for forming a thin film transistor.

  However, when glass is used in configuring the information terminal described above, the information terminal is heavy, inflexible, and can be broken by a drop impact. Therefore, it can be said that these characteristics resulting from the formation of thin film transistors on glass are undesirable as information terminals in the ubiquitous society.

  Therefore, in recent years, organic semiconductors have attracted attention as semiconductor materials for thin film transistors. Organic semiconductor materials do not require a heat treatment step at a high temperature unlike silicon-based materials, and thus have an advantage that they are provided on a flexible plastic substrate. Furthermore, since it can be produced by a printing process without using a vacuum process, there is an advantage that the cost can be reduced.

  In order to form a semiconductor layer from a solution, a spin coating method, a dip method, an ink jet method, or the like can be used. Among these, in a thin film transistor array in which a plurality of transistors manufactured by a spin coating method or a dip method are arranged, a current easily flows in a semiconductor layer between transistor elements or between a transistor and a pixel electrode. There is a problem that the (leakage current) value increases and the on / off ratio decreases. For this reason, for example, in Patent Document 1, transistor element isolation is realized by forming an organic semiconductor layer at a desired location using an inkjet method. For example, in Patent Document 2, the arrangement of the thin film transistor array is optimized so that the organic semiconductor layer can be formed in a stripe shape, and the organic semiconductor solution is formed by flexographic printing.

Japanese Patent Laid-Open No. 2005-210086 JP 2008-235861 A

  However, when the ink jet method is used, since organic semiconductors generally have low solubility in solvents, organic semiconductors are often deposited in the vicinity of nozzles, resulting in poor ejection. Further, the method of injecting the organic semiconductor solution into the channel portion has a problem that the throughput is low.

  In addition, when forming an independent pattern by flexographic printing, when the organic semiconductor solution is transferred from anilox to the flexographic plate, it is transferred depending on whether the convex portion of the flexographic plate enters the concave portion of the anilox or the bank portion. The amount of liquid is different and the thickness of the deposited film varies. Variation in film thickness results in variations in characteristics of thin film transistors.

  Further, when the organic semiconductor layer has a stripe shape parallel to the source wiring, there is a problem that the capacitor electrode, the gate insulating film, and the pixel electrode cannot be formed in the region, and the storage capacity cannot be increased. In addition, when the organic semiconductor layer has a stripe shape parallel to the gate wiring, current flows between the source wiring and drain electrode of the adjacent pixel and crosstalk occurs in the gate wiring direction, or current flows between the source wiring of the adjacent pixels. There is a problem that power consumption increases due to flow.

  It is an object of the present invention to provide a structure of a thin film transistor array having a large storage capacity, low power consumption, and high display quality, and a method for manufacturing a thin film transistor array using the structure with high throughput and high alignment accuracy. .

  One aspect of the invention for solving the above problems is an insulating substrate, a source electrode, a drain electrode formed with a predetermined gap from the source electrode, a pixel electrode connected to the drain electrode, and at least a source A plurality of thin film transistors having a semiconductor pattern formed in a gap between an electrode and a drain electrode, a plurality of source wirings to which the source electrode is connected, and a material that repels the semiconductor pattern, and formed in a stripe shape with the semiconductor pattern interposed therebetween And a plurality of liquid repellent insulating layer patterns.

  Further, the liquid repellent insulating layer pattern may have a stripe shape orthogonal to the source wiring.

  Further, the liquid repellent insulating layer pattern may have a stripe shape parallel to the source wiring.

  Further, a protective layer may be provided on the semiconductor pattern, and the protective layer may have a stripe shape extending over a plurality of semiconductor patterns in a direction orthogonal to the liquid repellent insulating layer pattern.

  Further, the capacitor electrode may be further included, and a portion where the semiconductor pattern is printed in a stripe shape and is repelled by the liquid repellent insulating layer pattern may overlap the capacitor electrode and the pixel electrode.

  In addition, an interlayer insulating film having an opening on the pixel electrode and an upper pixel electrode connected to the pixel electrode through the opening on the interlayer insulating film may be further included.

  Another aspect of the present invention is a method of manufacturing the above-described thin film transistor array, the step of forming a source electrode, a source wiring, a drain electrode, and a pixel electrode on an insulating substrate, and a pixel electrode and / or a source wiring. A step of forming a liquid-repellent insulating film pattern on the substrate, and a step of forming a semiconductor pattern by printing a material forming the semiconductor pattern in a stripe shape orthogonal to the liquid-repellent insulating layer pattern. This is a method of manufacturing a thin film transistor array, wherein in the step of printing a pattern material, an independent semiconductor pattern is formed between the liquid-repellent insulating film patterns by causing the semiconductor pattern to repel the liquid-repellent insulating film pattern.

  According to the present invention, the liquid-repellent insulating film pattern is provided on the pixel electrode and / or the source wiring, so that even if a stripe-shaped semiconductor layer is printed on the liquid-repellent insulating layer pattern, each pixel is independent. A semiconductor pattern can be formed. Therefore, since the capacitor electrode and the pixel electrode can be formed in a region between the gate electrode and the capacitor wiring in a plan view, the storage capacity can be increased. Further, since a stripe-shaped semiconductor layer that is relatively simple in patterning and easy to align is printed, high throughput and alignment accuracy can be realized.

The top view which shows the thin-film transistor array which concerns on the 1st Embodiment of this invention The top view which shows the thin-film transistor which concerns on the 1st Embodiment of this invention Sectional drawing which shows the thin-film transistor which concerns on the 1st Embodiment of this invention 1 is a plan view showing a method for manufacturing a thin film transistor according to a first embodiment of the present invention. 1 is a plan view showing a method for manufacturing a thin film transistor according to a first embodiment of the present invention. The top view which shows the thin-film transistor array which concerns on the 2nd Embodiment of this invention The top view which shows the thin-film transistor concerning the 2nd Embodiment of this invention The top view which shows the thin-film transistor array which concerns on the 3rd Embodiment of this invention The top view which shows the thin-film transistor concerning the 3rd Embodiment of this invention The top view which shows the thin-film transistor array which concerns on the 4th Embodiment of this invention The top view which shows the thin-film transistor which concerns on the 4th Embodiment of this invention

(First embodiment)
The thin film transistor array 100 according to the first embodiment of the present invention and the thin film transistor 101 constituting the thin film transistor array 100 are shown in FIGS. FIG. 1 is a plan view of a thin film transistor array 100 in which the interlayer insulating film 11 and the upper pixel electrode 13 are omitted for explanation. 2 and 3 are a plan view and a cross-sectional view of the thin film transistor 101 constituting one pixel of the thin film transistor array 100 in which the interlayer insulating film 11 and the upper pixel electrode 13 are similarly omitted. As shown in FIGS. 2 and 3, the thin film transistor 101 according to the present embodiment is connected to the gate electrode 2 and the gate wiring 3 connected to the gate electrode 2, and the capacitor electrode 14 and the capacitor electrode 14 on the insulating substrate 1. The capacitor wirings 15 are stacked. A gate insulating film 4 is stacked thereon, and a source electrode 5 and a drain electrode 7 having a gap in a region overlapping with the gate electrode 2 when viewed from above are stacked on the gate insulating film 4. The drain electrode 7 is connected to the pixel electrode 10 that overlaps the capacitor electrode 14 when viewed from above. A source wiring 6 is connected to the source electrode 5. On the pixel electrode 10 and / or the source wiring 6, a liquid repellent insulating film 16 pattern having a property of repelling a material for forming a semiconductor layer 8 ′ described later is laminated. When viewed from above, the semiconductor pattern 8 is stacked in the gap between the source electrode 5 and the drain electrode 7, and the protective layer 9 is stacked so as to cover the semiconductor pattern 8. As shown in FIG. 1, in the thin film transistor array 100, the liquid repellent insulating film 16 and the protective layer 9 are formed in a stripe shape across the plurality of thin film transistors 101.

  In the thin film transistor 101, the source electrode 5 and the drain electrode 7 are formed in a comb shape when viewed from above. The comb shape is selected to increase the effective channel width and increase the current, but is not limited to this shape. Further, the drain electrode 7 has a single linear shape. As a result, only one portion of the drain electrode 7 that overlaps with the gate electrode 2 and does not form a channel, that is, a portion for supplying power to the channel, is required, so that the gate-drain capacitance is reduced and the gate voltage is reduced. A so-called gate field-through voltage, in which the voltage change when changing from on to off affects the pixel potential, can be suppressed to a small level, and the display quality is improved.

  The gate electrode 2, the capacitor electrode 14, the source electrode 5, the drain electrode 7, and the pixel electrode 10 may have a polygonal shape, a curved shape, or the like, but the tip is preferably rounded. Thereby, there is no electric field concentration during driving, and deterioration of the semiconductor 8 pattern and the gate insulating film 4 can be suppressed. Moreover, since the space | interval between electrodes becomes wide, the short circuit between electrodes can be suppressed (The electrode pattern of FIG. 2 was made into the polygonal shape).

  The liquid repellent insulating layer 16 pattern has a stripe shape parallel to the gate wiring 3 and is formed so as to extend over a plurality of pixels. As a result, even if the semiconductor layer 8 ′ is printed in a stripe shape orthogonal to the pattern of the liquid repellent insulating layer 16, the semiconductor 8 ′ is not bounced and formed on the liquid repellent insulating layer 16, and is independent for each pixel. The semiconductor pattern 8 can be formed. This facilitates the formation and alignment of the semiconductor pattern 8 independent of each transistor. The stripe patterning which is relatively simple is easy, and alignment is easy because there is no influence even if the position is shifted in the direction parallel to the gate wiring 3.

  Further, since the semiconductor layer 8 ′ is repelled on the liquid repellent insulating layer 16, the capacitor electrode 14 and the pixel electrode 10 are formed in the lower layer of the liquid repellent insulating layer 16 so that the semiconductor pattern 8 and the capacitor electrode and It can be formed so as not to overlap with the pixel electrode. For this reason, almost all the portions (non-transistor portions) where the semiconductor pattern 8 is not formed in the thin film transistor 101 can be used as the storage capacitor, and the storage capacitor can be increased. Further, since the semiconductor pattern 8 is formed on the pixel electrode 10, a current flows between the source electrode 5 and the pixel electrode 10 even in the off state, and the problem that the on / off ratio becomes small can be avoided.

  Further, the protective layer 9 has a stripe shape continuously formed over a plurality of pixels in a direction orthogonal to the liquid repellent insulating layer 16 pattern (a direction orthogonal to the gate wiring 3). This facilitates the formation and alignment of the protective layer 9. The stripe patterning which is relatively simple is easy, and alignment is easy because there is no influence even if the position is shifted in the direction parallel to the gate wiring 3.

  As the insulating substrate 1, it is desirable to use a flexible substrate. Examples of generally used materials for the substrate 1 include polyethylene terephthalate (hereinafter sometimes referred to as “PET”), polyimide, polyethersulfone (hereinafter also referred to as “PES”), polyethylene naphthalate (hereinafter referred to as “PET”). PEN ”) and plastic materials such as polycarbonate. A glass substrate 1 such as quartz, a silicon wafer, or the like can be used as the insulating substrate 1, but a plastic substrate is preferable in consideration of thickness reduction, weight reduction, and flexibility. In consideration of the temperature used in each manufacturing process, it is desirable to use PEN, polyimide, or the like as the substrate 1.

  The material used as the electrode material is not particularly limited, but generally used materials include metal such as gold, platinum, nickel, indium tin oxide, or a thin film of oxide or poly (ethylenedioxythiophene). ) / Polystyrene sulfonate (PEDOT / PSS), conductive polymer such as polyaniline, gold colloidal particles such as gold, silver and nickel, or thick film paste using silver or other metal particles as a conductive material is there. Further, the electrode forming method is not particularly limited, and a dry film forming method such as vapor deposition or sputtering may be used. However, in consideration of flexibility and cost reduction, it is desirable to form the film by a wet film forming method such as screen printing, reversal offset printing, letterpress printing, flexographic printing, or an ink jet method. Further, the degree of roundness of the electrode pattern is preferably a curvature radius of 2 μm or more, and more preferably 5 μm or more. However, the radius of curvature cannot be increased as much as possible, and since it is necessary to form a pattern, the upper limit is generally about 1/10 of the pixel size.

  The material used for the gate insulating film 4 is not particularly limited, but generally used materials include polymer solutions such as polyvinyl phenol, polymethyl methacrylate, polyimide, polyvinyl alcohol, and epoxy resin, alumina, and silica gel. There are solutions in which particles such as are dispersed. A thin film such as PET, PEN, or PES may be used as the gate insulating film 4.

  The material used as the liquid repellent insulating layer 16 is not particularly limited, but is a material that repels the material of the semiconductor layer 8 ′ printed on the liquid repellent insulating layer 16. For example, a material obtained by adding a fluorine or fluorine-containing substituent having high water repellency or high oil repellency or an oligomer or polymer containing a siloxane group in the side chain or main chain to the gate insulating film 4 material can be used. Examples of water- and oil-repellent materials include long-chain fluoroalkylsilanes, hydrolyzable group-containing siloxanes, and fluoroalkyl group-containing oligomers.

  The materials used as the semiconductor layer 8 ′ and the semiconductor pattern 8 are not particularly limited, but generally used materials include polymer systems such as polythiophene, polyallylamine, fluorenebithiophene copolymer, and derivatives thereof. There are organic semiconductor materials and low molecular weight organic semiconductor materials such as pentacene, tetracene, copper phthalocyanine, perylene, and derivatives thereof. However, it is desirable to use an organic semiconductor material to which the printing method can be applied in consideration of cost reduction, flexibility, and large area. Carbon compounds such as carbon nanotubes or fullerenes, semiconductor nanoparticle dispersions, and the like may also be used as the semiconductor material.

  As a printing method for forming the semiconductor layer 8 ′ using an organic semiconductor material, known methods such as gravure printing, offset printing, screen printing, and an inkjet method can be used. In general, since the organic semiconductor material described above has low solubility in a solvent, it is desirable to use relief printing, flexographic printing, reverse offset printing, an inkjet method, and a dispenser method suitable for printing a low viscosity solution. In particular, letterpress printing is most preferable because it requires a short printing time and uses a small amount of ink, and is suitable for printing stripe shapes. By forming the semiconductor layer 8 ′ in a stripe shape, the distribution of variations in film thickness due to the anilox irregularities is averaged within the stripe shape, and the film thickness of the semiconductor layer 8 ′ becomes constant, and the TFT characteristics can be made uniform.

  The material used for the protective layer 9 is not particularly limited, but generally includes a fluorine-based resin and a silicon-based resin. As a printing method for forming the protective layer 9, known methods such as letterpress printing, flexographic printing, reverse offset printing, an ink jet method, a dispenser method, and the like can be used.

  The material used for the interlayer insulating film 11 is not particularly limited, but generally used materials include organic materials such as polyvinylphenol, polymethyl methacrylate, polyimide, polyvinyl alcohol, and epoxy resin. For the layer formation, known methods such as letterpress printing, reverse offset printing, ink jet, screen printing, spray coating, spin coating can be suitably used. However, in consideration of flexibility and cost reduction, the printing method should be used. Is preferred. Further, in order to reduce the influence of the voltage from the source wiring 6 and the source electrode 5 of the thin film transistor to the upper pixel electrode 13, it is necessary to make the film relatively thick, so that screen printing is preferable.

  The material used for the upper pixel electrode 13 is not particularly limited, but a metal such as platinum, nickel, indium tin oxide, or a thin oxide or poly (ethylenedioxythiophene) / polystyrene sulfonate (PEDOT / PSS). ) Or a conductive polymer such as polyaniline, a solution in which metal colloidal particles such as gold, silver, or nickel are dispersed, or a thick film paste that uses metal particles such as silver as a conductive material. Moreover, it does not specifically limit as a formation method, Dry-type film-forming methods, such as a vacuum evaporation method and sputtering method, are also considered. However, in consideration of flexibility and cost reduction, it is desirable to form by a printing method such as screen printing, reverse offset printing, flexographic printing, and inkjet method.

  When the thin film transistor array 100 is used as an image display substrate of a display, the type of the substrate is not particularly limited, and examples thereof include an electrophoretic display, a liquid crystal display, and an organic electroluminescence (EL) display.

  Note that a gas barrier layer, a planarizing film, or the like may be formed on the thin film transistor array 100 as necessary.

  In the thin film transistor array, the names of the source and the drain are for convenience and may be called in reverse. In the thin film transistor array 100, the electrode connected to the source wiring 6 is called a source electrode 5, and the electrode connected to the pixel electrode 10 is called a drain electrode 7.

(Thin Film Transistor Array Manufacturing Method)
Next, a method for manufacturing the thin film transistor array 100 will be described. For illustration purposes, FIGS. 4A and 4B show a thin film transistor 101 for one pixel.

  First, the gate electrode 2, the gate wiring 3, the capacitor electrode 14, and the capacitor wiring 15 are formed on the insulating substrate 1 ((a) in FIG. 4A). Next, the gate insulating film 4 is formed thereon (FIG. 4A (b)). Further, the source electrode 5, the source wiring 6, the drain electrode 7, and the pixel electrode 10 are formed ((c) in FIG. 4A). Next, a liquid repellent insulating film 16 is formed in a stripe shape parallel to the gate wiring 3 on the pixel electrode 10 and / or the source wiring 6 ((d) in FIG. 4A). Next, a semiconductor pattern 8 is formed at least between the source electrode 5 and the drain electrode 7. In forming the semiconductor pattern 8, first, the semiconductor layer 8 ′ is formed in a stripe shape parallel to the source wiring 6 as indicated by a dotted line in the figure, but the semiconductor layer 8 is formed on the liquid repellent insulating film 16. Since 'is repelled, the semiconductor pattern 8 becomes independent for each pixel ((e) of FIG. 4B). Next, a protective layer 9 is formed in a stripe shape parallel to the source wiring 6 so as to cover the semiconductor pattern 8 ((f) in FIG. 4B). At this time, it is desirable that the liquid repellent insulating film 16 and the protective layer 9 are continuously formed over a plurality of pixels. Next, an interlayer insulating film 11 having a hole 12 is formed on the pixel electrode 10 ((g) in FIG. 4B). Finally, an upper pixel electrode 13 connected to the pixel electrode 10 through the hole 12 in the interlayer insulating film 11 is formed ((h) in FIG. 4B). In this manner, since the stripe-shaped semiconductor layer 8 ′ that is relatively simple in patterning and easy to align is printed, high throughput and alignment accuracy can be realized.

(Second Embodiment)
Next, a thin film transistor array 200 according to a second embodiment of the present invention and a thin film transistor 201 constituting the thin film transistor array 200 are shown in FIGS. FIGS. 5 and 6 are plan views showing the thin film transistor array 200 and the thin film transistor 201 as one pixel portion thereof, in which the interlayer insulating film 11 and the upper pixel electrode 13 are omitted for explanation. The thin film transistor array 200 is substantially the same as the thin film transistor array 101, except that the liquid repellent insulating film 16 pattern is formed in a different place. That is, the liquid repellent insulating film 16 pattern has a stripe shape parallel to the source wiring 6 and is formed so as to extend over a plurality of pixels. Thereby, even if the semiconductor layer 8 is printed in a stripe shape, the semiconductor layer 8 ′ is not repelled and formed on the liquid repellent insulating film 16, and an independent semiconductor pattern 8 can be formed for each pixel. it can. Therefore, it becomes easy to form and align a semiconductor pattern independent for each pixel. Patterning in a simple stripe shape is easy, and alignment is easy because there is no influence even if the position is shifted in a direction parallel to the gate wiring 3.

(Third and fourth embodiments)
Next, thin film transistor arrays 300 and 400 and thin film transistors 301 and 401 constituting them according to the third and fourth embodiments of the present invention are shown in FIGS. 7 to 10 are also abbreviated as an interlayer insulating film 11 and an upper pixel electrode 13 for explanation. 7 and 8 are plan views showing the thin film transistor array 300 and the thin film transistor 301 of one pixel portion thereof. 9 and 10 are plan views showing the thin film transistor array 400 and the thin film transistor 401 of one pixel portion thereof. The thin film transistor 301 and the thin film transistor 401 are substantially the same as the thin film transistor 201, but the shape of the pixel electrode 10 is different. In the thin film transistor 401, a part of the source electrode 5 and the drain electrode 7 have an L shape. Although it is not necessary to be limited to these shapes, it is preferable that the portion where the drain electrode 7 and the pixel electrode 10 do not overlap the gate electrode 2 and the capacitor electrode 14 respectively do not overlap the semiconductor pattern 8. This is because it becomes impossible to control the current that flows when the gate electrode and the capacitor electrode are turned off by the voltage ratio of the gate electrode and the capacitor electrode, leading to a decrease in the on / off ratio.

  In each of the thin film transistor arrays 200, 300, and 400, the liquid repellent insulating film 16 and the protective layer 9 are formed in a stripe shape across the plurality of thin film transistors 201, 301, and 401.

Example 1
A first embodiment of the present invention will be described with reference to FIG.

  A polyethylene naphthalate (PEN) film was used as the insulating substrate 1. Silver ink was transferred and printed on the PEN substrate and dried at 180 ° C. for 1 hour to obtain a gate electrode 2, a gate wiring 3, a capacitor electrode 14, and a capacitor wiring 15 having a film thickness of 100 nm.

  Next, polyvinyl phenol was applied by a die coater and dried at 180 ° C. for 1 hour to form the gate insulating film 4.

  Silver ink was transferred onto the gate insulating film 4 and dried at 180 ° C. for 1 hour to obtain a source electrode 5, source wiring 6, drain electrode 7, and pixel electrode 10 having a thickness of 100 nm.

  As the liquid repellent insulating layer 16, a solution obtained by adding 1.0% by weight of a long-chain fluoroalkylsilane to polyimide was used. Further, a photosensitive resin relief plate was used as the relief plate. Then, a stripe pattern is printed in a direction parallel to the gate wiring 3 by letterpress printing using a 150-line anilox roll on a region other than the gate electrode 2 and dried at 100 ° C. for 60 minutes to obtain a liquid repellent insulating layer. 16 was formed.

  As a material for the semiconductor layer 8 ′, a solution in which TIPS pentacene was dissolved in tetralin to 1.0% by weight was used. Further, a photosensitive resin relief plate was used as the relief plate. Then, a stripe-shaped semiconductor layer 8 ′ along the source wiring 6 was printed by letterpress printing using a 150-line anilox roll. At that time, the semiconductor layer 8 ′ on the liquid repellent insulating layer 16 was bounced to obtain a rectangular semiconductor pattern 8 independent of each pixel. Thereafter, the semiconductor pattern 8 was formed by drying at 100 ° C. for 60 minutes.

  As the material for the protective layer 9, a fluorine-based resin that is a fluorine-containing compound was used. A stripe pattern covering the semiconductor pattern 8 and parallel to the source wiring 6 was formed by letterpress printing using a 150-line anilox roll, and vacuum-dried at 90 ° C. for 2 hours to form a protective layer 9.

  The interlayer insulating film 11 was formed by screen printing using an epoxy resin material paste and baking at 100 ° C. for 60 minutes.

  The upper pixel electrode 13 was formed by screen printing using a silver paste and firing at 100 ° C. for 60 minutes.

  An electrophoretic body was sandwiched between the thin film transistor thus manufactured and a PET substrate having a transparent electrode, and a predetermined drive waveform was applied, thereby obtaining a good display with a large storage capacity and no crosstalk. In addition, a display with low power consumption and hardly deteriorated was obtained.

(Example 2)
A second embodiment of the present invention will be described with reference to FIG.

  A polyethylene naphthalate (PEN) film was used as the insulating substrate 1. Silver ink was transferred and printed on the PEN substrate and dried at 180 ° C. for 1 hour to obtain a gate electrode 2, a gate wiring 3, a capacitor electrode 14, and a capacitor wiring 15 having a film thickness of 100 nm.

Next, polyvinyl phenol was applied by a die coater and dried at 180 ° C. for 1 hour to form the gate insulating film 4.

  Silver ink was transferred onto the gate insulating film 4 and dried at 180 ° C. for 1 hour to obtain a source electrode 5, source wiring 6, drain electrode 7, and pixel electrode 10 having a thickness of 100 nm.

  As the liquid repellent insulating layer 16, a solution obtained by adding 1.0% by weight of a long-chain fluoroalkylsilane to polyimide was used. Further, a photosensitive resin relief plate was used as the relief plate. Then, a stripe pattern is printed along the source wiring 6 by relief printing using a 150-line anilox roll on the region other than the gate electrode 2 and dried at 100 ° C. for 60 minutes to form the liquid repellent insulating layer 16. Formed.

  As a material for the semiconductor layer 8 ', a solution in which TIPS pentacene was dissolved with tetralin so as to be 1.0% by weight was used. Further, a photosensitive resin relief plate was used as the relief plate. Then, a stripe-shaped semiconductor layer 8 ′ parallel to the gate wiring 3 was printed by letterpress printing using a 150-line anilox roll. At that time, the semiconductor layer 8 ′ on the liquid repellent insulating film 16 was bounced to obtain a rectangular semiconductor pattern 8 independent of each pixel. Thereafter, the semiconductor pattern 8 was formed by drying at 100 ° C. for 60 minutes.

  As the material for the protective layer 9, a fluorine-based resin that is a fluorine-containing compound was used. A stripe pattern covering the semiconductor pattern 8 and parallel to the gate wiring 3 was formed by letterpress printing using a 150-line anilox roll, and vacuum-dried at 90 ° C. for 2 hours to form a protective layer 9. .

  The interlayer insulating film 11 was formed by screen printing using an epoxy resin material paste and baking at 100 ° C. for 60 minutes.

  The upper pixel electrode 13 was formed by screen printing using a silver paste and firing at 100 ° C. for 60 minutes.

  An electrophoretic body was sandwiched between the thin film transistor thus manufactured and a PET substrate having a transparent electrode, and a predetermined drive waveform was applied, thereby obtaining a good display with a large storage capacity and no crosstalk. In addition, a display with low power consumption and hardly deteriorated was obtained.

(Comparative Example 1)
A polyethylene naphthalate (PEN) film was used as the insulating substrate 1. Silver ink was transferred and printed on the PEN substrate and dried at 180 ° C. for 1 hour to obtain a gate electrode 2, a gate wiring 3, a capacitor electrode 14, and a capacitor wiring 15 having a film thickness of 100 nm.

Next, polyvinyl phenol was applied by a die coater and dried at 180 ° C. for 1 hour to form the gate insulating film 4.

  Silver ink was transferred onto the gate insulating film 4 and dried at 180 ° C. for 1 hour to obtain a source electrode 5, source wiring 6, drain electrode 7, and pixel electrode 10 having a thickness of 100 nm.

  As a material for the semiconductor layer 8 ', a solution in which TIPS pentacene was dissolved with tetralin so as to be 1.0% by weight was used. Further, a photosensitive resin relief plate was used as the relief plate. Then, a semiconductor layer 8 ′ having a stripe pattern parallel to the gate wiring 3 was printed by letterpress printing using a 150-line anilox roll. Thereafter, the semiconductor layer 8 ′ was formed by drying at 100 ° C. for 60 minutes.

  As the material for the protective layer 9, a fluorine-based resin that is a fluorine-containing compound was used. Then, a stripe pattern covering the semiconductor layer 8 and parallel to the gate wiring 3 was formed by letterpress printing using a 150-line anilox roll, and vacuum-dried at 90 ° C. for 2 hours to form a protective layer 9. .

  The interlayer insulating film 11 was formed by screen printing using an epoxy resin material paste and baking at 100 ° C. for 60 minutes.

  The upper pixel electrode 13 was formed by screen printing using a silver paste and firing at 100 ° C. for 60 minutes.

  An electrophoretic body was sandwiched between the thin film transistor thus fabricated and a PET substrate having a transparent electrode, and a predetermined drive waveform was applied. As a result, current flows between the source line 6 and the drain electrode 7 of the adjacent pixel, and crosstalk occurs in the direction of the gate line 3. In addition, power consumption has increased.

  The present invention is applicable to a thin film transistor array used in a liquid crystal display device, electronic paper, an organic EL display device, and the like.

DESCRIPTION OF SYMBOLS 1 Insulating substrate 2 Gate electrode 3 Gate wiring 4 Gate insulating film 5 Source electrode 6 Source wiring 7 Drain electrode 8 Semiconductor pattern 8 'Semiconductor layer 9 Protective layer 10 Pixel electrode 11 Interlayer insulating film 12 Hole of interlayer insulating film 13 Upper pixel electrode 14 Capacitor electrode 15 Capacitor wiring 16 Liquid repellent insulating film 100, 200, 300, 400 Thin film transistor array 101, 201, 301, 401 Thin film transistor

Claims (7)

An insulating substrate, a source electrode, a drain electrode formed with a predetermined gap from the source electrode, a pixel electrode connected to the drain electrode, and at least the gap between the source electrode and the drain electrode A plurality of thin film transistors having a formed semiconductor pattern;
A plurality of source lines to which the source electrode is connected;
A thin film transistor array comprising: a material that repels the material of the semiconductor pattern, and a plurality of liquid-repellent insulating layer patterns formed in a stripe shape with the semiconductor pattern interposed therebetween.   The thin film transistor array according to claim 1, wherein the liquid repellent insulating layer pattern has a stripe shape orthogonal to the source wiring.   2. The thin film transistor array according to claim 1, wherein the liquid repellent insulating layer pattern has a stripe shape parallel to the source wiring.   4. The semiconductor device according to claim 1, further comprising a protective layer on the semiconductor pattern, wherein the protective layer has a stripe shape extending over the plurality of semiconductor patterns in a direction orthogonal to the liquid repellent insulating layer pattern. Thin film transistor array. A capacitor electrode;
The thin film transistor array according to claim 1, wherein the semiconductor pattern is formed so as not to overlap the capacitor electrode and the pixel electrode.   6. The semiconductor device according to claim 1, further comprising: an interlayer insulating film having an opening on the pixel electrode; and an upper pixel electrode connected to the pixel electrode through the opening on the interlayer insulating film. Thin film transistor array. It is a manufacturing method of the thin-film transistor array in any one of Claims 1-6,
Forming a source electrode, a source wiring, a drain electrode, and a pixel electrode on an insulating substrate;
Forming a liquid repellent insulating film pattern on the pixel electrode and / or source wiring;
Printing a semiconductor pattern material in a stripe shape orthogonal to the liquid repellent insulating layer pattern,
In the step of printing the semiconductor pattern material, a thin film transistor that forms the semiconductor pattern independent between the liquid repellent insulating film patterns by causing the semiconductor pattern material to repel the liquid repellent insulating film pattern Array manufacturing method.

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