JP2010080896A - Field effect transistor, its manufacturing method, and image display - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a field effect transistor structure for reliably manufacturing a semiconductor in a channel part with excellent accuracy by using a method which applies a semiconductor solution to the channel part using a bank layer as a guide, and also to provide a method for manufacturing the field effect transistor using the structure, and an image display using the same. <P>SOLUTION: It is characterized that the field effect transistor is constituted of: a gate electrode; a gate insulating layer formed on the gate electrode; a source electrode; a lower pixel electrode; a drain electrode connected to the lower pixel electrode; a semiconductor formed between the source electrode and the drain electrode; and bank layer formed so as to interleave the semiconductor, and that the bank layer is formed in a stripe shape. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a field effect transistor including at least a gate electrode, a gate insulating layer, a source electrode, a pixel electrode and a drain electrode connected thereto, and a semiconductor formed between the source electrode and the drain electrode, and The present invention relates to a manufacturing method thereof and an image display device using the same.

  In recent years, many of the display devices such as a liquid crystal display, an organic EL display, and an electrophoretic display that have been widely used in recent years use an active matrix type drive device using a thin film transistor (TFT) as a display switching device. As such a display switch, a field effect transistor (FET) made of a semiconductor disposed between a gate electrode, a gate insulating layer, a source-drain electrode, and a source-drain electrode is used. The drive principle of FET is to control the amount of charge carrier consisting of electrons or holes in the semiconductor by applying a voltage to the gate electrode, and to control the charge transfer between the source and drain, that is, the current. It plays the role of a switch.

  Conventionally, the semiconductors of the TFT array as described above are those using amorphous or polycrystalline thin film silicon as a semiconductor. Generally, each layer such as an electrode, a semiconductor, and an insulating layer of a thin film silicon TFT is used. Requires a vacuum process and a high temperature process of 300 ° C. or higher, and is formed by a relatively complicated and expensive process such as using photolithography for patterning.

  In contrast, in recent years, it has been proposed to use a solution-dispersible nanometal particle as an electrode material, an organic semiconductor as a semiconductor, and a material that can be dissolved or dispersed in a solvent such as an organic polymer as an insulating material. Many methods using a coating method such as spin coating or flexographic printing have been reported, and it has become possible to reduce the process temperature, increase the speed, and reduce the cost.

  When a semiconductor is applied from a solution, a dispersion or precursor solution of an organic semiconductor or an oxide semiconductor having a substituent for making it soluble in a solvent is used, and a channel portion sandwiched between a source electrode and a drain electrode is used. A semiconductor is formed by applying and drying so as to cover. When applying a semiconductor solution, it is necessary to use a bank layer in which an opening is formed in a channel portion so that the solution can be applied only in a desired place, so that the solution accumulates in a recess in the opening. Yes (see Patent Document 1).

  However, when a bank layer having a rectangular or circular opening only in the channel portion is used, it is necessary to accurately align the opening of the bank layer with the channel portion, particularly when forming a bank layer using a printing method, As the coating area increases and the pixel resolution increases, there is a problem that the positions of the opening and the channel are displaced.

JP 2005-142474 A

  The present invention relates to a field effect transistor including at least a gate electrode, a gate insulating layer, a source electrode, a pixel electrode and a drain electrode connected to the pixel electrode, and a semiconductor formed between the source electrode and the drain electrode. An object of the present invention is to provide a field effect transistor structure for accurately and reliably forming a semiconductor in a channel portion by using a method of applying a semiconductor solution using a bank layer as a guide. In addition, a method of manufacturing a field effect transistor using the structure and an image display device using the method are provided.

The invention according to claim 1, which has been made to solve the above problem, is connected to a gate electrode, a gate insulating layer formed on the gate electrode, a source electrode, a lower pixel electrode, and the lower pixel electrode. The bank layer is formed in a stripe shape in a field effect transistor comprising a drain electrode formed, a semiconductor formed between the source electrode and the drain electrode, and a bank layer formed so as to sandwich the semiconductor This is a field effect transistor.
The invention according to claim 2 is the field effect transistor according to claim 1, wherein a part of the bank layer is formed in parallel with the source wiring and on the source wiring.
The invention according to claim 3 is the field effect transistor according to claim 1 or 2, wherein a part of the bank layer is formed on the pixel electrode.
The invention according to claim 4 is the field effect transistor according to any one of claims 1 to 3, wherein the bank layer has ink repellency.
The invention according to claim 5 is the field effect transistor according to any one of claims 1 to 4, wherein the bank layer contains fluorine.
The invention according to claim 6 is the field effect transistor according to any one of claims 1 to 5, wherein the bank layer has a thickness of 50 nm to 1 μm.
The invention according to claim 7 is the field effect transistor according to any one of claims 1 to 6, wherein the semiconductor is an organic semiconductor.
The invention according to claim 8 is the field effect transistor according to any one of claims 1 to 7, wherein the semiconductor is soluble or dispersible in a solvent.
The invention according to claim 9 is the field effect transistor according to any one of claims 1 to 8, wherein the semiconductor is formed in a stripe shape.
The invention according to claim 10 includes at least a step of forming a gate electrode on a substrate, a step of forming a gate insulating layer, a step of forming a source wiring, a source electrode, a drain electrode, and a lower pixel electrode, and a source An electric field comprising a step of forming a bank layer in parallel with the wiring and on the source wiring and in stripes, and a step of forming a semiconductor by applying a semiconductor solution or dispersion and drying. This is a method of manufacturing an effect transistor.
The invention according to claim 11 includes, in addition to the manufacturing method according to claim 10, at least a step of forming an interlayer insulating layer having an opening on the lower pixel electrode. It is a manufacturing method.
The invention according to claim 12 is the method of manufacturing a field effect transistor according to claim 10 or 11, wherein the step of forming the semiconductor is a step of forming the semiconductor in a stripe shape.
A thirteenth aspect of the present invention is an image display device using the field effect transistor according to any one of the first to ninth aspects.
The invention according to claim 14 is an image display device characterized in that any one of a liquid crystal display element, organic EL, and electronic paper is used for the display unit of the image display device according to claim 13.

  By forming the bank layer sandwiching the semiconductor layer in a stripe shape, it is not necessary to align exactly in the major axis direction of the stripe. By using a material or a material having a low surface energy such as a long-chain alkyl group, a semiconductor could be reliably formed in the channel portion. This makes it possible to easily manufacture a reliable TFT array.

Hereinafter, embodiments of the present invention will be described in detail.
FIGS. 1 to 5 show some or all of the basic structural examples of the field effect transistor according to the present invention. A broken line in FIGS. 1 to 4 represents an outline of one pixel when a field effect transistor is used in an image display device. FIGS. 1 to 3 are all examples in which the positional relationship between the source electrode, the drain electrode, the pixel electrode, the bank layer, and the semiconductor is captured from above the pixel. FIG. 5 shows a cross-sectional structure at the position of the thick solid line in FIG.

  As the insulating substrate 10 of the present invention, any material can be used as long as the surface is insulative, sheet-like, and the surface is flat. For example, soda lime glass, quartz glass, polyethylene terephthalate (PET), polyethylene naphthalate ( PEN), cycloolefin polymer, polyimide (PI), polyethersulfone (PES), polymethyl methacrylate (PMMA), polycarbonate (PC), polyallylate and the like can be used. In addition, even a conductive or semiconductive substrate such as a stainless steel sheet, aluminum foil, copper foil, or silicon wafer can be coated or laminated with an insulating material such as a polymer material or a metal oxide on the surface. It can be used as an insulating substrate. Further, the above insulating substrate may be provided with a surface treatment layer such as an easy adhesion layer on the surface, or may be subjected to a surface treatment such as corona treatment, plasma treatment, UV / ozone treatment.

  As the gate electrode 20 and the source wiring 40 of the present invention, the source electrode 41, the drain electrode 42, and the pixel electrode 43, metals such as Al, Cr, Mo, Cu, Au, Pt, Pd, Fe, Mn, and Ag are PVD. After forming a film by a method such as CVD, plating, or the like, it can be formed using a known method such as photolithography. In addition, known transparent conductive materials such as indium tin oxide (ITO) fluorine doped tin oxide (FTO), aluminum doped zinc oxide (AZO), gallium doped zinc oxide (GZO), PEDOT: PSS, polyaniline, polythiophene A known organic conductive material or the like can also be used. However, when these have a relatively high wiring resistance, it is more preferable to reduce the resistance by using a metal bus electrode. In addition, after processing the above metals, transparent oxides, conductive materials such as organic conductive polymers or their precursors into solutions, pastes, nanoparticle dispersions, etc., they are coated by a printing method, dried, It can also be formed by baking, photocuring or aging. The printing method used is not particularly limited, but it is better to use a patternable printing method such as letterpress printing, intaglio printing, planographic printing, reverse offset printing, screen printing, ink jet, thermal transfer printing, dispenser, etc. Simplification of the process, cost reduction, and high speed can be achieved, which is more preferable. Further, a spin coating, a die coating, a micro gravure coating, a dip coating, and the like may be combined with a patterning method such as photolithography. Further, a combination of the above printing methods may be used.

  As the gate insulating layer 30 of the present invention, polyvinylphenol (PVP), polystyrene (PS), polymethyl methacrylate (PMMA), polyvinyl alcohol (PVA), polyvinyl chloride (PVC), polyvinylidene fluoride (PVDF), polytetra Fluoroethylene (PTFE), polyimide (PI), epoxy resin, polydimethylsiloxane (PDMS), organic polymer compounds such as butadiene rubber, or a mixture thereof, or alkoxysilane group, vinyl group, acrylic ester, epoxy group, etc. Mixtures with compounds having reactive substituents can be used, and furthermore, silicon oxide, titanium oxide, tantalum oxide, aluminum oxide, niobium oxide, zirconium oxide, copper oxide, nickel oxide, indium oxide, hafnium oxide, etc. Oxidation Alternatively, these composite oxides, oxide mixtures, oxynitrides, and the like can also be used, but are not limited to these as long as they have sufficient insulating properties and can form a thin film having a thickness of 1 μm or less. Absent. Further, these may be mixed or laminated. As a method for forming these organic polymer compounds, existing wet coating methods such as micro gravure coating, dip coating, screen coating, die coating, and spin coating can be used. In addition, as a method for forming inorganic oxides, oxynitrides, etc., vacuum film formation methods such as vapor deposition, sputtering, ion plating, and CVD can be used, and any gas was used during film formation. Plasma, ion gun, radical gun, etc. may be used in combination. In addition, precursors corresponding to the respective metal oxides, specifically metal halides such as chlorides and bromides, metal alkoxides, metal hydroxides, and the like, such as acids such as hydrochloric acid, sulfuric acid and nitric acid in alcohol and water, You may form by making it react with bases, such as sodium hydroxide and potassium hydroxide, and hydrolyzing. When such a solution process is used, an existing wet coating method such as micro gravure coating, dip coating, screen coating, die coating, spin coating, or the like can be used. The above gate insulating layer may be subjected to surface treatment such as corona treatment, plasma treatment, UV / ozone treatment, but care must be taken so that the surface roughness due to the treatment does not become rough. The surface of the gate insulating layer is preferably relatively smooth and free from pinholes, protrusions, and undulations.

  A self-assembled monolayer may be formed on the uppermost layer of the gate insulating layer of the present invention. Compounds that form self-assembled monolayers include (mono, di, tri) alkoxysilane groups, (mono, di, tri) chlorosilane groups, phosphonic acid, phosphinic acid, phosphoric acid, phosphorous acid, hypoxia Has functional groups such as phosphoric acid, amino group, halide group, carboxylic acid, hydroxyl group, thiol group, disulfide group, azide group, acetylene group, vinyl group, nitro group, cyano group, alkyl group, phenyl in the molecule And those having a substituent having 2 or more carbon atoms, including at least one of a group, a phenoxy group, a thiophene ring, a pyrrole ring, a pyridine ring, a fluorene ring, an ether, an ethylene group, and an acetylene group.

  The main skeleton is preferably not branched, for example, a linear normal alkyl (n-alkyl) group, a ter-phenyl group in which three phenyl groups are arranged in series, or both sides of the phenyl group in the para position. A structure in which an n-alkyl group is arranged in the structure is preferable. Moreover, an ether bond may be included in the alkyl chain, and a carbon-carbon double bond or a triple bond may be included. Self-assembled monolayers form a monolayer on a substrate by forming a bond when one reactive substituent of the molecule interacts or reacts with a reactive site on the corresponding substrate surface. To form. When the molecules are packed more densely, the surface of the self-assembled monolayer gives a smoother and lower surface energy surface, so the main skeleton of the molecule is linear and the molecular length is uniform. It is desirable.

The compound forming the self-assembled monolayer is formed on the corresponding substrate surface by the following reaction. For example, a substance having a trichlorosilane group reacts with a silanol group on the surface of a silicon substrate and is adsorbed by a chemical bond (Non-patent Document 1 below), and phosphonic acid, phosphinic acid, etc. react with a hydroxyl group on an alumina substrate. It is well known that it is adsorbed by chemical bonds (Non-Patent Document 2 below). The self-assembled monolayer is formed by using a method of depositing the compound forming the self-assembled monomolecule on a corresponding substrate under vacuum, a method of immersing the substrate in a solution of the compound, a Langmuir-Blodgett method, or the like. However, the present invention is not limited to this. However, for example, it is more preferable to use the methods described in Non-patent Documents 3 and 4 below as a method of obtaining only a monomolecular film with a denser and more reliable compound.
[Reference 1] J. Org. Am. Chem. Soc. 102, 92 (1980)
[Reference 2] J. Org. Phys. Chem. B 107, 5877 (2003)
[Reference 3] Langmuir 19, 1159 (2003)
[Reference 4] J. Org. Phys. Chem. B 110, 21101 (2006)

  As the bank layer 50 of the present invention, polyvinyl phenol (PVP), polystyrene (PS), polymethyl methacrylate (PMMA), polyvinyl alcohol (PVA), polyvinyl chloride (PVC), polyvinylidene fluoride (PVDF), polytetrafluoro Reactions such as organic polymer compounds such as ethylene (PTFE), polyimide (PI), epoxy resin, polydimethylsiloxane (PDMS), butadiene rubber, or mixtures thereof, or alkoxysilane groups, vinyl groups, acrylate esters, epoxy groups, etc. A mixture with a compound having a functional substituent can be used, and furthermore, oxidation of silicon oxide, titanium oxide, tantalum oxide, aluminum oxide, niobium oxide, zirconium oxide, copper oxide, nickel oxide, indium oxide, hafnium oxide, etc. object, Rui it is possible to use an insulating material such as a composite oxide thereof, or oxide mixtures, oxynitride. In order to impart ink repellency to these insulating materials, a compound having an alkyl chain and a reactive substituent or a fluorine-containing compound may be added. Examples of the compound to be added include octyltrimethoxysilane, hexyltrimethoxysilane, octadecyltrichlorosilane, tridecafluoro-1,1,2,2-tetrahydrooctyltrichlorosilane, dodecyldimethylchlorosilane, hexamethylenedisilazane, Examples include octadecylphosphonic acid, octadecene, hexanoic acid, pentafluorothiophenol, and 2-perfluorooctylethanol. Furthermore, a fluorine-based polymer or a polysiloxane compound may be used, and more specifically, it is more preferable to use CYTOP (manufactured by Asahi Glass Co., Ltd.) which is a fluorine-based resin.

  As shown in FIG. 1 or 2, the bank layer of the present invention is formed in a stripe shape so that the source electrode, the drain electrode, and the channel portion sandwiched between them are openings in one pixel. Features. The width of the stripe is not particularly limited, and a bank layer may be formed only on both sides of the channel portion as shown in FIG. 1, or may be formed so as to cover the pixel electrode as shown in FIG. good. The bank layer formed on the right side of the channel portion may be integrated with the bank layer on the left side of the channel portion of an adjacent pixel. The film thickness of the bank layer is not particularly limited, but is preferably 50 nm to 1 μm. The bank layer of the present invention may form a stripe shape in either the vertical direction or the horizontal direction of the pixel as long as the channel portion has an opening, but more preferably a part of the source wiring and / or the pixel electrode. It is good to form in the direction which covers. This is to prevent the solution from being formed on the wiring or electrode material due to the magnitude of the surface energy of the wiring or electrode material when applying a solution-like semiconductor.

  When the bank layer of the present invention is formed in a stripe shape having an opening in the channel portion, the semiconductor can be reliably formed in the channel portion when the semiconductor is deposited. Such an effect can be obtained particularly when a material having a low surface energy, that is, a fluorine-based material or a material having a long-chain alkyl group is used as the bank layer. When the semiconductor is formed from a solution, the solution may be applied only in the vicinity of the channel portion, or may be formed between the bank layers in a stripe shape, but it is more sure that the stripe is formed between the bank layers in the channel portion. Since a semiconductor can be formed, it is more preferable. The semiconductor may be formed using a vacuum film formation method. As described above, when the bank layer is striped, it is not necessary to strictly align in the major axis direction of the stripe, and a reliable TFT array can be easily manufactured.

  The bank layer of the present invention is formed by forming a resist in stripes so as to cover the channel portion, and then using an existing wet coating method such as microgravure coating, dip coating, screen coating, die coating, spin coating, flexographic printing, or vapor deposition method. The bank layer can be formed by using a vacuum film forming method such as sputtering, ion plating, or CVD, and then the resist is removed. Alternatively, a method of directly forming a stripe shape as shown in FIG. 1 or 2 using an existing printing method such as offset gravure printing, reverse offset printing, screen coating, flexographic printing, or the like may be used.

  Examples of the semiconductor 60 of the present invention include π-conjugated organic polymers exhibiting semiconductivity, such as polypyrroles, polythiophenes, polyanilines, polyallylamines, fluorenes, polycarbazoles, polyindoles, poly (p-phenylene vinylene). ) And other low-molecular substances having a π-conjugated system, for example, polycyclic aromatic derivatives such as pentacene, phthalocyanine derivatives, perylene derivatives, tetrathiafulvalene derivatives, tetracyanoquinodimethane derivatives, fullerenes, carbon nanotubes However, this is not a limitation. In addition, inorganic semiconductors such as amorphous silicon, germanium, cadmium telluride, zinc selenide, gallium nitride, and aluminum nitride, and oxide semiconductors such as indium gallium zinc oxide (IGZO), zinc oxide, tin oxide, and indium oxide are used. Also good.

  As a method for forming a semiconductor of the present invention, a vacuum deposition method, a CVD method, a sputtering method, a printing method using a solution, or the like can be used, but a semiconductor soluble in a solvent is used from the viewpoint of productivity and cost reduction. It is more preferable to use the method of coating using. When using the printing method, there is no particular limitation, but letterpress printing, intaglio printing, planographic printing, reverse offset printing, screen printing method, ink jet, thermal transfer printing, dispenser, spin coating, die coating, micro gravure coating, dip A coat or the like can be used, and the above printing methods may be used in combination.

  The field effect transistor of the present invention may be used by further forming a sealing layer, an interlayer insulating layer, and an upper pixel electrode. Although the details of the field effect transistor of the present invention have been described above along the structure of one pixel, the field effect transistor of the present invention normally has a pixel lighting device of an image display device by arranging pixels in an array. Used as Specifically, an image display device having an active matrix TFT array using a field effect transistor as a back plate, and a display element such as a liquid crystal display element, organic EL, or electronic paper on the back plate is provided. It is possible to form an image display device.

  Hereinafter, the present invention will be described in detail by way of specific examples. However, these examples are for the purpose of explanation, and the present invention is not limited thereto.

[Example 1]
A field effect transistor having the same structure as that shown in FIG. 5 was formed in an 80 × 60 array. Glass having a thickness of 0.7 mm was used as the insulating substrate 10, and aluminum was formed as the gate electrode 20 to a thickness of 50 nm by vacuum vapor deposition, followed by patterning by photolithography and etching. Subsequently, 300 nm of SiON is laminated as the insulating layer 30 by a sputtering method, gold is formed to a thickness of 50 nm by a vacuum vapor deposition method, and patterned by the same method as the gate electrode, whereby the source wiring 40, the source electrode 41, the drain electrode are formed. 42 and the electrode pattern used as the pixel electrode 43 were formed. At this time, in order to increase the adhesion between the gold and the insulating layer, chromium is laminated to about 3 nm before gold is deposited.

  Subsequently, CYTOP (manufactured by Asahi Glass Co., Ltd.) was applied as a bank layer 50 by flexographic printing in a stripe shape as shown in FIG. 1, and dried at 120 ° C. for 30 minutes. Further, poly (3-hexylthiophene) (P3HT) is formed as a semiconductor 60 by stripe printing as shown in FIG. 3 by flexographic printing, and dried at 120 ° C. for 30 minutes to form a field effect transistor. Obtained.

The transfer characteristics of the field-effect transistors in the array obtained above were measured at a gate voltage of −20 V to 40 V and a source voltage of −40 V. The mobility was 0.01 cm ² / Vs, on / off was 105, and the threshold voltage. Was -5V. The standard deviation of mobility was 0.001, and a field effect transistor having substantially uniform characteristics over the entire array could be fabricated.

[Example 2]
A field effect transistor having the same structure as that shown in FIG. 5 was formed in an 80 × 60 array. Polyethylene naphthalate (PEN) having a thickness of 150 μm was used as the insulating substrate 10, and aluminum was formed as the gate electrode 20 by 50 nm by a vacuum deposition method, followed by patterning by photolithography and etching. Subsequently, 500 nm of PVP is laminated as the insulating layer 30 by spin coating, silver is patterned from a nanoparticle ink by an offset inversion printing method to a film thickness of 200 nm, and baked at 180 ° C. for 1 hour. 41, the electrode pattern used as the drain electrode 42 and the pixel electrode 43 was formed.

  Subsequently, CYTOP (manufactured by Asahi Glass Co., Ltd.) was applied as a bank layer 50 by flexographic printing in a stripe shape as shown in FIG. 1, and dried at 120 ° C. for 30 minutes. Further, 6,13-bis (triisopropylsilylethynyl) pentacene (TIPS-pentacene) is applied as a semiconductor 60 in a stripe shape as shown in FIG. 3 by flexographic printing and dried at 90 ° C. for 30 minutes. Thus, a field effect transistor was obtained.

The transfer characteristics of the field-effect transistors in the array obtained above were measured from a gate voltage of −20 V to 40 V and a source voltage of −40 V. The mobility was 0.5 cm ² / Vs, on / off was 105, and the threshold voltage. Was -10V. The standard deviation of mobility was 0.01, and a field effect transistor having substantially uniform characteristics over the entire array could be produced.

[Comparative Example 1]
A field effect transistor without a bank layer was fabricated in an 80 × 60 array. The insulating substrate 10 was prepared in the same manner as in Example 2, and electrode patterns to be the gate electrode 20, the insulating layer 30, the source wiring 40, the source electrode 41, the drain electrode 42, and the pixel electrode 43 were formed. Subsequently, the semiconductor 60 was applied in a stripe shape by flexographic printing in the same manner as in Example 2, and formed by drying at 90 ° C. for 30 minutes to obtain a field effect transistor.

When the array obtained as described above was observed, transistors in which the semiconductor did not cover the entire channel portion in some pixels were observed. When the transfer characteristics of the field effect transistors in the obtained array were measured at a gate voltage of −20 V to 40 V and a source voltage of −40 V, the maximum mobility was 0.5 cm ² / Vs, on / off was 105, and the threshold voltage was − Although it was the same as that of Example 2 at 10 V, the average mobility was 0.1 cm ² / Vs, the standard deviation was 0.2, and the characteristics of each element in the array were not uniform.

  The present invention is used for a display element such as a liquid crystal display element, organic EL, and electronic paper having an active matrix type TFT array using TFT as a back plate.

It is the example which showed a part of pixel which has a striped bank layer in this invention from the upper part. It is the example which showed a part of pixel which has a striped bank layer in this invention from the upper part. FIG. 2 is an example in which a part of a pixel having a stripe-shaped semiconductor is shown from the top in an interval where a channel portion exists in the stripe-shaped bank layer of FIG. 1. It is the example which showed the shape of the source wiring, source electrode, drain electrode, and pixel electrode in FIGS. 1-3 from the upper part. It is an example of the cross-section of the thick solid line part in FIG. 3 of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Insulating substrate 20 Gate electrode 30 Gate insulating layer 40 Source wiring 41 Source electrode 42 Drain electrode 43 Pixel electrode 50 Bank layer 60 Semiconductor

Claims (14)

  A gate electrode; a gate insulating layer formed on the gate electrode; a source electrode; a lower pixel electrode; a drain electrode connected to the lower pixel electrode; and the source electrode and the drain electrode. A field effect transistor comprising a semiconductor layer and a bank layer formed so as to sandwich the semiconductor, wherein the bank layer is formed in a stripe shape.   2. The field effect transistor according to claim 1, wherein a part of the bank layer is formed in parallel with the source wiring and on the source wiring.   3. The field effect transistor according to claim 1, wherein a part of the bank layer is formed on the pixel electrode.   The field effect transistor according to claim 1, wherein the bank layer has ink repellency.   The field effect transistor according to claim 1, wherein the bank layer contains fluorine.   6. The field effect transistor according to claim 1, wherein the bank layer has a thickness of not less than 50 nm and not more than 1 μm. The field effect transistor according to claim 1, wherein the semiconductor is an organic semiconductor. 8. The field effect transistor according to claim 1, wherein the semiconductor is soluble or dispersible in a solvent. The field effect transistor according to claim 1, wherein the semiconductor is formed in a stripe shape.   At least a step of forming a gate electrode on the substrate, a step of forming a gate insulating layer, a step of forming a source wiring, a source electrode, a drain electrode, and a lower pixel electrode, and parallel to the source wiring and on the source wiring And a step of forming a bank layer in stripes, and a step of forming a semiconductor by applying and drying a semiconductor solution or dispersion, and a method for manufacturing a field effect transistor.   11. A method for manufacturing a field effect transistor, comprising at least a step of forming an interlayer insulating layer having an opening on at least a lower pixel electrode in addition to the manufacturing method according to claim 10.   12. The method of manufacturing a field effect transistor according to claim 10, wherein the step of forming the semiconductor is a step of forming the semiconductor in a stripe shape.   An image display device using the field effect transistor according to claim 1.   14. An image display device using any one of a liquid crystal display element, organic EL, and electronic paper for the display unit of the image display device according to claim 13.

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