JP5141476B2 - FIELD EFFECT TRANSISTOR, MANUFACTURING METHOD THEREOF, AND IMAGE DISPLAY DEVICE - Google Patents

Description

  The present invention includes at least a gate electrode, a gate insulating layer, a source electrode, a lower pixel electrode and a drain electrode connected thereto, a semiconductor formed between the source electrode and the drain electrode, an interlayer insulating layer, and an upper pixel. The present invention relates to a field effect transistor composed of electrodes, a manufacturing method thereof, and an image display device using the same.

  In recent years, many of the display devices such as a liquid crystal display, an organic EL display, and an electrophoretic display that have been widely used in recent years use an active matrix type drive device using a thin film transistor (TFT) as a display switching device. As such a display switch, a field effect transistor (FET) made of a semiconductor disposed between a gate electrode, a gate insulating layer, a source-drain electrode, and a source-drain electrode is used. The drive principle of FET is to control the amount of charge carrier consisting of electrons or holes in the semiconductor by applying a voltage to the gate electrode, and to control the charge transfer between the source and drain, that is, the current. It plays the role of a switch.

  Conventionally, the semiconductors of the TFT array as described above are those using amorphous or polycrystalline thin film silicon as a semiconductor. Generally, each layer such as an electrode, a semiconductor, and an insulating layer of a thin film silicon TFT is used. Requires a vacuum process and a high temperature process of 300 ° C. or higher, and is formed by a relatively complicated and expensive process such as using photolithography for patterning.

  In contrast, in recent years, it has been proposed to use a solution-dispersible nanometal particle as an electrode material, an organic semiconductor as a semiconductor, and a material that can be dissolved or dispersed in a solvent such as an organic polymer as an insulating material. Many methods using a coating method such as spin coating or flexographic printing have been reported, and it has become possible to reduce the process temperature, increase the speed, and reduce the cost.

  When a semiconductor is applied from a solution, a dispersion or precursor solution of an organic semiconductor or an oxide semiconductor having a substituent for making it soluble in a solvent is used, and a channel portion sandwiched between a source electrode and a drain electrode is used. A semiconductor is formed by applying and drying so as to cover. When applying a semiconductor solution, it is necessary to use a bank layer in which an opening is formed in a channel portion so that the solution can be applied only in a desired place, so that the solution accumulates in a recess in the opening. Yes (see Patent Document 1). However, when adopting the upper pixel electrode to increase the pixel area, the lower pixel electrode connected to the drain electrode is connected to the upper pixel electrode, and the structure other than the connecting portion is insulated by the interlayer insulating film. An opening is also formed on the lower pixel electrode so that the bank layer does not completely cover the lower pixel electrode.

  However, if the opening of the bank layer is also formed on the lower pixel electrode, when the semiconductor solution is applied, the solution is also accumulated in the opening and a semiconductor layer is formed. As a result, there is a problem in that the via portion connecting the lower pixel electrode and the upper pixel electrode is isolated by the semiconductor, becomes high resistance, and a potential cannot be applied to the upper pixel.

JP 2005-142474 A

  The present invention includes at least a gate electrode, a gate insulating layer, a source electrode, a lower pixel electrode and a drain electrode connected thereto, a semiconductor formed between the source electrode and the drain electrode, an interlayer insulating layer, and an upper pixel. An object of the present invention is to provide a structure using a bank layer so that a semiconductor is easily formed in a field-effect transistor composed of electrodes and a problem does not occur in applying a voltage to the upper pixel electrode due to the semiconductor formation. And In addition, a method of manufacturing a field effect transistor using the structure and an image display device using the method are provided.

The invention according to claim 1, which has been made to solve the above problems, includes a gate electrode, a gate insulating layer covering the gate electrode, a source electrode, a lower pixel electrode, and a drain connected to the lower pixel electrode. An electrode, a semiconductor formed between the source electrode and the drain electrode, a bank layer that surrounds the semiconductor and covers the lower electrode, and an interlayer having an opening at least on the lower pixel electrode A field effect transistor comprising: an insulating layer; and an upper pixel electrode electrostatically connected to the lower pixel electrode through the bank layer.
The invention according to claim 2 is the field effect transistor according to claim 1, wherein the semiconductor is an organic semiconductor.
The invention according to claim 3 is the field effect transistor according to claim 1 or 2, wherein the bank layer has ink repellency.
The invention according to claim 4 is the field effect transistor according to claim 3, wherein the bank layer contains fluorine.
The invention according to claim 5 is the field-effect transistor according to any one of claims 1 to 4, wherein the bank layer has a thickness of 50 nm to 1 μm.
The invention according to claim 6 is the field effect transistor according to any one of claims 1 to 5, further comprising a sealing layer between the semiconductor and the interlayer insulating layer.
The invention according to claim 7 includes at least a step of forming a gate electrode on a substrate, a step of forming a gate insulating layer, a step of forming a source electrode, a drain electrode and a lower pixel electrode, and a source electrode and a drain. Forming a bank layer leaving an electrode and a portion sandwiched between them as an opening, applying a semiconductor solution to the opening and drying, or forming a semiconductor by vacuum-depositing a semiconductor; A method for manufacturing a field effect transistor, comprising: forming an interlayer insulating film having an opening on a pixel electrode; and forming an upper pixel electrode on a bank layer of the opening.
The invention according to claim 8 is characterized in that the step of forming the semiconductor includes a step of applying a semiconductor solution to the opening and a step of drying the semiconductor solution. This is a method of manufacturing an effect transistor.
The invention according to claim 9 is the method for manufacturing a field-effect transistor according to claim 7 or 8, further comprising a step of forming a sealing layer on the semiconductor.
The invention according to claim 10 is an image display device using the field effect transistor according to any one of claims 1 to 6.
The invention according to claim 11 is an image display device characterized in that a liquid crystal display element or electronic paper is used for the display section of the image display device according to claim 10.

  The field effect transistor according to the present invention can prevent the semiconductor layer from being formed on the lower electrode by covering the lower pixel electrode with the bank layer, and can be stabilized by electrostatically connecting the upper pixel electrode. The applied voltage can be applied. Further, since the semiconductor layer only needs to be formed in the opening of the bank layer, the semiconductor layer can be formed by a simple process, and the productivity is improved.

Hereinafter, embodiments of the present invention will be described in detail.
1, 5 and 7 show some or all of the basic structural examples of the field effect transistor according to the present invention. Further, FIGS. 2, 4 and 6 show conventional examples. A broken line in FIGS. 1 to 3 represents an outline of one pixel when a field effect transistor is used in an image display device. FIGS. 1 to 3 are all examples in which the positional relationship among the source electrode, the drain electrode, the lower pixel electrode, and the bank layer is captured from the upper part of the pixel. A thick solid line in FIGS. 1 and 2 is a line showing a position indicating the cross-sectional structure of FIGS. 4 and 5, respectively.

The present invention includes at least a gate electrode, a gate insulating layer, a source electrode, a lower pixel electrode and a drain electrode connected thereto, a semiconductor formed between the source electrode and the drain electrode, and a semiconductor electrode disposed so as to surround the semiconductor electrode. A plurality of bank layers, an interlayer insulating layer having an opening on at least the lower pixel electrode, and an upper pixel electrode electrostatically connected to the lower pixel electrode through the bank layer. It is a field effect transistor.
In addition, the present invention includes at least a step of forming a gate electrode on a substrate, a step of forming a gate insulating layer, a step of forming a source electrode, a drain electrode, and a lower pixel electrode, a source electrode, a drain electrode, and them. Forming a bank layer leaving a sandwiched portion; applying a semiconductor solution to the bank layer non-forming portion and drying; or forming a semiconductor by vacuum-depositing a semiconductor; and forming a semiconductor layer on the lower pixel electrode A method for manufacturing a field effect transistor, comprising: forming an interlayer insulating film having an opening; and forming an upper pixel electrode on a bank layer of the opening.

  As the insulating substrate 10 of the present invention, any material can be used as long as the surface is insulative, sheet-like, and the surface is flat. For example, soda lime glass, quartz glass, polyethylene terephthalate (PET), polyethylene naphthalate ( PEN), cycloolefin polymer, polyimide (PI), polyethersulfone (PES), polymethyl methacrylate (PMMA), polycarbonate (PC), polyallylate and the like can be used. In addition, even a conductive or semiconductive substrate such as a stainless steel sheet, aluminum foil, copper foil, or silicon wafer can be coated or laminated with an insulating material such as a polymer material or a metal oxide on the surface. It can be used as an insulating substrate. Further, the above insulating substrate may be provided with a surface treatment layer such as an easy adhesion layer on the surface, or may be subjected to a surface treatment such as corona treatment, plasma treatment, UV / ozone treatment.

  Examples of the gate electrode 21 and the source electrode 41, the drain electrode 42, the lower pixel electrode 43, and the upper pixel electrode 90 of the present invention include metals such as Al, Cr, Mo, Cu, Au, Pt, Pd, Fe, Mn, and Ag. Can be formed using a known method such as photolithography after the film is formed by a method such as PVD, CVD, or plating. In addition, known transparent conductive materials such as indium / tin oxide (ITO) fluorine doped tin oxide (FTO), aluminum doped zinc oxide (AZO), gallium doped zinc oxide (GZO), PEDOT: PSS, polyaniline, polythiophene A known organic conductive material or the like can also be used. However, when these have a relatively high wiring resistance, it is more preferable to reduce the resistance by using a metal bus electrode. In addition, after processing the above metals, transparent oxides, conductive materials such as organic conductive polymers or their precursors into solutions, pastes, nanoparticle dispersions, etc., they are coated by a printing method, dried, It can also be formed by baking, photocuring or aging. The printing method used is not particularly limited, but it is better to use a patternable printing method such as letterpress printing, intaglio printing, planographic printing, reverse offset printing, screen printing, ink jet, thermal transfer printing, dispenser, etc. Simplification of the process, cost reduction, and high speed can be achieved, which is more preferable. Further, a spin coating, a die coating, a micro gravure coating, a dip coating, and the like may be combined with a patterning method such as photolithography. Further, a combination of the above printing methods may be used.

  When the field effect transistor of the present invention is used in an image display device such as electronic paper or a liquid crystal display device, the capacitor electrode 22 is usually disposed under the lower pixel electrode via an insulating layer. As a result, a storage capacitor is provided in the lower pixel electrode to stabilize the voltage. The capacitor electrode can be formed in the same manner as the gate electrode and the like.

  As the gate insulating layer 30 of the present invention, polyvinylphenol (PVP), polystyrene (PS), polymethyl methacrylate (PMMA), polyvinyl alcohol (PVA), polyvinyl chloride (PVC), polyvinylidene fluoride (PVDF), polytetra Fluoroethylene (PTFE), polyimide (PI), epoxy resin, polydimethylsiloxane (PDMS), organic polymer compounds such as butadiene rubber, or a mixture thereof, or alkoxysilane group, vinyl group, acrylic ester, epoxy group, etc. Mixtures with compounds having reactive substituents can be used, and furthermore, silicon oxide, titanium oxide, tantalum oxide, aluminum oxide, niobium oxide, zirconium oxide, copper oxide, nickel oxide, indium oxide, hafnium oxide, etc. Oxidation Alternatively, these composite oxides, oxide mixtures, oxynitrides, and the like can also be used, but are not limited to these as long as they have sufficient insulating properties and can form a thin film having a thickness of 1 μm or less. Absent. Further, these may be mixed or laminated. As a method for forming these organic polymer compounds, existing wet coating methods such as micro gravure coating, dip coating, screen coating, die coating, and spin coating can be used. In addition, as a method for forming inorganic oxides, oxynitrides, etc., vacuum film formation methods such as vapor deposition, sputtering, ion plating, and CVD can be used, and any gas was used during film formation. Plasma, ion gun, radical gun, etc. may be used in combination. In addition, precursors corresponding to the respective metal oxides, specifically metal halides such as chlorides and bromides, metal alkoxides, metal hydroxides, and the like, such as acids such as hydrochloric acid, sulfuric acid and nitric acid in alcohol and water, You may form by making it react with bases, such as sodium hydroxide and potassium hydroxide, and hydrolyzing. When such a solution process is used, an existing wet coating method such as micro gravure coating, dip coating, screen coating, die coating, spin coating, or the like can be used. The above gate insulating layer may be subjected to surface treatment such as corona treatment, plasma treatment, UV / ozone treatment, but care must be taken so that the surface roughness due to the treatment does not become rough. The surface of the gate insulating layer is preferably relatively smooth and free from pinholes, protrusions, and undulations.

  A self-assembled monolayer may be formed on the uppermost layer of the gate insulating layer of the present invention. Compounds that form self-assembled monolayers include (mono, di, tri) alkoxysilane groups, (mono, di, tri) chlorosilane groups, phosphonic acid, phosphinic acid, phosphoric acid, phosphorous acid, hypoxia Has functional groups such as phosphoric acid, amino group, halide group, carboxylic acid, hydroxyl group, thiol group, disulfide group, azide group, acetylene group, vinyl group, nitro group, cyano group, alkyl group, phenyl in the molecule And those having a substituent having 2 or more carbon atoms, including at least one of a group, a phenoxy group, a thiophene ring, a pyrrole ring, a pyridine ring, a fluorene ring, an ether, an ethylene group, and an acetylene group.

  The main skeleton is preferably not branched, for example, a linear normal alkyl (n-alkyl) group, a ter-phenyl group in which three phenyl groups are arranged in series, or both sides of the phenyl group in the para position. A structure in which an n-alkyl group is arranged in the structure is preferable. Moreover, an ether bond may be included in the alkyl chain, and a carbon-carbon double bond or a triple bond may be included. Self-assembled monolayers form a monolayer on a substrate by forming a bond when one reactive substituent of the molecule interacts or reacts with a reactive site on the corresponding substrate surface. To form. When the molecules are packed more densely, the surface of the self-assembled monolayer gives a smoother and lower surface energy surface, so the main skeleton of the molecule is linear and the molecular length is uniform. It is desirable.

The compound forming the self-assembled monolayer is formed on the corresponding substrate surface by the following reaction. For example, a substance having a trichlorosilane group reacts with a silanol group on the surface of a silicon substrate and is adsorbed by a chemical bond (the following reference 1), and phosphonic acid, phosphinic acid and the like react with a hydroxyl group on an alumina substrate, It is well known that it adsorbs by chemical bonds (Reference Document 2 below). The self-assembled monolayer film is formed by using a method in which the compound forming the self-assembled monomolecule is deposited on a corresponding substrate under vacuum, a method in which the substrate is immersed in a solution of the compound, a Langmuir-Blodgett method, or the like. However, the present invention is not limited to this. However, for example, it is more preferable to use the methods described in the following References 3 and 4 as a method for obtaining only a monomolecular film with a denser and more reliable compound.
[Reference 1] J. Org. Am. Chem. Soc. 102, 92 (1980)
[Reference 2] J. Org. Phys. Chem. B 107, 5877 (2003)
[Reference 3] Langmuir 19, 1159 (2003)
[Reference 4] J. Org. Phys. Chem. B 110, 21101 (2006)

  As the bank layer 50 of the present invention, polyvinyl phenol (PVP), polystyrene (PS), polymethyl methacrylate (PMMA), polyvinyl alcohol (PVA), polyvinyl chloride (PVC), polyvinylidene fluoride (PVDF), polytetrafluoro Reactions such as organic polymer compounds such as ethylene (PTFE), polyimide (PI), epoxy resin, polydimethylsiloxane (PDMS), butadiene rubber, or mixtures thereof, or alkoxysilane groups, vinyl groups, acrylate esters, epoxy groups, etc. A mixture with a compound having a functional substituent can be used, and furthermore, oxidation of silicon oxide, titanium oxide, tantalum oxide, aluminum oxide, niobium oxide, zirconium oxide, copper oxide, nickel oxide, indium oxide, hafnium oxide, etc. object, Rui it is possible to use an insulating material such as a composite oxide thereof, or oxide mixtures, oxynitride. In order to impart ink repellency to these insulating materials, a compound having an alkyl chain and a reactive substituent or a fluorine-containing compound may be added. Examples of the compound to be added include octyltrimethoxysilane, hexyltrimethoxysilane, octadecyltrichlorosilane, tridecafluoro-1,1,2,2-tetrahydrooctyltrichlorosilane, dodecyldimethylchlorosilane, hexamethylenedisilazane, Examples include octadecylphosphonic acid, octadecene, hexanoic acid, pentafluorothiophenol, and 2-perfluorooctylethanol. Furthermore, a fluorine-based polymer or a polysiloxane compound may be used, and more specifically, it is more preferable to use CYTOP (manufactured by Asahi Glass Co., Ltd.) which is a fluorine-based resin.

  As shown in FIG. 1, the bank layer of the present invention has an opening so as to surround the source electrode, the drain electrode, and the channel portion sandwiched between them in one pixel, and covers the entire lower pixel electrode. It has the shape which does not have an opening part, It is characterized by the above-mentioned. In such a structure, the upper pixel electrode and the lower pixel electrode are structurally separated as shown in FIG. 7, but when a potential is applied to the lower electrode, the dielectric layer is interposed through the bank layer. A voltage can be electrostatically applied to the upper pixel electrode. By such an action, it becomes possible to drive the electronic paper and the liquid crystal display element.

  This will be described in more detail with reference to FIG. FIG. 8 is a circuit diagram in the case where electronic paper using an electrophoretic microcapsule front plate (Japanese Patent No. 3833266) as a display device is bonded to the field effect transistor of the present invention. In FIG. 8, Vg is the gate voltage, Vs is the source voltage, Vd is the drain voltage, Vp is the pixel applied voltage, Cb is the bank layer capacitance, Cs is the storage capacitance, Cp is the capacitance of the microcapsule front plate, and Rp is before the microcapsule. It is the resistance of the face plate. At this time, if Vd applied via the transistor and the potential Vp obtained via the bank layer have substantially the same value, the display device (front plate) can be operated. Vp is calculated by Equation 1.

Vp = {Rp // (1 / jωCp) / Rp // (1 / jωCp) + (1 / jωCb)} Vd
= {JωCbRp / (jωCbRp + jωCpRp + 1)} Vd (Formula 1)

In Equation 1, // represents the composition of parallel connections.
From Expression 1, when Cb >> Cp and | ωCb | >> 1 / Rp, Vp≈Vd. Usually, Cb is two orders of magnitude or more larger than Cp, and | ωCb | is two orders of magnitude or more larger than 1 / Rp. However, when designing a circuit of a pixel, Must be selected.

  Since the bank layer of the present invention has a structure as shown in FIG. 1, the semiconductor can be formed only in the opening of the bank layer, that is, the channel portion without using a special patterning method when depositing the semiconductor. it can. For example, it can be realized by applying a semiconductor solution and drying it. In that case, the bank layer preferably has ink repellency, and a material having a low surface energy, that is, an organic material containing fluorine or a long-chain alkyl group is used. It can be obtained conspicuously when using the material it has. The method of forming a semiconductor only at the opening of such a bank layer is not only a method of applying a semiconductor from a solution, but also controlling a substrate temperature, a film formation rate, a degree of vacuum, etc. when using a vacuum film formation method. Can be obtained. When an opening is provided on the lower pixel electrode of the bank layer as in the conventional example (FIG. 2), the semiconductor is deposited between the upper pixel electrode and the lower pixel electrode unless strict patterning is performed. Become. When such a problem occurs, a process for removing the semiconductor on the lower pixel electrode after forming the sealing layer must be provided.

 The thickness of the bank layer is desirably 50 nm to 1 μm. If it is less than 50 nm, it is difficult to form a uniform film on the entire surface.

  The bank layer of the present invention is formed by forming a resist on the channel portion, and then using an existing wet coating method such as microgravure coating, dip coating, screen coating, die coating, spin coating, flexographic printing, or vapor deposition, sputtering, ion It can be formed by forming a bank layer using a vacuum film formation method such as plating or CVD, and then peeling off the resist. Alternatively, a method of directly producing a shape as shown in FIG. 1 using an existing printing method such as offset gravure printing, reverse offset printing, screen coating, flexographic printing, or the like may be used.

  Examples of the semiconductor 60 of the present invention include π-conjugated organic polymers exhibiting semiconductivity, such as polypyrroles, polythiophenes, polyanilines, polyallylamines, fluorenes, polycarbazoles, polyindoles, poly (p-phenylene vinylene). ) And other low-molecular substances having a π-conjugated system, for example, polycyclic aromatic derivatives such as pentacene, phthalocyanine derivatives, perylene derivatives, tetrathiafulvalene derivatives, tetracyanoquinodimethane derivatives, fullerenes, carbon nanotubes However, this is not a limitation.

In addition, inorganic semiconductors such as amorphous silicon, germanium, cadmium telluride, zinc selenide, gallium nitride, and aluminum nitride, and oxide semiconductors such as indium gallium zinc oxide (IGZO), zinc oxide, tin oxide, and indium oxide are used. Also good.

As a method for forming a semiconductor of the present invention, a vacuum deposition method, a CVD method, a sputtering method, a printing method using a solution, or the like can be used, but a semiconductor soluble in a solvent is used from the viewpoint of productivity and cost reduction. It is more preferable to use the method of coating using. When using the printing method, there is no particular limitation, but letterpress printing, intaglio printing, planographic printing, reverse offset printing, screen printing method, ink jet, thermal transfer printing, dispenser, spin coating, die coating, micro gravure coating, dip A coat or the like can be used, and the above printing methods may be used in combination.

  In the case where the interlayer insulating film may deteriorate the semiconductor, a sealing layer may be provided over the semiconductor. If there is no such fear, the sealing layer may not be provided. As the sealing layer 70 of the present invention, it is preferable to use a material that does not easily interact electrically and chemically with a semiconductor, an electrode, or the like. For example, polyvinylphenol (PVP), polystyrene (PS), polymethyl methacrylate ( PMMA), polyvinyl alcohol (PVA), polyvinyl chloride (PVC), polyvinylidene fluoride (PVDF), polytetrafluoroethylene (PTFE), polyimide (PI), epoxy resin, polydimethylsiloxane (PDMS), butadiene rubber, benzo Cyclobutene resins, phenol resins, polymer alloys and copolymers of these resins can be used, and furthermore, condensed fluorine-containing polymers such as fluorine-containing acrylic resins and fluorine-containing polyimides, fluorine-containing ether polymers, fluorine-containing resins Cyclic ether polymer, etc. You can have, they may have such trifluoromethane substituent. Further, a visible light curable resin, a UV curable resin, an EB curable resin, or a thermosetting resin curable by heat can be used. In addition, oxides such as silicon oxide, titanium oxide, tantalum oxide, aluminum oxide, niobium oxide, zirconium oxide, copper oxide, nickel oxide, indium oxide, and hafnium oxide, or a composite oxide or oxide mixture thereof, oxynitride These metal nitrides and carbides can also be used.

  When applying a polymer or resin, a solvent in which the material to be used is appropriately selected, for example, letterpress printing, reverse offset printing, ink jet printing, screen printing, spray coating, spin coating, die coating, roll coating. , Reverse gravure coating, bar coating, dip coating, blade coating, lamination, and other printing methods.

  As a method for forming inorganic oxides, oxynitrides, etc., vacuum film formation methods such as vapor deposition, sputtering, ion plating, and CVD can be used. An ion gun or a radical gun may be used in combination.

  As the interlayer insulating layer 80 of the present invention, a relatively thick film of 1 μm to 10 μm can be formed, patterning is easy, and an insulating material having a low dielectric constant is preferable. Epoxy, acrylic resin, polyimide, polyvinyl A resin such as phenol, polyvinyl alcohol, or a fluorine-based polymer can be formed by a photolithography method or a screen printing method.

  In addition, an image display device such as a liquid crystal display device or electronic paper can be obtained by using the field effect transistor of the present invention formed as described above. Specifically, an image display element having an active matrix TFT array using a field effect transistor as a back plate, and forming a display element such as a liquid crystal display device or electronic paper on a display portion on the back plate, An image display device can be obtained.

  Hereinafter, the present invention will be described in detail by way of specific examples. However, these examples are for the purpose of explanation, and the present invention is not limited thereto.

[Example 1]
A field effect transistor having a structure similar to that shown in FIG. 7 was formed in an 80 × 60 array. 0.7 mm thick glass was used as the insulating substrate 10, and aluminum was formed as the gate electrode 21 and the capacitor electrode 22 by 50 nm by vacuum deposition, and then patterned by photolithography and etching. Subsequently, 300 nm of SiON is laminated as the insulating layer 30 by sputtering, gold is formed to a thickness of 40 nm by vacuum deposition, and patterning is performed in the same manner as the gate electrode and the capacitor electrode, whereby the source electrode 41 and the drain electrode 42 are formed. And the electrode pattern used as the lower pixel electrode 43 was formed. At this time, in order to increase the adhesion between the gold and the insulating layer, chromium is laminated to about 3 nm before gold is deposited.

  Next, a resist is formed on the channel portion by photolithography, Cytop manufactured by Asahi Glass Co., Ltd. is spin-coated at a film thickness of 100 nm, heated at 120 ° C. for 1 minute, and then the resist is peeled off to open the channel portion. A bank layer 50 having a portion was obtained. Further, P3HT (poly (3-hexylthiophene)) was applied as a semiconductor 60 by spin coating from a chloroform solution and dried at 50 ° C. to form a channel portion. After applying Cytop as the sealing layer 70 by screen printing, drying at 90 ° C., applying negative acrylic resin as the interlayer insulating layer 80, annealing at 150 ° C., and opening on the lower pixel electrode by photolithography Was made. Finally, after patterning the resist, aluminum was deposited as the upper pixel electrode 90 and the resist was peeled off to form an array of field effect transistors having the upper pixel electrode.

Using one of the field-effect transistors obtained as described above, the gate electrode, the source electrode, and the drain electrode were connected at three terminals, and the transfer characteristics were measured at a gate voltage of −20V to 40V and a source voltage of −40V. The mobility was 0.01 cm ² / Vs, on / off was 105, and the threshold voltage was −5V. Further, the obtained array was laminated with an electrophoretic microcapsule and a front plate having a transparent electrode, and when the display was driven, a good display was obtained over the entire array.

[Comparative Example 1]
A field effect transistor having a structure similar to that shown in FIG. 6 was formed in an 80 × 60 array. On the 0.7 mm thick glass as the insulating substrate 10, an electrode pattern to be the gate electrode 21, the capacitor electrode 22, the insulating layer 30, the source electrode 41, the drain electrode 42, and the lower pixel electrode 43 is formed as in the first embodiment. did.

  Next, a resist is formed on the channel portion and the lower pixel electrode by photolithography, Cytop manufactured by Asahi Glass Co., Ltd. is spin-coated at a film thickness of 100 nm, heated at 120 ° C. for 1 minute, and then the resist is peeled off. A bank layer 50 having openings on the channel portion and the lower pixel electrode was obtained. Further, in the same manner as in Example 1, the semiconductor 60 was formed by spin coating and dried at 50 ° C., and after forming the sealing layer 70, it was immersed in a chloroform solution and subjected to ultrasonic cleaning for 5 minutes. The semiconductor deposited in the bank opening on the pixel electrode was removed. Further, by forming the interlayer insulating layer 80 and the upper pixel electrode 90 in the same manner as in Example 1, an array of field effect transistors having the upper pixel electrode was obtained.

Using one of the field-effect transistors obtained as described above, the gate electrode, the source electrode, and the drain electrode were connected at three terminals, and the transfer characteristics were measured at a gate voltage of −20V to 40V and a source voltage of −40V. The mobility was 0.01 cm 2 / Vs, on / off was 105, and the threshold voltage was −7 V. Further, the obtained array was laminated with an electrophoretic microcapsule and a front plate having a transparent electrode, and when the display was driven, a good display was obtained over the entire array.

  Although Example 1 was a simpler process compared to Comparative Example 1, a field effect transistor having a performance equal to or higher than that of the conventional method could be produced.

[Example 2]
A field effect transistor having a structure similar to that shown in FIG. 7 was formed in an 80 × 60 array. Polyethylene naphthalate (PEN) having a thickness of 200 μm was used as the insulating substrate 10, and aluminum was formed as a gate electrode 21 and a capacitor electrode 22 by 50 nm by vacuum deposition, and then patterned by photolithography and etching. Subsequently, polyvinylphenol (PVP) is laminated as an insulating layer 30 by spin-coating a cyclohexanone solution to a thickness of 300 nm, and gold is further formed to a thickness of 40 nm by a vacuum deposition method, followed by patterning in the same manner as the gate electrode and the capacitor electrode. Thus, an electrode pattern to be the source electrode 41, the drain electrode 42, and the lower pixel electrode 43 was formed. At this time, in order to increase the adhesion between the gold and the insulating layer, chromium is laminated to about 3 nm before gold is deposited.

  Next, a resist is formed on the channel portion by screen printing, Cytop manufactured by Asahi Glass Co., Ltd. is spin-coated at a film thickness of 100 nm, heated at 120 ° C. for 1 minute, and then the resist is peeled off to open the channel portion. A bank layer 50 having a portion was obtained. Further, pentacene was formed as a semiconductor 60 in the channel portion by vacuum deposition at a substrate temperature of 120 ° C. By forming the sealing layer 70, the interlayer insulating layer 80, and the upper pixel electrode 90 in the same manner as in Example 1, an array of field effect transistors having the upper pixel electrode was obtained.

  Using one of the field-effect transistors obtained as described above, the gate electrode, the source electrode, and the drain electrode were connected at three terminals, and the transfer characteristics were measured at a gate voltage of −20V to 40V and a source voltage of −40V. The mobility was 0.6 cm 2 / Vs, on / off was 106, and the threshold voltage was −7 V. Further, the obtained array was laminated with an electrophoretic microcapsule and a front plate having a transparent electrode, and when the display was driven, a good display was obtained over the entire array.

[Comparative Example 2]
A field effect transistor having a structure similar to that shown in FIG. 6 was formed in an 80 × 60 array. An electrode pattern to be the gate electrode 21, the capacitor electrode 22, the insulating layer 30, the source electrode 41, the drain electrode 42, and the lower pixel electrode 43 was formed on the 200 μm thick glass as the insulating substrate 10 in the same manner as in Example 2. Further, the bank layer 50 was formed in the same manner as in Comparative Example 1.
Further, the semiconductor 60 is formed by vacuum evaporation as in the second embodiment, and the sealing layer 70, the interlayer insulating layer 80, and the upper pixel electrode 90 are formed in the same manner as in the second embodiment, so that the field effect type having the upper pixel electrode is formed. A transistor was obtained.

  Using one of the field-effect transistors obtained as described above, the gate electrode, the source electrode, and the drain electrode are connected at three terminals, and the transfer characteristics are measured at a gate voltage of −20V to 40V and a source voltage of −40V. The mobility was 0.6 cm 2 / Vs, on / off was 106, and the threshold voltage was −8 V. Furthermore, when an electrophoretic microcapsule and a front plate having a transparent electrode were laminated on the obtained array and display driving was performed, only some pixels were displayed well, and most did not operate normally.

  In Comparative Example 2, it is considered that the semiconductor on the lower pixel electrode obstructs the contact between the lower pixel electrode and the upper pixel electrode, resulting in a large resistance.

The present invention is used for a display element such as a liquid crystal display element or electronic paper having an active matrix type TFT array using TFT as a back plate.

It is an example which showed a part of pixel which has a bank layer which has an opening part on the lower pixel electrode in this invention from the upper part. It is an example which showed a part of pixel which has a bank layer without an opening part in the lower pixel electrode in a prior art example from the upper part. FIG. 3 is a diagram showing a source electrode, a drain electrode, and a lower pixel electrode in FIGS. 1 and 2 from above. It is an example of the cross-section of the thick solid line part in FIG. 2 of a prior art example. It is an example of the cross-section of the thick continuous line part in FIG. 1 of the example of this invention. 5 is an example of a cross-sectional structure of one pixel formed up to an upper pixel electrode in FIG. 4 of the conventional example. FIG. 6 is an example of a cross-sectional structure of one pixel formed up to an upper pixel electrode in FIG. It is a circuit diagram when the field effect transistor of the present invention is used for electrophoretic electronic paper.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Insulating substrate 21 Gate electrode 22 Capacitor electrode 30 Gate insulating layer 41 Source electrode 42 Drain electrode 43 Lower pixel electrode 50 Bank layer 60 Semiconductor 70 Sealing layer 80 Interlayer insulating layer 90 Upper pixel electrode

Claims (11)

  A gate electrode; a gate insulating layer formed on the gate electrode; a source electrode; a lower pixel electrode; a drain electrode connected to the lower pixel electrode; and the source electrode and the drain electrode. A semiconductor layer, a bank layer surrounding the semiconductor and covering the lower electrode, an interlayer insulating layer having an opening on at least the lower pixel electrode, and the lower pixel electrode via the bank layer A field effect transistor comprising an upper pixel electrode that is electrostatically connected. 2. The field effect transistor according to claim 1, wherein the semiconductor is an organic semiconductor.   The field effect transistor according to claim 1, wherein the bank layer has ink repellency.   4. The field effect transistor according to claim 3, wherein the bank layer contains fluorine.   5. The field effect transistor according to claim 1, wherein the bank layer has a thickness of 50 nm to 1 μm.   The field effect transistor according to claim 1, further comprising a sealing layer between the semiconductor and the interlayer insulating layer.   At least a step of forming a gate electrode on the substrate, a step of forming a gate insulating layer, a step of forming a source electrode, a drain electrode, and a lower pixel electrode, and opening the source electrode, the drain electrode, and a portion sandwiched between them Forming a bank layer as a part, applying a semiconductor solution to the opening and drying, or forming a semiconductor by vacuum-depositing the semiconductor, and an interlayer having an opening on the lower pixel electrode A method of manufacturing a field effect transistor, comprising: forming an insulating film; and forming an upper pixel electrode on the bank layer of the opening.   8. The method of manufacturing a field effect transistor according to claim 7, wherein the step of forming the semiconductor includes a step of applying a semiconductor solution to the opening and a step of drying the semiconductor solution.   9. The method of manufacturing a field effect transistor according to claim 7, further comprising a step of forming a sealing layer on the semiconductor.   An image display device using the field effect transistor according to claim 1.   An image display device, wherein a liquid crystal display element or electronic paper is used for the display unit of the image display device according to claim 10.

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