JP2006165234A - Field-effect transistor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a field-effect transistor achieving an element having an excellent ON/OFF ratio even when a source, a drain, a gate electrode, an organic semiconductor layer or the like is formed by a simple method such as a printing method, an ink jet method or the like when the source, the drain, the gate electrode, the organic semiconductor layer or the like is formed and using an organic material having; a large operating current and having the little dispersion of characteristics among the elements by achieving a short-sized channel. <P>SOLUTION: In a field-effect transistor element; the transistor element is composed of at least a supporting substrate, a source electrode, a drain electrode, an active layer, an insulating layer, and the gate electrode. The source electrode and the drain electrode are formed in the same plane, a width between sections, in which partition walls are formed while being adjacent to the source electrode and the drain electrode is connected electrically by at least the active layer, and an organic matter is used as the active layer. In such a transistor element, the heights of the partition walls differ in a section between the source and the drain and at other sections. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention is a field effect using an organic material as at least a semiconductor material used in a flexible, sensor device such as a switching element for pixel display such as a liquid crystal display, an organic EL display, an electrophoretic display, a plastic IC card, an information tag, and a biosensor. More particularly, the present invention relates to a thin-film field effect transistor having a novel structure with a large operating current and a large ON / OFF ratio, and a method for manufacturing the same.

  Thin film transistors (TFTs) are widely used as driving switching elements for active matrix liquid crystal displays and organic EL displays. A TFT is an example of a field effect transistor (FET), and is a FET in which a metal-insulator-semiconductor having a semiconductor layer formed as a thin film on a substrate is combined.

Currently, most TFTs are manufactured using amorphous silicon or polysilicon as a semiconductor layer. Amorphous silicon is an inexpensive alternative to crystalline silicon and is provided for use in large area applications with reduced transistor costs. Amorphous silicon has a mobility of about 0.1 to ¹ cm ² / V · sec, and polysilicon has a mobility of about 1 to 10 cm ² / V · sec. On the other hand, since it is about 1 / 10,000 to 1/1000, their application is limited to a relatively low speed. Polysilicon is formed by recrystallization annealing such as excimer laser irradiation on amorphous silicon. Film formation of amorphous silicon on a substrate is performed at a low temperature and is therefore cheaper than crystalline silicon. However, film formation of amorphous silicon is expensive because it requires plasma chemical vapor deposition. Polysilicon film formation requires an annealing process such as excimer laser irradiation as described above, which further increases the cost.

  In recent years, there are expectations for the application of flexible and sensor devices such as sheet displays, electronic paper, plastic IC cards, information tags, biosensors, etc. that take advantage of the various flexibility of organic materials such as mechanical, diverse, and manufacturing processes. Gathered.

  However, most organic semiconductor materials have lower electrical conductivity and carrier mobility than inorganic semiconductor materials, and improvement of operating characteristics has been a challenge for practical use of organic semiconductor thin film transistors.

FIG. 5 is a cross-sectional view of a conventional thin film transistor. In the invention described in Patent Document 1 shown in FIG. 5, a pentacene organic material is formed on a highly doped silicon substrate to operate a TFT, and the movement is 0.52 cm ² / V · sec. The degree is realized. However, since a thin film formed of pentacene requires vacuum film formation to form the thin film, the adhesion to the substrate is weak and therefore, it is fragile. Further, since it is necessary to use an expensive silicon substrate, it is difficult to form a thin film transistor at low cost.

On the other hand, according to Non-Patent Document 1, CJ Drury et al. Used polyimide as a substrate, PTV (polythienylene vinylene) as a semiconductor material, PVP (polyvinylphenol) as an insulating material, and as an electrode material. By using doped polyaniline and using photochemical patterning, a TFT of an all organic material is manufactured to obtain a TFT having a charge mobility of 3 × 10 ⁻⁴ cm ² / V · sec. However, the charge mobility of this TFT is still low, and there is much room for improvement.

  The electrical characteristics of TFTs using organic semiconductors can be almost explained by the theory of transistors using inorganic semiconductors. In the region where the drain voltage is low, the relational expression between the drain voltage (Vd) and the drain current (Id) of the organic TFT is expressed by the following formula. (Linear region)

ここで、Ｗはゲートのチャネル幅、Ｌはチャネル長、Ｃｉはゲート絶縁膜の単位面積あたりの静電容量、μはキャリア移動度、Ｖｔはゲート閾値電圧である。

Here, W is the channel width of the gate, L is the channel length, Ci is the capacitance per unit area of the gate insulating film, μ is the carrier mobility, and Vt is the gate threshold voltage.

  When Vd increases, Id is saturated and becomes a constant value due to the pinch-off of the channel. Id at this time is expressed by the following equation. (Saturated region)

有機半導体を用いたＴＦＴのキャリア移動度は、ゲート電圧によりチャネルに蓄積される電荷量に依存し、一般にＶｇとともに増加して飽和する関係が知られている。また、ＴＦＴの動作速度や電流駆動能力を表す遮断周波数Ｔｆと相互コンダクタンスｇｍは式３および式４により求められる。

The carrier mobility of a TFT using an organic semiconductor depends on the amount of charge accumulated in the channel due to the gate voltage, and is generally known to increase with Vg and saturate. Further, the cutoff frequency Tf and the mutual conductance gm representing the operation speed and current driving capability of the TFT are obtained by Expression 3 and Expression 4.

但し、飽和領域ではＶｄ＝Ｖｇ−Ｖｔ

However, in the saturation region, Vd = Vg−Vt

但し、飽和領域ではＶｄ＝Ｖｇ−Ｖｔ
これらの式から有機半導体を用いたＴＦＴを作成する上で、（１）有機半導体のキャリア移動度μを大きくする。（２）チャネル長Ｌを小さく、チャネル幅Ｗを大きくする。（３）ゲート絶縁膜の誘電率を大きくする。ことが重要である。このほか、有機半導体を用いたＴＦＴに求められる性能として、ドレイン電流のＯＮ/ＯＦＦ比が大きい、閾値電圧が低いなどがある。
特開平１０−２７０７１２号公報 APPLIED PHISICS LETTERS Vol.73, No. 1 (1998) 108―110 Nature,vol.401(1999)685-688

However, in the saturation region, Vd = Vg−Vt
In creating a TFT using an organic semiconductor from these equations, (1) the carrier mobility μ of the organic semiconductor is increased. (2) The channel length L is reduced and the channel width W is increased. (3) Increasing the dielectric constant of the gate insulating film. This is very important. In addition, the performance required for a TFT using an organic semiconductor includes a large drain current ON / OFF ratio and a low threshold voltage.
JP-A-10-270712 APPLIED PHISICS LETTERS Vol.73, No. 1 (1998) 108-110 Nature, vol. 401 (1999) 685-688

  Examples of the organic semiconductor material include the aforementioned low molecular weight compounds (for example, pentacene, metal phthalocyanine), short chain oligomers (for example, n-thiophene having n = 3 to 8), long chain polymers (for example, polythiophene, polyphenylene vinylene), and the like. is there.

High molecular weight materials are attracting attention because they can be easily formed into a film by a solution process, so that the cost can be reduced and the area can be increased. In addition, by using an inkjet method, an integrated circuit can be formed by directly drawing a fine pattern on a substrate. However, the high molecular weight material has a problem that the carrier mobility is small because disorder is larger than that of the low molecular weight material. The hole mobility of polyfluorene is 0.02 cm ² / Vs, and the carrier mobility of a general polymer material is about two orders of magnitude smaller than that of a low molecule. However, in Non-Patent Document 2, it is reported by H. Sirringhaus et al. That stereoregular polyhexylthiophene exhibits a large hole mobility of 0.1 cm ² / Vs.

  Since this material has a head-to-tail arrangement of side chains, it is considered that π-electron orbital overlap is formed by the overlapping of the thiophene rings of the main chain, thereby indicating high carrier mobility. Yes. New polymer materials have been actively developed because higher carrier mobility can be realized by providing intermolecular regularity in polymer materials as well.

  However, when spin coating, dipping coating, an ink jet method, or the like is used, the film thickness is generally thicker than when a vacuum process such as vapor deposition is used. In addition, the variation in the film thickness also increases. In particular, the film thickness of the source and drain electrodes has an effect on the formation of the channel region between the source and drain, and thus there is a problem that the characteristic variation between elements increases.

  Although a fine pattern can be formed by a simple method by direct patterning using an inkjet method, the resolution at that time is about 30 μm in line and space, which is insufficient for miniaturization of the channel length.

  The present invention has been made to solve this problem, and by using a simple and inexpensive manufacturing method such as a printing method or an inkjet method, a wiring material or an organic semiconductor material is patterned, and the organic semiconductor material has low mobility. The present invention provides a field effect transistor having a novel structure with a large operating current and a large ON / OFF ratio.

  That is, the first aspect of the present invention is a field effect transistor having at least a support substrate, a source electrode, a drain electrode, a semiconductor layer, an insulating layer, and a gate electrode, and using an organic substance as the semiconductor layer. The electrodes are formed in the same plane, and at least a partition wall having an insulating property is provided adjacent to the source electrode and the drain electrode, and the height of the partition wall is different between the source and the drain and other portions. This is a field effect transistor.

  As a preferred embodiment, in a field effect transistor in which a source electrode and a drain electrode are formed on the same plane on a supporting substrate and a semiconductor layer, an insulating layer, and a gate electrode are provided in that order, a partition wall between the source and drain is formed. The sum of the film thicknesses of the semiconductor layer and the insulating layer is thin due to the difference between the height and the height of the partition wall at other points higher than the partition wall.

  In another preferred embodiment, partition walls having different heights are provided in the same plane on the support substrate on which the gate electrode is disposed, between the source and the drain and in other locations, and the semiconductor layer is disposed above the source and drain electrodes. In the field effect transistor in which is formed, the partition wall is wider than the gate electrode between the source and drain electrodes.

  In the present invention, by changing the height of the partition between the source and the drain from other portions, it becomes possible to form the source and the drain more accurately at a short distance. Can be formed stably.

  Moreover, in the partition walls adjacent to the source electrode and the drain electrode, the partition walls having different heights are made of two types of resin compositions, so that the partition walls having different heights can be formed with high accuracy. .

  According to a second aspect of the present invention, there is provided a method of manufacturing a field effect transistor, comprising a step of transferring the partition from a second substrate having a partition shape formed in advance.

  The third invention of the present invention is characterized in that the conductive liquid material applied between the high partition walls of the partition wall is spontaneously separated by the low partition walls during drying to form a source electrode and a drain electrode. .

  In a more preferred embodiment, the method includes a step of forming the source electrode and the drain electrode by an ink jet method.

  Furthermore, the method further includes a step of forming the semiconductor layer made of the organic material by an inkjet method.

  For this reason, it is possible to provide a field-effect transistor at a low cost because it is a simple method and material can be effectively used by creating a field-effect transistor using an ink-jet method.

  According to the present invention, when a source, a drain, a gate electrode, an organic semiconductor layer, and the like are formed, the OFF current in the organic semiconductor layer can be suppressed even if formed by a simple method such as a printing method or an inkjet method. An element with a good / OFF ratio is realized. In addition, even when the ink jet method is used, by realizing a short channel, it is possible to provide a field effect transistor using an organic material with a large operating current and a small variation in characteristics between elements at low cost. Become.

  The present invention is characterized in that, in a field effect transistor element using an organic substance as a semiconductor layer, the height of the partition is different between the source and the drain and other portions. In particular, the above requirements are effective in a field effect transistor that can be formed by a simple method using an ink jet method. Embodiments of the field effect transistor and the method of manufacturing the same according to the present invention will be described below with reference to the drawings.

  Although the inkjet method is attracting attention as a direct patterning method, even a small droplet of about 4 pl has a diameter of 20 μm, which is large for the channel length of a field effect transistor. It is very difficult to realize a short channel.

  FIG. 1 shows an embodiment of the present invention. Two types of partition walls having different heights are provided, and the source electrode and the drain electrode are separated by a partition wall having a low height. In the portion corresponding to the channel, the height of the electrode is defined by the upper surface of the partition wall, so that the height of the source electrode and the drain electrode is equal. At this time, the sum of the film thicknesses of the semiconductor layer and the insulating layer (FIG. 1b) becomes thinner due to the difference (FIG. 1a) between the height of the partition between the source and drain and the height of the partition walls at other locations higher than the above-mentioned partition. In this way, the OFF current is suppressed and the ON / OFF ratio is increased.

  FIG. 2 shows another embodiment. Two kinds of partition walls having different heights are provided on a substrate having a gate electrode, and source and drain electrodes provided by an inkjet method are provided between the partition walls. The source electrode and the drain electrode are separated by a partition wall having a low height. Since the partition wall is wider than the gate electrode between the source and drain electrodes, insulation between the source electrode, the drain electrode and the gate electrode is maintained. Further, since the electrode is formed along the outer high partition, the distance between the source and the drain becomes wider as the distance from the gate increases, so that the OFF current is suppressed and the ON / OFF ratio is increased.

  FIG. 3 is a schematic view showing an example of a method for producing the field effect transistor of the present invention shown in FIG.

  First, glass, plastic, quartz, silicon, or the like can be used as the support substrate. Examples of the plastic substrate include polycarbonate, mylar, polyimide, polyethylene, (PET), polyethylene naphthalate (PEN), and polyimide, PEN and the like are preferably used from the viewpoint of heat resistance.

  Next, the resin composition used to form the partition includes photosensitive resin or non-photosensitive resin such as epoxy resin, acrylic resin, polyimide resin including polyamideimide, urethane resin, polyester resin, and polyvinyl resin. However, it is preferable to have heat resistance, and from this point, epoxy resin, acrylic resin, and polyimide resin are preferably used.

  As a method for patterning the partition wall, a direct pattern processing method such as an ink jet method, a relief printing method, an intaglio printing method, an offset printing method, a screen printing method, or the like may be used. In order to form barrier ribs having different thicknesses, it is desirable to form a pattern by using a negative photosensitive resin material, and exposing and developing using a predetermined mask after applying the photosensitive resin. At this time, by using two kinds of resin materials as the photosensitive resin material, partition walls having different heights can be accurately formed. In addition, in the partition wall material having a low height, it is desirable to use a material having high liquid repellency with respect to an electrode material formed after the partition wall formation. By the above-described method, it is possible to form the partition wall pattern with high accuracy with respect to the electrode pattern. Therefore, it is possible to maintain good positional accuracy of the source and drain electrodes formed thereafter.

  In the present invention, partition wall formation by nanoimprinting is preferably used. Partitions having different heights are collectively formed using nanoimprinting by pressing a fine concavo-convex pattern on a mold and transferring and molding the fine pattern. The nanoimprint includes a photo-curing type and a thermosetting type, but a thermosetting nano-imprint is preferable from the viewpoint of not selecting a substrate. FIG. 7 shows a schematic diagram of partition formation by nanoimprinting. A fine pattern is transferred and molded by superimposing a Ni mold on which a fine pattern is formed on a substrate coated with a thermosetting resin and pressing it at a temperature above the glass transition point. At this time, since the base layer remains thinly under the uneven pattern on the substrate, the shape of the partition walls having different heights can be obtained by using nanoimprint that forms a highly accurate uneven pattern by removing this by dry etching. Can be formed with high accuracy by a single process.

  Next, a source electrode and a drain electrode are formed. Here, in the present invention, since the ink jet method is suitably used, a liquid material that can be ejected by ink jet is used. Poly 3,4-ethylenedioxythiophene / polystyrene sulfonic acid (PEDOT / PSS) aqueous solution (Baytron P, manufactured by Bayer Co. Ltd.) as the conductive polymer material, and nano-order particles such as silver and gold as the metal paste A liquid obtained by adjusting the viscosity of the ink in which the ink is dispersed is preferable. As the ink jet, a bubble jet (registered trademark) type using an electrothermal transducer as an energy generating element, a piezo jet type using a piezoelectric element, or the like can be used.

  The liquid material is applied as ink using an inkjet head between partition walls provided with gate electrodes at the bottom. (FIG. 3B) At this time, when the inner low partition wall has water repellency, the solvent of the ink material is volatilized by heating and drying thereafter, and the volume of the ink material is reduced. As shown, the ink is separated so as to avoid the partition walls, and the solid content remains so as to show a concave shape, and can be used as a source and drain electrode.

  Even when complete separation cannot be performed, the entire substrate can be separated into the source electrode and the drain electrode by etching the thinnest portion of the conductive ink layer to which the source and drain electrodes are electrically bonded, by dry etching or the like. it can. In addition, surface treatment may be performed to impart liquid repellency to the partition walls in order to correct ink landing before applying the ink material between the partition walls by an inkjet method. As the surface treatment, a liquid repellent material may be applied to the partition wall, or plasma treatment may be performed using a fluorine-based gas.

  Further, a semiconductor layer is formed. Organic semiconductor layers include low molecular organic materials such as naphthalene, anthracene, tetracene, pentacene, hexacene, and polyacetylene, which is a π-conjugated polymer, polyparaphenylene, polythiophene, polypyrrole, polyaniline, polythienylene vinylene, polyparaffin. Examples include phenylene vinylene, polypyridazine, polynaphthylene, polyazulene, and polyisothianaphthene. Moreover, what introduce | transduced a suitable substituent into these and an oligomer body may be sufficient. Furthermore, a dopant may be included in these π-conjugated polymers. Further, a π-conjugated polymer is dispersed in the polymer binder. Alternatively, a structure such as a polymer having a π-conjugated polymer in the side chain is also possible.

  Plating, vapor deposition, sputtering, CVD method, plasma CVD method, spin coating, dipping, letterpress printing method, intaglio printing method, offset printing method, screen printing method and the like can be appropriately used for film formation of these semiconductor materials. In particular, the ink jet method is preferably used from the viewpoint that necessary materials can be applied to necessary portions.

  Subsequently, an insulating layer is formed. As an insulating layer of the gate electrode, as an inorganic insulating layer, silicon dioxide, barium strontium titanate, barium zirconate titanate, lead zirconate titanate, lead lanthanum titanate, strontium titanate, barium titanate, barium magnesium fluoride, Examples include strontium titanate, bismuth titanate, strontium bismuth titanate, tantalum pentoxide, strontium bismuth tantalate, bismuth tantalate niobate, titanium dioxide, and yttrium trioxide. These may be combined or stacked. good. In addition, as organic insulating materials, polyethylene, polyimide, polyvinyl carbazole, polyvinyl butyral, polyvinyl phenol, cyanoethyl pullulan, polyester, polytetrafluoroethylene, tetrafluoroethylene-hexafluoroethylene copolymer, polyvinyl chloride, polypropylene, polybutadiene, Examples thereof include organic insulating polymers such as cellulose acetate, polyphenylene oxide, polyphenylene sulfide, phenol resin, epoxy resin, and polystyrene. These insulating materials may be used alone or in combination of two or more.

  Finally, a gate electrode is formed. A field effect transistor element is completed by providing an electrode material on the insulating layer between the source electrode and the drain electrode described above.

  The gate electrode material is not particularly limited as long as it has conductivity. Platinum, gold, silver, nickel, chromium, copper, iron, tin, antimony, lead, tantalum, indium, aluminum, zinc, magnesium, and alloys thereof And conductive metal oxides such as indium and tin oxide, carbon paste, silver paste, gold paste, or inorganic and organic semiconductors whose conductivity has been improved by doping, such as polysilicon, amorphous silicon, germanium, graphite, Examples include polyacetylene, polyparaphenylene, polythiophene, polypyrrole, polyaniline, polythienylene vinylene, polyparaphenylene vinylene, polypyridazine, polynaphthylene, polyazulene, and polyisothianaphthene.

  The method for forming the gate electrode is not particularly limited, and for example, a conventional method such as plating, vapor deposition, sputtering, CVD, plasma CVD, spin coating, or dipping can be appropriately selected.

  As a pattern processing method, photolithography using positive resist or negative resist, masking, etching or the like can be appropriately selected. In addition, pattern processing can be performed directly at the same time as film formation. An inkjet method, a relief printing method, an intaglio printing method, an offset printing method, a screen printing method, or the like can be used as appropriate.

  FIG. 4 shows a method for manufacturing a field effect transistor in which a gate electrode is provided below a source-drain electrode. First, a gate electrode is formed on a substrate using a material suitable for the gate electrode described above. Next, a partition is formed. At this time, the partition on the gate electrode is formed wider than the gate electrode, and the gate electrode, the source electrode, and the drain electrode must be electrically insulated.

  Next, a source-drain electrode is formed, and an inkjet method is also preferably used here. Finally, the above-described organic semiconductor material is applied to complete the field effect transistor. At this time, the organic semiconductor material may be applied to the entire surface by spin coating or the like, or may be formed only between the source and drain by an inkjet method. Since the gate is provided below the source-drain electrode, the thickness of the organic semiconductor layer provided at this time only needs to be larger than the thickness of the channel, so that accuracy is not so required.

  With the manufacturing method as described above, even in a field effect transistor using an organic material, a short channel can be realized and an element with little variation between elements can be formed.

  Hereinafter, the present invention will be described more specifically with reference to examples. The field effect transistor shown in FIG. 1 is produced. A “CT-2000L resist” made by Fuji Film Olin, which serves as a partition wall, is applied onto a glass substrate by spin coating to a thickness of 2 μm, and exposure, development, and post-bake treatment are performed using a mask to form a channel of 40 μm × A partition wall having an opening of 100 μm was produced. Next, the coating is further applied by spin coating so as to have a film thickness of 1 μm, and a partition wall having a width of 5 μm and a height of 1 μm is formed at the center of the opening.

  Surface treatment is performed to make the partition surface water repellent. Plasma treatment was performed on the glass substrate on which the partition walls were formed using a plasma treatment apparatus under the following conditions.

Gas used: CF ₄
Gas flow rate: 330sccm
Pressure: 44Pa
RF power: 1200W
Processing time: 120 sec
The contact angle of the partition wall surface after the plasma treatment was 87 °.

  Next, a source electrode and a drain electrode are formed. A poly 3,4-ethylenedioxythiophene / polystyrene sulfonic acid (PEDOT / PSS) aqueous solution (manufactured by Baytron P, Bayer Co. Ltd.) is applied to the opening of a partition wall having a height of 2 μm using a piezoelectric ink jet and dried. By doing so, the applied PEDOT / PSS aqueous solution is divided into two by a partition wall having a height of 1 μm provided at the center, and these are used as a source electrode and a drain electrode, respectively. At this time, the width between the source and the drain is 5 μm, the channel length L is 5 μm, and the channel width W is 100 μm.

As the insulating layer, SiO ₂ was deposited, and finally, as the organic semiconductor layer, pentacene was deposited to 200 nm by vapor deposition in an ultrahigh vacuum chamber. The electric characteristics of the obtained field effect transistor were measured in a vacuum using a 4145B semiconductor parameter analyzer manufactured by Hewlett-Packard.

  The mobility μ can be obtained from Equation 5 obtained by differentiating Equation 1 that gives the drain current in the linear region of the field effect transistor with respect to the gate voltage Vg.

計算より得られた移動度は０．２３ｃｍ^２/V・ｓ、ＯＮ/OFF比は１０^７以上であり、アモルファスＳｉ半導体には及ばないものの、良好なトランジスタ特性が得られた。

The mobility obtained from the calculation was 0.23 cm ² / V · s, and the ON / OFF ratio was 10 ⁷ or more, and although it did not reach the amorphous Si semiconductor, good transistor characteristics were obtained.

A field effect transistor having the structure shown in FIG. 1 was produced. A PMMA is formed on a glass substrate by 2.5 μm, a Ni mold on which a pattern is formed is pressed against the substrate, and a pattern having a partition wall having a width of 5 μm and a height of 1 μm in the center of a groove having a width of 40 μm, a length of 100 μm, and a depth of 2 μm. Transcript. Next, the base layer of PMMA is removed by dry etching using CF ₄ gas with an RIE apparatus. As a result, the glass surface is exposed at the portion without PMMA, and the hydrophilicity is high, and the water repellency is obtained at the PMMA surface. A poly 3,4-ethylenedioxythiophene / polystyrene sulfonic acid (PEDOT / PSS) aqueous solution (manufactured by Baytron P, Bayer Co. Ltd.) is applied to the opening of a partition wall having a height of 2 μm using a piezoelectric ink jet and dried. By doing so, the applied PEDOT / PSS aqueous solution is divided into two by a partition wall having a height of 1 μm provided at the center, and these are used as a source electrode and a drain electrode, respectively. At this time, the width between the source and the drain is 5 μm, the channel length L is 5 μm, and the channel width W is 100 μm.

By the same method as in [Example 1], an insulating layer and an organic semiconductor layer are formed to complete a field effect transistor. By the same method as in Example 1, the measured mobility was 0.28 cm ² / V · s, the ON / OFF ratio was 10 ⁷ or more, and good transistor characteristics were obtained.

  A field effect transistor having the structure shown in FIG. 2 was produced.

  As a gate electrode on a glass substrate, a gold electrode is patterned by photolithography and vapor deposition. The width of the gate electrode constituting the field effect transistor at this time was designed to be 5 μm. Next, photosensitive polyimide is formed with a film thickness of 300 nm by spin coating. Exposure is performed using a mask, development and post-baking are performed, and a partition wall having a width of 10 μm and a height of 300 μm is formed on the gate electrode. Next, “CT-2000L resist” manufactured by Fujifilm Olin was applied by spin coating to a film thickness of 2 μm, exposed using a mask, developed and post-baked, and on both sides of the polyimide partition wall. A partition wall having a height of 2 μm was formed. Surface treatment by plasma treatment is performed under the same conditions as in [Example 1] for water repellency of the partition wall surface.

  Next, a source electrode and a drain electrode are formed. A poly 3,4-ethylenedioxythiophene / polystyrene sulfonic acid (PEDOT / PSS) aqueous solution (manufactured by Baytron P, Bayer Co. Ltd.) is applied to the opening of a partition wall having a height of 2 μm using a piezoelectric ink jet and dried. By doing so, the applied PEDOT / PSS aqueous solution is divided into two by a partition having a height of 300 nm provided in the center, and each is used as a source electrode and a drain electrode. At this time, the width between the source and the drain is 5 μm, the channel length L is 15 μm, and the channel width W is 100 μm.

A field effect transistor was obtained by forming polyhexylthiophene as an organic semiconductor layer with a film thickness of 300 nm by spin coating using chloroform solvent. The transistor characteristics were measured in the same manner as in [Example 1]. At this time, the mobility was 0.01 cm ² / V · s, the ON / OFF ratio was 10 ⁵ or more, and good transistor characteristics were obtained although it was not possible when pentacene, which is a low molecular material, was used. .

As in [Example 3] in which the field effect transistor having the structure shown in FIG. 2 was fabricated, PMMA was formed to 2.5 μm on a substrate provided with a gate electrode, and a Ni mold on which a pattern had been formed was pressed against the substrate. A pattern having a partition wall having a width of 10 μm and a height of 300 nm is transferred to the center of a groove having a length of 40 μm, a length of 100 μm, and a depth of 2 μm. Next, the base layer of PMMA is removed by dry etching using CF ₄ gas with an RIE apparatus. As a result, the glass surface is exposed at the portion without PMMA, and the hydrophilicity is high, and the water repellency is obtained at the PMMA surface.

Next, Ag metal paste made of vacuum metallurgy was used to adjust the viscosity to 10 mPa · s as the source and drain electrodes, applied to the opening of the partition wall by piezoelectric ink jet, and dried by heating at 200 ° C. Although the nano paste ink was divided into two parts, a part that was not completely separated was observed. Therefore, dry etching was performed using CF ₄ gas by an RIE apparatus, and each was used as a source electrode and a drain electrode. Use. The etching time at this time was adjusted so that the width between the source and the drain was 10 μm. Next, polyhexylthiophene was formed with a film thickness of 300 nm by spin coating using a chloroform solvent, and the transistor characteristics were measured in the same manner as in [Example 1]. The mobility at this time is 0.005 cm ² / V · s, the ON / OFF ratio is 10 ⁶ or more, and the ON / OFF ratio is good, but the mobility deteriorates as compared with [Example 3]. ing. This is thought to be because a barrier was formed between the semiconductor layer and the electrode because Ag nanopaste was used as the source and drain electrodes and the work function was lower than that of PEDOT.

(Comparative Example 1)
A field effect transistor having the structure shown in FIG. 6 was prepared. A “CT-2000L resist” made by Fuji Film Orin is applied on a glass substrate by spin coating to a thickness of 2 μm, exposed using a predetermined mask, developed and post-baked by a predetermined method, and a partition wall is formed. Produced. A partition wall having a width of 5 μm and a length of 100 μm was formed in a region to be a channel.

  Surface treatment is performed to make the partition surface water repellent. Plasma treatment was performed on the glass substrate on which the partition walls were formed using a plasma treatment apparatus under the following conditions.

Gas used: CF ₄
Gas flow rate: 330sccm
Pressure: 44Pa
RF power: 1200W
Processing time: 120 sec
The contact angle of the partition wall surface after the plasma treatment was 87 °.

  A source electrode and a drain electrode are formed adjacent to the partition wall. By applying a poly 3,4-ethylenedioxythiophene / polystyrene sulfonic acid (PEDOT / PSS) aqueous solution (manufactured by Baytron P, Bayer Co. Ltd.) to the opening of the partition wall using a piezoelectric ink jet and drying, Although the applied PEDOT / PSS aqueous solution was divided into two, the film thickness of the source / drain electrodes was formed with variations. At this time, the width between the source and the drain varied between 10 and 15 μm.

After forming an insulating layer and an organic semiconductor layer by the same method as in [Example 1], the electric characteristics of the obtained field effect transistor were measured by the same method as in [Example 1]. The mobility at this time was as good as 0.21 cm ² / V · s, but the ON / OFF ratio was about 20 to 50, and although the transistor characteristics were exhibited, sufficient characteristics were not obtained.

(Comparative Example 2)
A field effect transistor having the structure shown in FIG. 6 was prepared. As in [Example 3], photosensitive polyimide is formed to a thickness of 300 nm by spin coating on a substrate provided with a gate electrode. Using a mask, exposure, development, and post-bake are performed, and a barrier rib is formed on the gate electrode with a width of 10 μm, the same thickness as the barrier rib of 300 μm height, and 15 μm apart on both sides. . Surface treatment by plasma treatment is performed under the same conditions as in [Example 1] for water repellency of the partition wall surface. Next, a poly 3,4-ethylenedioxythiophene / polystyrene sulfonic acid (PEDOT / PSS) aqueous solution (manufactured by Baytron P, Bayer Co. Ltd.) is applied to the opening of the partition using a piezoelectric ink jet and dried. Thus, the applied PEDOT / PSS aqueous solution is divided into two by a partition having a height of 300 nm provided at the center thereof. At this time, the source electrode and the drain electrode are each formed in a convex shape, and are formed away from the central partition wall in some places, so the source-drain electrode distance varies. After forming the organic semiconductor layer by the same method as in [Example 3], the electric characteristics of the obtained field effect transistor were measured by the same method as in [Example 1]. The mobility at this time was as good as 0.21 cm ² / V · s, but the ON / OFF ratio was about 20 to 50, and although the transistor characteristics were exhibited, sufficient characteristics were not obtained. 0.01 cm ² / V · s, ON / OFF ratio was about 50, and although the transistor characteristics were shown, sufficient characteristics were not obtained.

The schematic diagram which shows the cross section of one Embodiment of the field effect transistor of this invention. The schematic diagram which shows the cross section of other embodiment of the field effect transistor of this invention. The process drawing of one Embodiment of the manufacturing method of the field effect transistor of this invention. Process drawing of other embodiment of the manufacturing method of the field effect transistor of this invention. The schematic diagram which shows the cross section of the conventional field effect transistor. Process drawing which shows the method of partition formation in nanoimprint. The schematic diagram which shows the cross section of the field effect transistor of a comparative example. The schematic diagram which shows the cross section of the field effect transistor of a comparative example.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Support substrate 2 Gate electrode 3 Insulating layer 4 Partition 5 Source electrode 6 Drain electrode 7 Organic-semiconductor layer 8 Inkjet head 9 Ink droplet 10 Mold substrate 11 Pentacene 12 Thermosetting resin

Claims (8)

  In a field effect transistor having at least a support substrate, a source electrode, a drain electrode, a semiconductor layer, an insulating layer, and a gate electrode, and using an organic substance as the semiconductor layer, the source electrode and the drain electrode are formed in the same plane, A field effect transistor characterized in that a partition wall having an insulating property is provided adjacent to at least the source electrode and the drain electrode, and the height of the partition wall is different between the source and the drain and other portions. .   In a field effect transistor in which a source electrode and a drain electrode are formed on the same plane on a supporting substrate, and a semiconductor layer, an insulating layer, and a gate electrode are provided in that order, the height of the partition between the source and drain and the partition 2. The field effect transistor according to claim 1, wherein the sum of the film thicknesses of the semiconductor layer and the insulating layer is thin due to a difference between the height of the partition walls at other higher positions.   In a field effect transistor in which barrier ribs having different heights are provided in the same plane on a supporting substrate on which a gate electrode is disposed, and between the source and the drain, and a semiconductor layer is formed above the source and drain electrodes. 2. The field effect transistor according to claim 1, wherein a width of the partition wall is wider than that of the gate electrode between the source and drain electrodes.   4. The electric field according to claim 1, wherein the partition walls adjacent to the source electrode and the drain electrode are formed of two types of resin compositions. 5. Effect transistor.   The field effect transistor manufacturing method according to any one of claims 1 to 3, further comprising a step of transferring and forming the partition wall from a second substrate having a partition wall shape formed in advance. Method.   The conductive liquid material applied between the high barrier ribs is separated spontaneously by the low barrier ribs during drying to form a source electrode and a drain electrode. A method for producing the field effect transistor according to any one of the above items.   4. The method of manufacturing a field effect transistor according to claim 1, further comprising a step of forming the source electrode and the drain electrode by an inkjet method. 5.   4. The method of manufacturing a field effect transistor according to claim 1, further comprising a step of forming the organic semiconductor layer by an inkjet method.

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