JP2000276076A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which has high reliability by arranging TFTs(thin film transistors) is a proper structure according to the circuit function. SOLUTION: The semiconductor device has a driving circuit part and a pixel part on the same substrate; and a hold capacitor is formed of an electrode 103 formed in the same layer as a light shield film 102 and a semiconductor film 118 of the same composition as a drain region 115 and at the part of the hold capacitor, a 1st insulating film 104 is removed to use a 2nd insulating film 105 as a dielectric 106. Consequently, the hold capacitor having a large capacity with a small area can be secured.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a circuit composed of thin film transistors (hereinafter, referred to as TFTs). For example, a liquid crystal display device or EL (Electric
Electro-optical devices such as display devices
Device, semiconductor circuit and electro-optical device or semiconductor device of the present invention
The present invention relates to a configuration of an electric appliance (electronic device) using a body circuit.

[0002] In this specification, a semiconductor device generally means a device that can function by utilizing semiconductor characteristics, and an electro-optical device, a semiconductor circuit, and an electric appliance are all semiconductor devices.

[0003]

2. Description of the Related Art Since a thin film transistor (hereinafter, referred to as TFT) can be formed on a transparent substrate, an active matrix type liquid crystal display (hereinafter, referred to as AM-LC) is used.
D) has been actively promoted. Since a TFT using a crystalline semiconductor film (typically, a polysilicon film) has high mobility, it is possible to realize a high-definition image display by integrating functional circuits on the same substrate. I have.

Basically, an AM-LCD has a pixel portion for displaying an image (also referred to as a pixel matrix circuit) and a gate drive circuit (gate circuit) for driving a TFT of each pixel arranged in the pixel portion.
Source driver circuit ( also called a source driver circuit ) that sends an image signal to each pixel TFT.
) Or data drive circuit (also with data driver circuit)
Are formed on the same substrate. The gate drive
A driving circuit in which an area where the driving circuit and the source driving circuit are formed
We call a department.

In recent years, a system-on-panel has been proposed in which a signal processing circuit such as a signal dividing circuit and a gamma correction circuit is provided on the same substrate in addition to the pixel section and the driving circuit section.

However, since the performance required by the circuit is different between the pixel portion and the drive circuit portion, it is difficult to satisfy all the circuit specifications with the TFT having the same structure. That is,
Drive circuits including shift register circuits, etc. that emphasize high-speed operation
TFT constituting a road section, the pixel section that emphasizes high withstand voltage characteristics
(Hereinafter referred to as pixel TFT)
At present, the T structure has not been established.

Therefore, the applicant of the present invention has proposed a T
An application has been filed in which the thickness of the gate insulating film is made different between an FT (hereinafter, referred to as a driving TFT) and a pixel TFT (Japanese Patent Application Laid-Open No. 10-056184, and corresponding US Pat. No. 08 / 862,895). Specifically, the driving TFT
Is made thinner than the gate insulating film of the pixel TFT.

[0008]

In the present invention, the pixel portion is further improved based on the configuration described in the above publication. Specifically, an object of the present invention is to provide a structure for forming a storage capacitor capable of securing a large capacity in a small area.

It is another object of the present invention to provide a highly reliable electro-optical device by forming each circuit of an electro-optical device represented by an AM-LCD with a TFT having an appropriate structure according to a function. In addition, it is an object to increase the reliability of a semiconductor device (electric appliance) having such an electro-optical device as a display portion .

[0010]

According to the invention disclosed in the present specification, each pixel has a pixel TFT and a storage capacitor.
In the semiconductor device including the element portion, the activation of the pixel TFT
The layers are shielded with at least two layers of insulating film sandwiched between them.
The storage capacitor is formed above an optical film, and the storage capacitor is
Electrode, dielectric and pixel TFT formed on the same layer
Formed of a semiconductor film having the same composition as the drain region of
The dielectric is laminated on the at least two layers.
It is characterized by being composed of a part of an insulating film.

Further, in another configuration of the present invention, each pixel has a pixel T.
In a semiconductor device including a pixel portion having an FT and a storage capacitor,
The active layer of the pixel TFT has at least two layers.
It is formed above the light-shielding film with the laminated insulating film
The storage capacitor is formed by an electric current formed in the same layer as the light shielding film.
Same as the pole, dielectric and drain region of the pixel TFT
The dielectric is formed of a semiconductor film having a composition.
Remove at least some layers of insulating film laminated in two or more layers
It is characterized by comprising the remaining layer.

Further, in another configuration of the present invention, each pixel has a pixel T.
In a semiconductor device including a pixel portion having an FT and a storage capacitor,
And the active layer of the pixel TFT is in contact with the light-shielding film.
With the first insulating film and the second insulating film in contact with the active layer interposed therebetween
The storage capacitor is formed above the light shielding film, and the storage capacitor is
An electrode formed in the same layer as the above, the second insulating film and the
Formed with a semiconductor film of the same composition as the drain region of the pixel TFT
It is characterized by having been done.

Further, in another configuration of the present invention, each pixel has a pixel T.
In a semiconductor device including a pixel portion having an FT and a storage capacitor,
And the active layer of the pixel TFT is in contact with the light-shielding film.
With the first insulating film and the second insulating film in contact with the active layer interposed therebetween
The storage capacitor is formed above the light shielding film, and the storage capacitor is
An electrode formed in the same layer as the above, the second insulating film and the
Formed with a semiconductor film of the same composition as the drain region of the pixel TFT
It is characterized by having been done.

In the above structure, the second insulating film
Is a laminated film composed of the first insulating film and the second insulating film.
1/5 or less of the film thickness (preferably 1/100 to 1/1)
0 times) .

Further, in another configuration of the present invention, each pixel has a pixel T.
Fabrication of a semiconductor device including a pixel portion having an FT and a storage capacitor
A light shielding film and the same light shielding film as the light shielding film on the substrate.
Forming an electrode made of a material;
Forming a first insulating film covering the electrode;
Forming an opening on the electrode by etching the insulating film;
And a second step covering the first insulating film and the opening.
Forming an insulating film; and forming a semiconductor on the second insulating film.
Forming a film.

Another embodiment of the present invention relates to a driving circuit
Each pixel includes a pixel portion having a pixel TFT and a storage capacitor.
A method for manufacturing a semiconductor device, comprising:
Forming an electrode made of the same material as the light-shielding film;
Forming a first insulating film covering the light shielding film and the electrode;
And etching the first insulating film on the electrode.
Forming an opening in the first insulating film and the opening;
Forming a second insulating film covering the opening;
Forming a semiconductor film on the edge film;
Forming a gate insulating film overlying the gate insulating film;
Part of the film is etched, and the semiconductor film and the drive circuit portion are removed.
Exposing a part of the semiconductor film of the pixel portion and
Oxidation treatment exposes the gate insulating film
Forming a thermal oxide film on the surface of the presented semiconductor film;
It is characterized by having.

Another embodiment of the present invention provides a driving circuit
Each pixel includes a pixel portion having a pixel TFT and a storage capacitor.
A method for manufacturing a semiconductor device, comprising:
Forming an electrode made of the same material as the light-shielding film;
Forming a first insulating film covering the light shielding film and the electrode;
And etching the first insulating film on the electrode.
Forming an opening in the first insulating film and the opening;
Forming a second insulating film covering the opening;
Forming a semiconductor film on the edge film;
Forming a gate insulating film overlying the gate insulating film;
Part of the film is etched, and the semiconductor film and the drive circuit portion are removed.
Exposing a part of the semiconductor film of the pixel portion and
Oxidation treatment exposes the gate insulating film
Forming a thermal oxide film on the surface of the presented semiconductor film;
In the semiconductor film of the drive circuit portion and the semiconductor film of the pixel portion,
Forming an LDD region, wherein the drive circuit portion and the pixel portion have different lengths of the LDD region.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to FIG. FIG. 1 is a cross-sectional view of an AM-LCD in which a drive circuit portion and a pixel portion are integrally formed on the same substrate. Here, a CMOS circuit is shown as a basic circuit constituting the drive circuit portion, and a TFT having a double gate structure is shown as a pixel TFT. Needless to say, a multi-gate structure such as a triple gate structure or a single gate structure is not limited to the double gate structure.

In FIG. 1, reference numeral 101 denotes a substrate having heat resistance, which may be a quartz substrate, a silicon substrate, a ceramic substrate, or a metal substrate (typically, a stainless steel substrate). Whichever substrate is used, a base film (preferably, an insulating film containing silicon as a main component) may be provided as necessary.

Reference numeral 102 denotes a light-shielding film, and reference numeral 103 denotes a lower electrode of a storage capacitor. The material for forming the light-shielding film 102 and the lower electrode 103 of the storage capacitor is 800 to 1150 ° C. (preferably 900 to 150 ° C.).
(1100 ° C.) is used.

Typically, a conductive silicon film (for example, a phosphorus-doped silicon film, a boron-doped silicon film, or the like), a metal film (for example, a tungsten film, a tantalum film, a molybdenum film, a titanium film, or the like) or a film of the above metal film An alloy film combining components may be used. Further, a silicide film in which the metal film is silicided, or a nitrided film (a tantalum nitride film, a tungsten nitride film, a titanium nitride film, or the like) may be used. Further, these may be freely combined and laminated.

When the metal film is used, it is preferable that the metal film has a laminated structure with a silicon film in order to prevent oxidation of the metal film. Further, from the viewpoint of preventing oxidation, a structure in which a metal film is covered with an insulating film containing silicon as a main component is also effective. Note that in this specification, “an insulating film containing silicon as its main component” refers to a silicon oxide film, a silicon nitride film, or an insulating film containing silicon, oxygen, and nitrogen at a predetermined component ratio.

Reference numeral 104 denotes a base film ( hereinafter referred to as a base film) having a thickness of 0.3 to 1 μm (preferably 0.6 to 0.8 μm).
(Hereinafter, referred to as a first insulating film), which is formed of an insulating film containing silicon as a main component. In the first insulating film 104, an opening is provided in a portion serving as a storage capacitor, and an insulating film (hereinafter, referred to as a second insulating film) 105 containing silicon as a main component is provided thereon.

Here, the first insulating film in contact with the light shielding film
104 and a second insulating film 105 in contact with the active layer of the pixel TFT
However, a multi-layer structure may be employed.
Therefore, the pixel TFT has at least two active layers.
Above the light-shielding film 102 with the insulating film laminated as described above interposed therebetween.
The structure is formed. Also, this at least two layers
Layer of the insulating film laminated on the substrate (one or more layers
Becomes a dielectric of the storage capacitor. In other words, at least
Is also obtained by removing some layers of the insulating film laminated on two or more layers.
The other layer becomes a dielectric of the storage capacitor.

In this embodiment, the second insulating film 105 functions as a dielectric of the storage capacitor (particularly, a portion indicated by 106). This second insulating film 105 (the dielectric 1 of the storage capacitor)
06) is 5 to 75 nm (preferably 20 to 50 nm)
It is good. The thinner the storage capacity, the larger the capacity of the storage capacitor can be. It is effective to improve the withstand voltage by stacking the film twice.

The first insulating film 104 has a T
It is necessary to have a sufficiently large film thickness so as not to form the FT and the parasitic capacitance. However, by providing the opening in the storage capacitance portion in this manner, the dielectric of the storage capacitance can be made thin. Therefore, capacity can be obtained without increasing the area for forming the capacitor. The configuration of the storage capacitor is not described in the above-mentioned Japanese Patent Application Laid-Open No. 10-056184.

The structure of FIG. 1 is characterized by the pixel T
The thickness of the insulating film (laminated film composed of the first insulating film 104 and the second insulating film 105) provided between the FT active layer and the light-shielding film 102, and the upper electrode 1 of the storage capacitor made of a semiconductor film
18 and the lower electrode 103 of the storage capacitor .
2 is that the thickness of the insulating film 105 (dielectric 106 of the storage capacitor) is different. Specifically, the film thickness of the latter is designed to be 1/5 or less (preferably 1/100 to 1/10 ) as compared with the former.

By doing so, the pixel TFT and the light shielding film 10 are formed.
Thus, a storage capacitor having a large capacity can be formed without forming a parasitic capacitance between the storage capacitor and the storage capacitor 2.

The light-shielding film 102 provided below the pixel TFT may be set in a floating state or a fixed potential. As the fixed potential, it is desirable to set at least a potential lower than the lowest potential of the video signal, preferably a lowest power supply potential of the entire circuit formed on the substrate or a potential lower than the lowest power supply potential.

For example, in the case of an AM-LCD, various power supply lines are formed by a driving circuit section and other signal processing circuits and a pixel section, and a predetermined potential is applied to each of them.
In other words, there is a certain reference minimum potential, and various voltages are formed based on the lowest potential. The minimum power supply potential refers to a minimum potential that is a reference in all of those circuits.

As described above, the light shielding film 102 is floating.
By setting the state or the fixed potential , it is possible to obtain a light-shielding film that does not affect the TFT operation (forms almost no parasitic capacitance or the like).

As described above, by providing the light-shielding film under the pixel TFT, it is possible to prevent the occurrence of light leakage current due to stray light from the substrate side. It is not necessary to provide a light-shielding film because light is not originally applied to the drive circuit portion side. This is preferable in terms of reducing the parasitic capacitance even slightly.

The first insulating film 104 and the second insulating film 10
On 5, an active layer of a driving TFT, an active layer of a pixel TFT, and a semiconductor film to be an upper electrode of a storage capacitor are formed.
Note that in this specification, an “electrode” is a part of a “wiring” and indicates a portion where an electrical connection with another wiring is made or a portion which intersects with a semiconductor film. Therefore, for convenience of explanation, “wiring” and “electrode” are properly used, but it is assumed that the term “wiring” always includes “electrode”.

In FIG. 1, the active layer of the driving TFT includes N
Source region 107, drain region 108, LDD (lightly doped drain) region 109, and channel forming region 11 of a channel type TFT (hereinafter referred to as NTFT)
0, and a source region 111, a drain region 112, and a channel formation region 113 of a P-channel TFT (hereinafter, PTFT).

The active layer of the pixel TFT (here, NTFT is used) is composed of the source region 114 and the drain region 1.
15, LDD regions 116a and 116b and channel forming regions 117a and 117b. Further, the semiconductor film extended from the drain region 115 is used as the upper electrode 118 of the storage capacitor. That is, the upper electrode 11 of the storage capacitor
Reference numeral 8 denotes a semiconductor film having the same composition as the drain region 115.

As described above, the holding capacity of the present invention is
An electrode formed in the same layer as the optical film 102 (here, the holding
A lower electrode 103 of the capacitor), a dielectric (here, a second insulating film)
105) and the same composition as the drain region of the pixel TFT.
Semiconductor film (here, drain region 115 of pixel TFT)
It is formed with.

However, the drain region and the upper electrode of the storage capacitor do not necessarily have to be directly connected, and may be electrically connected by another wiring. Further, the semiconductor film does not necessarily have to have the same composition, and may be a semiconductor film having another conductivity type or a semiconductor film containing the same impurity as the drain region at different concentrations.

Here, in the case of FIG. 1, the width (length) of the LDD region is different between the driving TFT and the pixel TFT. Since the driving TFT emphasizes the operation speed, the driving TFT is provided as narrow as possible without providing a resistance component.
Since emphasis is placed on the reduction of the drain current flowing when T is in the OFF state, a somewhat long LDD region is required. Therefore, the LDD region of the driving TFT is the LDD region of the pixel TFT.
It is preferable to provide the same as or smaller than the region.

Then, a gate insulating film is formed so as to cover the active layer and the upper electrode of the storage capacitor. In the present invention, the thickness of the gate insulating film 119 of the driving TFT is equal to the thickness of the gate insulating film 120 of the pixel TFT. It is formed thinner. Typically, the thickness of the gate insulating film 120 is 50 to 200 nm.
(Preferably 100 to 150 nm) and the gate insulating film 1
The thickness of the film 19 may be 5 to 50 nm (preferably 10 to 30 nm).

It should be noted that the gate insulating film of the driving TFT does not need to have one kind of film thickness. That is, it is different in the drive circuit section.
A driving TFT having an insulating film having a film thickness may be present. In that case, at least three or more types of TFTs having gate insulating films of different thicknesses exist on the same substrate. That is, it can be said that the thickness of the gate insulating film of at least a part of the driving TFT included in the driving circuit portion is smaller than the thickness of the gate insulating film of the pixel TFT.

Next, on the gate insulating films 119 and 120, the gate wirings 121 and 122 of the driving TFT and the pixels TF
T gate wirings 123a and 123b are formed. The material for forming the gate wirings 121, 122, 123a, and 123b is 800 to 1150 ° C. (preferably 900 to 110 ° C.).
(0 ° C.) is used.
Specifically, the material may be selected from the same materials as those for the light-shielding film 102 or the lower electrode 103 of the storage capacitor.

That is, a conductive silicon film (for example, a phosphorus-doped silicon film, a boron-doped silicon film, etc.), a metal film (for example, a tungsten film, a tantalum film, a molybdenum film, a titanium film, etc.) or a combination of the components of the above metal film Alloy film may be used. Alternatively, a silicide film in which the metal film is silicided, a nitrided film (a tantalum nitride film,
Tungsten nitride film, titanium nitride film, etc.). Further, these may be freely combined and laminated.

When the metal film is used, it is preferable that the metal film has a laminated structure with a silicon film in order to prevent oxidation of the metal film. In terms of preventing oxidation, a structure in which a metal film is covered with an insulating film containing silicon as a main component is effective. In FIG. 1, a protective film 124 is provided to prevent oxidation of the gate wiring.

Next, reference numeral 125 denotes a first interlayer insulating film, which is formed of an insulating film (single-layer or laminated) containing silicon as a main component. As the insulating film containing silicon as a main component, a silicon oxide film,
A silicon nitride film, a silicon oxynitride film (having a higher nitrogen content than oxygen), or a silicon nitride oxide film (having a higher oxygen content than nitrogen) can be used.

A contact hole is provided in the first interlayer insulating film 125, and the source wiring 12 of the driving TFT is formed.
6, 127, a drain wiring 128, and a source wiring 129 and a drain wiring 130 of the pixel TFT are formed.
A passivation film 131 and a second interlayer insulating film 132 are formed thereon, and a light-shielding film (black mask) 133 is further formed thereon. Further, a third interlayer insulating film 134 is formed on the light-shielding film 133, and a pixel electrode 135 is formed after providing a contact hole.

The second interlayer insulating film 132 and the third interlayer insulating film 1
As 34, a resin film having a small relative dielectric constant is preferable. As the resin film, a polyimide film, an acrylic film, a polyamide film, a BCB (benzocyclobutene) film, or the like can be used.

The pixel electrode 135 is a transmission type A
To manufacture an M-LCD, a transparent conductive film typified by an ITO film may be used, and to manufacture a reflective AM-LCD, a metal film having a high reflectivity typified by an aluminum film may be used.

Although the pixel electrode 135 is electrically connected to the drain region 115 of the pixel TFT via the drain electrode 130 in FIG. 1, the pixel electrode 135 and the drain region 115 are directly connected. It is good also as a structure.

The AM-LCD having the above structure is
The gate insulating film of the driving TFT is thinner than the gate insulating film of the pixel TFT, and the first insulating film is selectively removed at a portion to be a storage capacitor, and the thin second insulating film functions as a dielectric of the storage capacitor. . At this time, since the sufficiently thick first insulating film is provided between the light-shielding film 102 provided below the pixel TFT and the active layer, there is no problem of the parasitic capacitance.

Thus, the most suitable TFT according to the performance of the circuit
Can be arranged, and at the same time, a storage capacitor that can secure a large capacity in a small area can be realized.

The present invention having the above configuration will be described in more detail with reference to the following embodiments.

[0052]

[Embodiment 1] In this embodiment, a manufacturing process for realizing the structure of FIG. 1 described in "Embodiment of the Invention" will be described. 2 to 5 are used for the description.

First, a quartz substrate 201 is prepared as a substrate, and a light-shielding film using a laminated film of a silicon film / tungsten nitride film / tungsten film (or a silicon film / tungsten silicide film / silicon film from the lower layer) is formed thereon. 20
2. The lower electrode 203 of the storage capacitor is formed. Of course, other conductive films described in “Embodiments of the invention” can also be used. In this embodiment, the thickness is set to 200 nm.

Next, the lower portion of the light-shielding film 202 and the storage capacitor is charged.
A first silicon oxide film covering the pole 203 and having a thickness of 0.6 μm;
An insulating film 204 is formed, and a portion serving as a storage capacitor (storage capacitor
(On the lower electrode 203) is selectively etched to form an opening 205. Then, the first insulating film 204 and the opening
The silicon oxide film (second insulating film) 206 and the amorphous silicon film 207 having a thickness of 20 nm are covered by the low pressure thermal CVD method so as to cover the opening 205.
Are continuously formed without exposing them to the atmosphere. This prevents impurities such as boron contained in the air from adsorbing to the lower surface of the amorphous silicon film.

In this embodiment, an amorphous silicon (amorphous silicon) film is used, but another semiconductor film may be used. A microcrystalline silicon (microcrystalline silicon) film or an amorphous silicon germanium film may be used.

The second insulating film 206 is an insulating film that functions as a dielectric of a storage capacitor. Therefore, in this embodiment, silane (SiH ₄ ) and nitrous oxide (N
_{Using 2} O), a high quality silicon oxide film (dielectric) is formed at a film forming temperature of 800 ° C.

Next, the amorphous silicon film 207 is crystallized. A known technique can be used as the crystallization means. In this embodiment, the crystallization means is disclosed in JP-A-9-3
The technique described in JP-A-12260 is used. The technology described in the publication discloses nickel, cobalt, palladium, germanium, platinum, as a catalyst element for promoting crystallization,
Amorphous by solid phase growth using elements selected from iron and copper
The silicon film is crystallized.

In this embodiment, nickel is selected as a catalyst element, and a layer (not shown) containing nickel is formed on the amorphous silicon film 207. Then, a heat treatment at 550 ° C. for 4 hours is performed to crystallize the crystalline silicon (polysilicon) film 20.
8 is formed. Thus, the state shown in FIG. 2B is obtained.

Here, an impurity element (phosphorus or boron) for controlling the threshold voltage of the TFT may be added to the crystalline silicon film 208. Phosphorus or boron may be separated, or only one of them may be added.

Next, a mask film 209 made of a silicon oxide film having a thickness of 100 nm is formed on the crystalline silicon film 208, and a resist mask 210 is formed thereon. Further, the mask film 209 is etched using the resist mask 210 as a mask to form openings 211a to 211c.

In this state, an element belonging to Group 15 of the periodic table (phosphorus in this embodiment) is added to form phosphorus-added regions (phosphorus-doped regions) 212a to 212c. The concentration of phosphorus to be added is ^{5 × 10 18 ~1 × 10 20} atoms / cm 3 ( preferably ^{1 × 10 19 ~5 × 10 1} 9 atoms / cm 3) is preferable. However, the concentration of phosphorus to be added varies depending on the temperature and time of the later gettering step and the area of the phosphorus-doped region, and is not limited to this concentration range. (Fig. 2 (C))

Next, the resist mask 210 is removed and 4
A heat treatment at 50 to 650 ° C. (preferably 500 to 600 ° C.) is applied for 2 to 16 hours to perform a gettering step of nickel remaining in the crystalline silicon film. To achieve the gettering action, a temperature of about ± 50 ° C. from the maximum temperature of the heat history is required, but the heat treatment for crystallization requires 550 to 60 ° C.
Since the heat treatment is performed at 0 ° C., the gettering action can be sufficiently exerted by the heat treatment at 500 to 650 ° C.

In this embodiment, nickel is moved in the direction of the arrow by heat treatment at 600 ° C. for 8 hours and gettered (trapped) in the phosphorus-added regions 212a to 212c. In this way, the concentration of nickel remaining in the crystalline silicon film indicated by 213 and 214 is reduced to 2 × 10 ¹⁷ atoms / cm ³ or less (preferably 1 × 10 ¹⁶ atoms / cm ³ or less). However, this concentration depends on mass secondary ion analysis (SIM
This is a measurement result according to S), and a concentration lower than this cannot be confirmed at present because of the measurement limit. (FIG. 3 (A))

When the nickel gettering step is completed, the crystalline silicon films 213 and 214 are patterned to form an active layer (semiconductor film) 215 of the driving TFT and a pixel T.
An FT active layer 216 is formed. At this time, it is desirable to completely remove the phosphorus-added region that has captured nickel.

Then, a gate insulating film 217 is formed by a plasma CVD method or a sputtering method. This gate insulating film functions as a gate insulating film of the pixel TFT, and has a thickness of 50 to 200 nm. In this embodiment, a silicon oxide film having a thickness of 100 nm is used. A stacked structure in which a silicon nitride film is provided over a silicon oxide film as well as a silicon oxide film can be used, or a silicon oxynitride film in which nitrogen is added to a silicon oxide film can be used.

[0066] After forming the gate insulating film 217, etching the gate insulating film provided resist mask (not shown)
And a part of the active layer of the driving circuit portion and the active layer of the pixel portion.
Expose. That is, the gate insulating film 21 is formed on the pixel TFT.
7 is removed, and the region above the region to be the driving TFT is removed. Thus, the state shown in FIG. 3B is obtained.

Next, at 800-1150 ° C. (preferably 9 ° C.)
A heat treatment step of 15 minutes to 8 hours (preferably 30 minutes to 2 hours) at a temperature of (00 to 1100 ° C.) is performed in an oxidizing atmosphere (thermal oxidation step). In this embodiment, 95
A thermal oxidation treatment is performed at 0 ° C. for 30 minutes.

The oxidizing atmosphere may be a dry oxygen atmosphere or a wet oxygen atmosphere, but a dry oxygen atmosphere is suitable for reducing crystal defects in a semiconductor film.
Further, an atmosphere containing a halogen element in an oxygen atmosphere may be used. This thermal oxidation treatment in an atmosphere containing a halogen element is effective because an effect of removing nickel can be expected.

By performing the thermal oxidation process in this manner, a silicon oxide film (thermal oxide film) 218 of 5 to 50 nm (preferably 10 to 30 nm) is formed on the surface of the semiconductor film exposed by the etching of the gate insulating film. Is done. Finally,
The silicon oxide film 218 functions as a gate insulating film of the driving TFT.

The oxidation reaction also proceeds at the interface between the gate insulating film 217 made of the silicon oxide film remaining in the pixel TFT and the semiconductor film 216 thereunder. Therefore, the thickness of the gate insulating film 219 of the pixel TFT finally becomes 50 to 2
00 nm (preferably 100 to 150 nm).

After the thermal oxidation step is completed, the gate wirings 220 (NTFT side) and 221 of the driving TFT are next formed.
(PTFT side), pixel TFT gate wiring 222a, 2
22b is formed. Note that the gate wirings 222a, 222b
Although two are described because the pixel TFT has a double gate structure, they are actually the same wiring.

In this embodiment, the gate wirings 220 to 2
As the layers 22a and 222b, a laminated film of a silicon film / a tungsten nitride film / a tungsten film (or a silicon film / a tungsten silicide film from a lower layer) is used. Of course,
It goes without saying that other conductive films described in "Embodiments of the invention" can be used. In this embodiment, the thickness of each gate wiring is 250 nm.

In this embodiment, the lowermost silicon film is formed by using a low pressure thermal CVD method. Since the gate insulating film of the driving circuit is as thin as 5 to 50 nm, the sputtering method or plasma CV
When the method D is used, a semiconductor film (active layer) may be used depending on conditions.
May cause damage to Therefore, a thermal CVD method capable of forming a film by a chemical vapor reaction is preferable.

Next, the gate wirings 220 to 222a, 22
2b, a 25 to 50 nm thick SiNxOy (typically, x = 0.5 to 2, y = 0.1 to 0.8) film 22
Form 3 The SiNxOy film 223 prevents oxidation of the gate wirings 220 to 222, and at the same time, functions as an etching stopper when removing a sidewall made of a silicon film. It is effective and effective to reduce the number of pinholes by performing film formation twice.

At this time, it is effective to perform a plasma treatment using a gas containing hydrogen (ammonia gas in this embodiment) as a pretreatment for forming the SiNxOy film 213.
Hydrogen activated (excited) by the plasma by this pretreatment is confined in the active layer (semiconductor film), so that hydrogen termination is effectively performed.

Further, when nitrous oxide gas is added in addition to the gas containing hydrogen, the surface of the object to be treated is washed by the generated moisture, and it is possible to effectively prevent contamination by boron and the like contained in the air. it can.

Thus, the state shown in FIG. 3C is obtained. next,
An amorphous silicon film (not shown) is formed, and anisotropic etching is performed using a chlorine-based gas to form sidewalls 224 and 22.
5, 226a and 226b are formed. After the formation of the sidewalls, resist masks 227a and 227b are formed. After that, an addition step of an element belonging to Group 15 of the periodic table (phosphorus in this embodiment) is performed on the semiconductor films 215 and 216.

At this time, the gate wirings 220 to 222a, 2
22b, the side walls 224 to 226 and the resist masks 227a and 227b serve as a mask, and the impurity region 2
28 to 232 are formed. Impurity regions 228 to 232
The concentration of phosphorus to be added is 5 × 10 ¹⁹ to 1 × 10 ²¹ atom
Adjust to s / cm ³ . In this specification, the phosphorus concentration at this time is represented by (n +). (FIG. 4 (A))

This step may be performed separately for a region where the gate insulating film is a driving TFT and a storage capacitor having a small thickness and a region where a gate insulating film is a pixel TFT having a thick film thickness, or may be performed simultaneously. May be. In the step of adding phosphorus, an ion implantation method for performing mass separation may be used, or a plasma doping method for not performing mass separation may be used. Further, the condition of the acceleration voltage and the dose amount may be set by the practitioner to the optimal values.

After the state shown in FIG. 4A is obtained, the resist masks 227a and 227b and the side walls 2 are formed.
24 to 226a and 226b are removed, and the phosphorus addition step is performed again. In this step, the doping is performed at a lower dose than in the previous step of adding phosphorus. Thus, a low-concentration impurity region is formed in a region where phosphorus has not been added in the previous step. The concentration of phosphorus added to this low concentration impurity region is 5 × 10 ¹⁷ to
Adjust so as to be 5 × 10 ¹⁸ atoms / cm ³ . In this specification, the phosphorus concentration at this time is represented by (n-). (FIG. 4
(B))

Of course, this step may be performed separately for a region where the gate insulating film is a thin film transistor TFT and a region where a storage capacitor is formed and a region where a gate insulating film is a thick film TFT and a region where a pixel TFT is thick. You may go. In the step of adding phosphorus, an ion implantation method for performing mass separation may be used, or a plasma doping method for not performing mass separation may be used. Further, the condition of the acceleration voltage and the dose amount may be set by the practitioner to the optimal values.

However, since this low concentration impurity region functions as an LDD region, it is necessary to carefully control the phosphorus concentration. Therefore, in the present embodiment, the concentration distribution (concentration profile) of the added phosphorus is set as shown in FIG. 9 by using the plasma doping method.

In FIG. 9, the gate insulating film 901 on the driving circuit portion and the gate insulating film 902 on the pixel portion have different thicknesses. Therefore, the concentration distribution of the added phosphorus in the depth direction is different.

In this embodiment, the phosphorus addition conditions (acceleration voltage, etc.) are adjusted so that the drive circuit section has the concentration distribution indicated by 903 and the pixel section has the concentration distribution indicated by 904. . In this case, although the concentration distribution in the depth direction is different, the low concentration impurity regions 905 and 9 formed as a result are formed.
The phosphorus concentration of 06 is almost equal.

The process shown in FIG. 9 can be used in all the impurity adding processes described in this specification.

In this step, a CMOS circuit N is formed.
A source region 233, an LDD region 234, and a channel forming region 235 of the TFT are defined. In addition, the source region 236, the drain region 237, and the LDD region 238 of the pixel TFT
a, 238b and channel forming regions 239a, 239b are defined.

Further, the lower electrode 240 of the storage capacitor is defined. In the case of the present embodiment, the first phosphorus addition (n +) step and the second phosphorus addition (n +) are performed on the lower electrode 240 of the storage capacitor.
-) In both steps, phosphorus is added at the same concentration as the source region or the drain region. Therefore, the semiconductor region has the same composition as the source or drain region of the NTFT and has conductivity.

In this step, the PTF of the CMOS circuit is used.
Similarly to the NTFT, the low concentration impurity region 2
41 are formed.

Next, a region other than the region which becomes the PTFT of the CMOS circuit is hidden by the resist masks 242a and 242b, and an element belonging to Group 13 of the periodic table (boron in this embodiment) is added. This step adds a higher concentration of boron than the phosphorus already added. Specifically, 1 × 10 ^{20 to} 3
Adjust so that boron is added at a concentration of × 10 ²¹ atoms / cm ³ . In this specification, the boron concentration at this time is (p +
+). As a result, the impurity regions exhibiting N-type conductivity formed in the region that becomes the PTFT are all inverted in conductivity due to boron and become impurity regions exhibiting P-type conductivity. (FIG. 3 (C))

Of course, also in this step, an ion implantation method for performing mass separation may be used, or a plasma doping method for not performing mass separation may be used. Further, the condition of the acceleration voltage and the dose amount may be set by the practitioner to the optimal values.

In this process, a P for forming a CMOS circuit is formed.
A source region 244, a drain region 245, and a channel formation region 246 of the TFT are defined. Also, the drain region 243 of the NTFT of the CMOS circuit is defined.

After all the impurity regions have been formed, the resist masks 242a and 242b are removed. Then, a heat treatment step is performed in a temperature range of 750 to 1150 ° C. for 20 minutes to 12 hours. In this embodiment, heat treatment at 950 ° C. for 2 hours is performed in an inert atmosphere. (FIG. 5
(A))

In this step, at the same time as activating phosphorus or boron added to each impurity region, the LDD region is expanded inward (toward the channel forming region), and the LDD region and the gate wiring are sandwiched by the gate insulating film. Achieve an overlapping structure.

That is, in the LDD region 247 of the driving TFT, phosphorus contained in the LDD region 247 is changed to the channel forming region 2.
Diffuses towards 48. As a result, the LDD region 247 and the gate wiring 220 overlap with the gate insulating film interposed therebetween . Such a structure is very effective in preventing deterioration due to hot carrier injection.

Similarly, in the PTFT of the driving TFT, the source region 249 and the drain region 250 correspond to the channel forming region 2.
It diffuses in the direction of 51 and overlaps with the gate wiring 221. In the pixel TFT, the LDD regions 252a and 252b
Are diffused in the directions of the channel formation regions 253a and 253b, respectively, and overlap the gate wirings 222a and 222b, respectively.

The diffusion distance of the impurity can be controlled by the temperature and time of the heat treatment. Therefore, the LDD region (or the source and drain regions of the PTFT)
Can be freely controlled. In this embodiment, the overlapping distance is 0.05
調節 1 μm (preferably 0.1 to 0.3 μm).

Further, the phosphorus added to the upper electrode 254 of the storage capacitor is activated by this step, and becomes a region exhibiting N-type conductivity. That is, the semiconductor film can function as the upper electrode 254 without inducing carriers by applying a voltage to the lower electrode 103 of the storage capacitor.

When the state shown in FIG. 5A is obtained,
A first interlayer insulating film 255 is formed. In this embodiment, a silicon oxide film having a thickness of 1 μm formed by a plasma CVD method is used. Then, after forming the contact holes, source wirings 256 to 258 and drain wirings 259 and 260 are formed. These wirings are formed of a stacked film in which a conductive film containing aluminum as a main component is sandwiched between titanium films.

After forming the source wiring and the drain wiring, a hydrogenation process is performed here. This step is a step of exposing the entire substrate to hydrogen excited (activated) by plasma or heat. The temperature of the hydrogenation treatment may be 350 to 450 ° C. (preferably 380 to 420 ° C.) when excited by heat.

Thereafter, a passivation film 261 is formed. As the passivation film 261, a silicon nitride film, a silicon oxynitride film, a silicon nitride oxide film, or a stacked film of these insulating films and a silicon oxide film can be used.
In this embodiment, a silicon nitride film having a thickness of 300 nm is used as a passivation film.

In this embodiment, as a pretreatment for forming a silicon nitride film, a plasma treatment using an ammonia gas is performed, and the passivation film 261 is formed as it is.
Hydrogen activated (excited) by plasma by this pretreatment is confined by the passivation film 261. Further, when nitrous oxide gas is added in addition to the hydrogen-containing gas, the surface of the object to be processed is washed with the generated moisture, and in particular, contamination by boron or the like contained in the air can be effectively prevented.

After the passivation film 261 is thus formed, a heat treatment process at about 400 to 420 ° C. is performed here. The processing atmosphere may be an inert atmosphere or an atmosphere containing hydrogen. In this step, the silicon nitride film 26
1 and the hydrogen contained in a large amount in the first interlayer insulating film 255 by the previous hydrogenation step are diffused downward (in the upward direction, the passivation film 261 becomes a blocking layer). The active layer (semiconductor film) is terminated with hydrogen. As a result, dangling bonds in the active layer can be efficiently inactivated.

After the completion of the hydrogenation, an acrylic film having a thickness of 1 μm is formed as the second interlayer insulating film 262. Then, a titanium film is formed thereon to have a thickness of 200 nm and is patterned to form a black mask 263.

Next, as the third interlayer insulating film 264, 1
A contact hole is formed by forming an acrylic film having a thickness of μm, and a pixel electrode 265 made of an ITO film is formed. Thus, an AM-LCD having a structure as shown in FIG. 5B is completed.

In the AM-LCD of the present invention, the thickness of the gate insulating film differs between the driving circuit portion (or the signal processing circuit portion) and the pixel portion formed on the same substrate. Typically, a driving TFT used in a driving circuit portion has a thinner gate insulating film than a pixel TFT used in a pixel portion.

Further, in the pixel portion, a light-shielding film is provided below the pixel TFT, and a thick base film (first insulating film) is provided therebetween to prevent formation of a parasitic capacitance. Further, a storage capacitor having a large capacity is formed by selectively removing a base film in a portion serving as a storage capacitor and providing a thin dielectric (second insulating film) again.

According to the manufacturing process of this embodiment, the final active layer (semiconductor film) of the TFT is formed of a crystalline silicon film having a unique crystal structure having continuity in a crystal lattice. The features will be described below.

First, as a first feature, the crystalline silicon film formed in accordance with the manufacturing process of this embodiment has a plurality of needle-like or rod-like crystals (hereinafter, abbreviated as rod-like crystals) when viewed microscopically.
Have a crystal structure arranged in a row. This is TEM
(Transmission electron microscopy) can be easily confirmed.

As a second feature, electron diffraction is used.
When used, crystalline silicon formed according to the manufacturing process of this embodiment
On the surface of the film (portion where the channel is formed),
Although there is a slight shift, the orientation plane is {110}
You can check the surface. This is about the spot diameter
When observing an electron diffraction photograph of 1.35 μm,
Diffraction spots with a specific regularity appear on the 0 ° plane.
It is confirmed from. Each spot has a distribution on a concentric circle.
It is also confirmed that it is.

Further, as a third feature, the X-ray diffraction method (strict
X-ray diffraction method using the θ-2θ method).
When the ratio is calculated, the orientation ratio of the {220} plane is 0.7 or less.
Above (typically 0.85 or more)
I have. The method of calculating the orientation ratio is described in Japanese Patent Application Laid-Open No. 7-3213.
The technique described in Japanese Patent Publication No. 39 is used.

As a fourth feature, the present applicant has proposed that the crystal grain boundary formed by contacting individual rod-shaped crystals is HR-TEM
(High-resolution transmission electron microscopy) to confirm that the crystal lattice has continuity at the crystal grain boundaries. This can be easily confirmed from the fact that the observed lattice fringes are continuously connected at the crystal grain boundaries.

The continuity of the crystal lattice at the crystal grain boundaries is caused by the fact that the crystal grain boundaries are grain boundaries called “planar grain boundaries”. The definition of the planar grain boundary in this specification is `` Characterization of High-Efficiency Cast-Si
Solar Cell Wafers by MBICMeasurement; Ryuichi Shi
mokawa and Yutaka Hayashi, Japanese Journal of Appl
ied Physics vol.27, No.5, pp.751-758, 1988 ".

According to the above paper, the planar grain boundaries include twin grain boundaries, special stacking faults, special twist grain boundaries, and the like. This planar grain boundary is characterized by being electrically inactive. In other words, since it is a crystal grain boundary but does not function as a trap that hinders the movement of carriers, it can be considered that it does not substantially exist.

In particular, when the crystal axis (axis perpendicular to the crystal plane) is <11
In the case of the <0> axis, the {211} twin grain boundaries are also called corresponding grain boundaries of {3}. The Σ value is a parameter serving as a guideline indicating the degree of consistency of the corresponding grain boundaries, and it is known that the smaller the Σ value, the better the grain boundaries of consistency. For example, two
At the grain boundaries formed between the grains, the faces of both
If the orientation is {110}, it corresponds to the {111} plane
Assuming that the angle formed by the lattice fringes is θ, a pair of Σ3 when θ = 70.5 °
It is known to be a grain boundary.

The crystalline silicon film obtained by carrying out this embodiment is
Between the two crystal grains whose crystal axis is <110>.
Observation of the formed grain boundaries by HR-TEM shows that
Each lattice fringe of a crystal grain is continuous at an angle of about 70.5 °
There are many. Therefore, the grain boundary is the corresponding grain boundary of Σ3,
It can be inferred that this is a {211} twin grain boundary.

Such a crystal structure (accurately, a structure of a crystal grain boundary) indicates that two different crystal grains are bonded to each other with extremely high consistency at the crystal grain boundary. That is, the crystal lattice is continuously connected at the crystal grain boundary, and it is very difficult to form a trap level due to a crystal defect or the like. Therefore, a semiconductor thin film having such a crystal structure can be regarded as having substantially no crystal grain boundaries.

Further, a heat treatment step at a high temperature of 700 to 1150 ° C. (the thermal oxidation step in the present embodiment)
That defects existing in crystal grains is almost extinguished is confirmed by TEM observation by hits). This is apparent from the fact that the number of defects is significantly reduced before and after this heat treatment step.

The difference in the number of defects was determined by electron spin resonance analysis (El
ectron Spin Resonance (ESR) appears as a difference in spin density. At present, the spin density of the crystalline silicon film manufactured according to the manufacturing process of this embodiment is at least
5 × 10 ¹⁷ spins / cm ³ or less (preferably 3 × 10 ¹⁷ spins / cm ³
Below). However, since this measured value is close to the detection limit of existing measuring devices, the actual spin density is expected to be lower.

As described above, since the crystalline silicon film obtained by carrying out this embodiment has substantially no inside of the crystal grain and no crystal grain boundary, the single-crystal silicon film or the substantially single-crystal silicon Think of it as a membrane.

(Knowledge Regarding Electrical Characteristics of TFT) The TFT manufactured by using this embodiment exhibited electrical characteristics comparable to those of the MOSFET. TFT prototyped by the applicant (however,
The thickness of the active layer is 35 nm, and the thickness of the gate insulating film is 80 n.
The following data is obtained from m).

(1) The sub-threshold coefficient as an index of the switching performance (the agility of switching on / off operation) is 80 to 150 mV / decade (typically 100 to 120 mV) for both the N-channel TFT and the P-channel TFT. / decade
) And small. (2) The field effect mobility (μ _FE ) which is an index of the operation speed of the TFT is 150 to 650 cm ² / Vs for the N-channel TFT.
(Typically 200-500cm ² / Vs), P-channel TFT
100-300 cm ² / Vs (typically 120-200 cm ² / Vs). (3) The threshold voltage (V
_th ) is as small as -0.5 to 1.5 V for an N-channel TFT and -1.5 to 0.5 V for a P-channel TFT.

As described above, it has been confirmed that extremely excellent switching characteristics and high-speed operation characteristics can be realized.

[Embodiment 2] In this embodiment, a specific structure of a TFT and a structure of a TFT will be described with reference to FIG.

In the AM-LCD, the minimum required operating voltage (power supply voltage) differs depending on the circuit. For example, in a pixel portion, an operation voltage of 14 to 20 V is obtained in consideration of a voltage applied to liquid crystal and a voltage for driving a pixel TFT. Therefore, a TFT that can withstand such a high voltage must be used.

For a shift resist circuit used for a source driver circuit or a gate driver circuit, an operation voltage of about 5 to 10 V is sufficient. There is an advantage that the lower the operating voltage is, the more compatible with the external signal and the more the power consumption can be suppressed. However, the above-mentioned high breakdown voltage type TFT is not suitable for a circuit requiring a high speed operation such as a shift register circuit because the operation speed is sacrificed instead of having a good breakdown voltage characteristic.

As described above, the circuit formed on the substrate is:
Depending on the purpose, there is a circuit for obtaining a TFT that emphasizes the withstand voltage characteristic and a circuit for obtaining a TFT that emphasizes the operation speed.

FIG. 6 specifically shows the configuration of this embodiment. FIG. 6A is a block diagram of the AM-LCD viewed from above. Reference numeral 601 denotes a pixel unit. Each pixel includes a pixel TFT and a storage capacitor, and functions as an image display unit. 602a is a shift register circuit;
02b is a level shifter circuit, and 602c is a buffer circuit. The circuit composed of these forms a gate drive circuit as a whole.

In the AM-LCD shown in FIG. 6A, a gate drive circuit is provided so as to sandwich the pixel portion, and the gate drive circuits share the same gate wiring, that is, there is a failure in driving one of the gates. In this case, the redundancy can be provided such that a voltage can be applied to the gate wiring even if the occurrence of the error occurs.

Reference numeral 603a denotes a shift register circuit;
03b is a level shifter circuit, 603c is a buffer circuit, 6
03d is a sampling circuit, and a circuit composed of these forms a source drive circuit as a whole. A precharge circuit 60 is provided on the opposite side of the pixel portion from the source drive circuit.
4 are provided.

In the AM-LCD having such a configuration, the shift register circuits 602a and 603a are circuits for demanding high-speed operation, and the operating voltage is as low as 3.3 to 10 V (typically 3.3 to 5 V). High breakdown voltage characteristics are not particularly required. Therefore, the thickness of the gate insulating film is preferably as thin as 5 to 50 nm (preferably, 10 to 30 nm).

FIG. 6B is a schematic diagram of a CMOS circuit to be used mainly for a circuit requiring high-speed operation such as a shift register circuit or another signal processing circuit. In FIG. 6B, reference numeral 605a denotes a gate insulating film of an NTFT, and 605b denotes a gate insulating film of a PTFT, which are designed to be as thin as 5 to 50 nm (preferably, 10 to 30 nm).

The length of LDD region 606 is 0.1 to
0.5 μm (typically 0.2 to 0.3 μm) is preferred. If the operating voltage is sufficiently low, such as 2 to 3 V, the LDD region may not be provided.

Next, the CMOS circuit shown in FIG.
It is mainly suitable for the level shifter circuits 602b and 603b, the buffer circuits 602c and 603c, the sampling circuit 603d, and the precharge circuit 604. Since these circuits require a large current to flow, the operating voltage is as high as 14 to 16V. In particular, an operating voltage such as 19 V may be required on the gate drive side in some cases. Therefore, a TFT having very good withstand voltage characteristics (high withstand voltage characteristics) is required.

At this time, in the CMOS circuit shown in FIG. 6C, the gate insulating film 607a of the NTFT and the PTFT
Is designed to have a thickness of 50 to 200 nm (preferably 100 to 150 nm). In a circuit requiring such good withstand voltage characteristics, it is preferable that the gate insulating film be thicker than a TFT such as the shift register circuit illustrated in FIG.

The length of the LDD region 608 is 0.5 to
3 μm (typically 2 to 2.5 μm) is preferred. FIG.
Since the CMOS circuit shown in FIG. 3C receives a high voltage equivalent to that of a pixel like a buffer circuit or the like, it is preferable that the length of the LDD region is also equal to or close to that of the pixel.

Next, FIG. 6D is a schematic diagram of the pixel portion 601. The pixel TFT requires an operating voltage of 14 to 16 V because the voltage applied to the liquid crystal is also taken into account.
In addition, since the charge stored in the liquid crystal and the storage capacitor must be held for one frame period, the off-current must be as small as possible.

For this reason, in this embodiment, the NTF
The gate insulating film 609 has a double gate structure using T
Film thickness of 50 to 200 nm (preferably 100 to 150 n
m). This film thickness is the same as the CMO shown in FIG.
The film thickness may be the same as that of the S circuit, or may be different.

The thickness of the dielectric 610 of the storage capacitor is 5
The thickness may be up to 75 nm (preferably 20 to 50 nm).

The length of each of the LDD regions 611a and 611b is preferably 1 to 4 μm (typically, 2 to 3 μm). FIG.
Since a high voltage of 14 to 16 V is applied to the pixel TFT shown in (D), the length of the LDD region needs to be increased.

Since it is necessary to reduce the off current (drain current flowing when the TFT is in the off state) of the pixel TFT as much as possible, a region of the LDD regions 611a and 611b that does not overlap with the gate wiring (a normal LDD region) is used. It is desirable to secure an area (functioning as an area) of 1 to 3 μm.

As described above, even in the case of an AM-LCD, various circuits are provided on the same substrate, and the required operating voltage (power supply voltage) may differ depending on the circuit.
In this case, it is effective to arrange TFTs in which the thickness of the gate insulating film or the length of the LDD region differs between the driving circuit portion and the pixel portion as in the present invention.

It is effective to use the circuit shown in the first embodiment to realize the configuration of the present embodiment.

[Embodiment 3] In the embodiment 1, in the step of selectively removing the gate insulating film, it is desirable that the removal in the region to be the driving TFT is performed as shown in FIG.
7, reference numeral 701 denotes an active layer, 702 denotes an end of the gate insulating film 217, and 703 and 704 denote gate wires. As shown in FIG. 7, in a portion 705 where the gate wiring crosses over the active layer, it is desirable to leave a gate insulating film at an end of the active layer 701.

At the end of the active layer 701, a phenomenon called edge thinning occurs when a thermal oxidation step is performed later. This is a phenomenon in which the oxidation reaction proceeds so as to sunk under the edge of the active layer, and the edge becomes thinner and simultaneously rises upward. For this reason, when the edge thinning phenomenon occurs, there is a problem that the gate wiring is easily broken when the gate wiring gets over.

However, if the gate insulating film is removed so as to obtain the structure as shown in FIG. 7, the edge thinning phenomenon can be prevented in the portion 705 over which the gate wiring runs. Therefore, a problem such as disconnection of the gate wiring can be prevented beforehand. It is effective to use the configuration of the present embodiment for the first embodiment.

[Embodiment 4] In this embodiment, a structure in which a capacitance wiring formed simultaneously with a gate wiring is used as an electrode of a storage capacitor in an AM-LCD having the structure shown in FIG. 1 will be described with reference to FIG. .

In the case of the structure of FIG. 8, the first electrode 801 and the first
The dielectric 802 and the second electrode 803 form a first storage capacitor, and the second electrode 803, the second dielectric 804, and the third
The electrode 805 forms a second storage capacitor. At this time,
The second dielectric 804 is an extension of the gate insulating film, and the third electrode 805 is formed simultaneously with the gate wiring.

By connecting the two storage capacitors in parallel in this manner, a storage capacitor having a larger capacity can be realized. In this case, the first electrode 801 and the third electrode 80
5 may be set to a fixed potential. Both fixed potentials may be set to the same potential.

The structure of the present embodiment can be realized only by providing the third electrode in the first embodiment, and the configuration of the present embodiment and the configurations of the second and third embodiments may be combined in any manner. .

[Embodiment 5] In this embodiment, a TFT is formed on a substrate by the manufacturing process shown in Embodiment 1, and an AM-
A case where an LCD is manufactured will be described.

When the state shown in FIG. 5B is obtained, an alignment film is formed on the pixel electrode 265 to a thickness of 80 nm. Next, a color filter, a transparent electrode (counter electrode), and an alignment film are formed on a glass substrate as a counter substrate, and a rubbing process is performed on each alignment film to form a sealing material (sealing material). Then, the substrate on which the TFT is formed and the counter substrate are bonded to each other. Then, the liquid crystal is held in the meantime. Since a well-known means may be used for this cell assembling step, a detailed description is omitted.

Note that a spacer for maintaining the cell gap may be provided as needed. Therefore, when the cell gap can be maintained without the spacer as in the case of an AM-LCD having a diagonal of 1 inch or less, it is not necessary to particularly provide the cell gap.

Next, the AM-L manufactured as described above was used.
FIG. 10 shows the appearance of the CD. An active matrix substrate (refers to a substrate on which a TFT is formed) 11 has a pixel portion 1
2. Source drive circuit 13, gate drive circuit 14, signal processing circuit (signal division circuit, D / A converter circuit, gamma correction circuit, differential amplifier circuit, etc.) 15 are formed, and FPC (flexible print circuit) 16 is attached. Have been. In addition, 17 is a counter substrate.

This embodiment can be freely combined with any of the first to fourth embodiments.

[Embodiment 6] In this embodiment, a case where another means is used for forming a crystalline silicon film in Embodiment 1 will be described.

Specifically, the crystallization of an amorphous silicon film is disclosed in Japanese Patent Application Laid-Open No. Hei 7-130652 (US Patent No. 08/32).
9, 644) is used. According to the technique described in the publication, a catalyst element (typically, nickel) that promotes crystallization is selectively retained on the surface of an amorphous silicon film, and crystallization is performed using the portion as a seed for nucleus growth. Technology.

According to this technique, a specific directionality can be given to crystal growth, so that a crystalline silicon film having extremely high crystallinity can be formed.

In addition, the mask insulating film provided for selectively retaining the catalyst element can be used as it is as a mask for phosphorus added for gettering. By doing so, the number of steps can be reduced. This technique is described in detail in Japanese Patent Application Laid-Open No. Hei 10-247735 (corresponding to U.S. Application No. 09 / 034,041) by the present applicant.

The structure of this embodiment can be freely combined with any of the structures of the first to fifth embodiments.

[Embodiment 7] In this embodiment, an example in which a storage capacitor having a structure different from that of Embodiment 1 is formed is shown in FIG.
1 will be described. Specifically, an oxide film obtained by oxidizing a lower electrode of the storage capacitor is used as a dielectric of the storage capacitor.

First, a light-shielding film 21 and a lower electrode 22 of a storage capacitor are formed on a substrate. As the material, the same material as that described in Embodiment 1 can be used, but in the case of this embodiment, a material capable of forming a high-quality insulating film by oxidizing at least the upper surface is preferable.

In this embodiment, a laminated film having a three-layer structure of a silicon film / a tungsten film (or a tungsten silicide film) / a silicon film is used. In addition, a three-layer structure of a tantalum film / a tantalum nitride film / a tantalum film from the bottom is effective.

After the light-shielding film 21 and the lower electrode 22 of the storage capacitor are formed, oxide films 23 and 24 are formed on the surface by heat treatment, plasma treatment or anodic oxidation treatment. In the case of this embodiment, this oxide film is a silicon oxide film,
It is formed by heat treatment at 30 ° C. for 30 minutes. The oxide film 2
The conditions for forming the layers 3 and 24 may be appropriately selected depending on the required thickness and quality of the oxide film.

Thus, the storage capacitor of this embodiment is formed by the lower electrode 22 of the storage capacitor, the thermal oxide film (silicon oxide film) 24, and the upper electrode (semiconductor film) 25 of the storage capacitor.

When a three-layer structure of a tantalum film / a tantalum nitride film / a tantalum film is used from the lower layer as the lower electrode 22 of the storage capacitor, the formed oxide film 24 is a tantalum oxide film and has a very high relative dielectric constant. A dielectric having a modulus is obtained. Therefore, it is possible to secure a very large capacity even with a small area.

The present embodiment having the above-described configuration is similar to the first to third embodiments.
It can be freely combined with any of the sixth embodiment.

[Eighth Embodiment] In this embodiment, an example in which a storage capacitor having a structure different from that of the first embodiment is formed is shown in FIG.
2 will be described. Specifically, it is characterized in that a tantalum oxide film is used as a dielectric of the storage capacitor.

In FIG. 12, 26 is a light shielding film, 27 is a lower electrode of a storage capacitor, and 28 is a base film made of a silicon oxide film. These materials may be referred to Embodiment 1. In this embodiment, after an opening is provided in the base film 28, a tantalum oxide film 29 is formed by a sputtering method. The film thickness is 10-1
The thickness may be set to 00 nm (preferably 30 to 50 nm).

After the opening is provided, the exposed lower electrode 27 of the storage capacitor may be oxidized by heat treatment, plasma treatment or anodic oxidation treatment to form a tantalum oxide film.

After forming the tantalum oxide film 29 in this manner, a thin silicon oxide film 30 of about 10 nm and an upper electrode 31 of a storage capacitor are formed. At this time, it is desirable to form the silicon oxide film 30 and the amorphous silicon film (semiconductor film which will later become the upper electrode of the storage capacitor) continuously without opening to the atmosphere. This can prevent the lower surface of the active layer connected to the upper electrode of the storage capacitor from being contaminated with boron or the like in the atmosphere.

The silicon oxide film 30 serves as a barrier layer for preventing the tantalum oxide film 29 from interacting with the upper electrode 31 of the storage capacitor made of a semiconductor film (specifically, a silicon film). Play.

As described above, in the structure of this embodiment, the laminated film of the tantalum oxide film 29 and the silicon oxide film 30 is used as the dielectric of the storage capacitor. Also, the tantalum oxide film 29
Since the dielectric constant is as large as about 25, a sufficiently large capacity can be obtained even with a film thickness of about 100 nm. However, if it is made as thin as possible in consideration of the dielectric strength, 3
Preferably, the thickness is 0 to 50 nm.

The present embodiment having the above configuration is similar to Embodiments 1 to 3.
Any of the seventh embodiment can be freely combined.

[Embodiment 9] In this embodiment, an example in which a storage capacitor having a structure different from that of Embodiment 1 is formed is shown in FIG.
3 will be described. More specifically, an insulating film serving as an etching stopper is provided before the dielectric of the storage capacitor is formed.

In FIG. 13, reference numeral 32 denotes a light-shielding film, 33 denotes a lower electrode of a storage capacitor, and a 20 nm-thick tantalum oxide film 34 is formed to cover them. The material of the light shielding film 32 and the lower electrode 33 of the storage capacitor may be in accordance with the first embodiment. Also,
The tantalum oxide film may be obtained by oxidizing the lower electrode 33 of the storage capacitor, or may be formed by a sputtering method.

A base film 35 made of a silicon oxide film is formed thereon, and an opening is formed in base film 35. At this time,
Since the etching of the base film 35 is completely stopped by the tantalum oxide film 34, the electrode 33 thereunder is not etched, and the thickness of the opening of the tantalum oxide film 34 can be uniform.

After the opening is thus formed, a dielectric (silicon oxide film in this embodiment) 36 of the storage capacitor is formed thereon, and an upper electrode (semiconductor film) 37 of the storage capacitor may be formed thereon. .

In this embodiment, an example is shown in which a tantalum oxide film is used as an etching stopper and a silicon oxide film is used as a base film. However, a film having a sufficient etching selectivity (10 or more, preferably Is 100 or more), it is also possible to use another combination of insulating films.

For example, when a silicon oxide film is used as a base film, a silicon nitride film can be used as an etching stopper.

In this embodiment, after the opening is formed in the base film 35, the silicon oxide film is provided again as the dielectric of the storage capacitor. However, the dielectric of the storage capacitor is formed only by the tantalum oxide film used as the etching stopper. It can also be a body. However, in this case, it is desirable to provide a thin silicon oxide film as a barrier layer between the tantalum oxide film and the upper electrode of the storage capacitor made of a semiconductor film.

Of course, even when a silicon nitride film is used as an etching stopper, it is possible to use only the silicon nitride film as a dielectric for a storage capacitor without forming another dielectric.

The present embodiment having the above-described configuration is similar to the first to third embodiments.
Any of the embodiments of the eighth embodiment can be freely combined.

[Embodiment 10] Phosphorus was used to getter nickel (the catalyst element used to crystallize a silicon film) described in Embodiment 1, but in this embodiment, other elements were used. The case where nickel is gettered will be described.

First, according to the steps of the first embodiment, FIG.
(B) state is obtained. In FIG. 2B, reference numeral 208 denotes a crystalline silicon film. However, in this embodiment, the concentration of nickel used for crystallization is set as low as possible. Specifically, a layer containing 0.5 to 3 ppm by weight of nickel is formed on the amorphous silicon film, and a heat treatment for crystallization is performed.
The concentration of nickel contained in the crystalline silicon film thus formed is 1 × 10 ¹⁷ to 1 × 10 ¹⁹ atoms / cm ³ (typically 5 × 10 ¹⁷ to 1 × 10 ¹⁸ atoms / cm ³ ). Become.

After the formation of the crystalline silicon film, heat treatment is performed in an oxidizing atmosphere containing a halogen element. The temperature is 800 to 1150 ° C (preferably 900 to 1000 ° C)
And the processing time is 10 minutes to 4 hours (preferably 30 minutes to
1 hour).

In the present embodiment, three to three atmospheres
In an atmosphere containing 10% by volume of hydrogen chloride, 9
Heat treatment is performed at 50 ° C. for 30 minutes.

In this step, nickel in the crystalline silicon film becomes volatile nickel chloride and is released into the processing atmosphere. That is, nickel can be removed by the gettering action of the halogen element. However, if the concentration of nickel existing in the crystalline silicon film is too high, there is a problem that oxidation proceeds abnormally at the nickel segregation portion. Therefore, it is necessary to minimize the concentration of nickel used in the crystallization stage.

The structure of this embodiment can be freely combined with any structure of the first to ninth embodiments.

[Embodiment 11] In this embodiment, the case where the structures of the CMOS circuit and the pixel portion shown in Embodiment 1 are different will be described. Specifically, an example is shown in which the arrangement of the LDD regions is changed according to the specifications required by the circuit.

Since the basic structures of the CMOS circuit and the pixel portion have already been shown in FIG. 1, in the present embodiment, only the necessary portions will be denoted by reference numerals.

First, the circuit shown in FIG.
T is a CMOS circuit for a buffer circuit having a double gate structure and PTFT having a single gate structure. In this embodiment, the source-side LDD regions 41a and 41b are formed in a self-aligned manner using only the sidewalls as a mask, and the drain-side LDD regions 42a and 42b are formed using a resist mask. The feature is that the width (length) is larger than that of 41b.

CM used for drive circuit and signal processing circuit
Since an OS circuit is required to operate at high speed, it is necessary to eliminate as much as possible a resistance component that may cause a reduction in operation speed. However, since the LDD region necessary to increase the hot carrier resistance functions as a resistance component,
Operation speed is sacrificed.

However, the hot carrier injection occurs at the end of the channel formation region on the drain region side, and the LD overlaps the gate electrode with the gate insulating film interposed therebetween.
If there is a D region, hot carrier measures are sufficient. Therefore, it is not always necessary to provide an LDD region more than necessary at the end of the channel formation region on the source region side.

The structure shown in FIG. 14A cannot be applied to the case where an operation like a pixel TFT in which a source region and a drain region are exchanged is performed. In the case of a CMOS circuit, the source region and the drain region are usually fixed, so that a structure as shown in FIG. 14A can be realized.

With such a structure, the resistance component due to the LDD region on the source region side is eliminated, and with the double gate structure, an electric field applied between the source and drain is dispersed and relaxed.

Next, the structure of FIG. 14B is an embodiment of a pixel portion. In the case of the structure of FIG. 14B, the LDD region 43 is provided only on one side near the source region or the drain region.
a and 43b are provided. That is, the two channel forming regions 44
No LDD region is provided between a and 44b.

In the case of a pixel TFT, a source region and a drain region are frequently switched because an operation of repeating charging and discharging is performed. Therefore, the structure in FIG. 14B has a structure in which the LDD region is provided on the drain region side of the channel formation region, whichever becomes the drain region. Conversely, since there is no electric field concentration in the region between the channel forming regions 44a and 44b, eliminating the LDD region serving as a resistance component is effective for increasing the on-current (current flowing when the TFT is in the on-state). is there.

The structure of this embodiment can be freely combined with any of the structures of Embodiments 1 to 10.

[Embodiment 12] In this embodiment, an embodiment relating to a position where a storage capacitor is formed in a pixel portion will be described. FIGS. 15A and 15B are used for the description. Note that FIG. 15B is a cross-sectional view taken along line AA ′ of FIG. In addition, the same reference numerals are used for the same portions in FIGS.

In FIG. 15A, reference numeral 51 denotes a lower electrode of a storage capacitor formed simultaneously with the light shielding film, 52 denotes a semiconductor film,
53 is a gate wiring, 54 is a source wiring, and 55 is a drain wiring (drain electrode).

The lower electrode 51 of the storage capacitor is connected to the gate wiring 53
And below the source wiring 54,
It has a network (matrix) pattern shape.
That is, the entire lower electrode 51 of the storage capacitor has the same potential (preferably the lowest power supply potential).

A semiconductor film 52 is formed thereon via a base film 56 and an insulating film 57 serving as a dielectric of a storage capacitor.
In the storage capacitor portion, the base film 56 is removed, and the lower electrode 51 of the storage capacitor, the insulating film 57, and the semiconductor film 52 form a storage capacitor.

The present embodiment is characterized in that the storage capacitor portion is formed below the gate line 53 and below the source line 54. By doing so, the aperture ratio is improved, and a bright image can be displayed. Further, since light can be prevented from being applied to the storage capacitor, leakage of electric charge from the storage capacitor can be prevented.

In the present embodiment, the semiconductor film is patterned so that the pixel TFT has a triple gate structure. However, the present embodiment is not limited to this.

The structure of this embodiment is similar to those of the first to eleventh embodiments.
Can be freely combined with any of the embodiments.

[Embodiment 13] In this embodiment, an embodiment relating to a position where a storage capacitor is formed in a pixel portion will be described. 16A and 16B are used for the description. Note that FIG. 16B is a cross-sectional view of FIG. 16A taken along line AA ′. Also, the same reference numerals are used for the same portions in FIGS.

In FIG. 16A, reference numeral 61 denotes a lower electrode of a storage capacitor formed simultaneously with the light shielding film, 62 denotes a semiconductor film,
63 is a gate wiring, 64 is a source wiring, and 65 is a drain wiring (drain electrode).

The lower electrode 61 of the storage capacitor is connected to the source line 64
Are formed so as to be overlapped with each other, and have a mesh (matrix) pattern shape. That is, the entire lower electrode 61 of the storage capacitor has the same potential (preferably the lowest power supply potential).
It has become.

A semiconductor film 62 is formed thereon via a base film 66 and an insulating film 67 serving as a dielectric of a storage capacitor.
In the storage capacitor portion, the base film 66 is removed, and the lower electrode 61 of the storage capacitor, the insulating film 67, and the semiconductor film 62 form a storage capacitor.

The present embodiment is characterized in that this storage capacitor portion is formed below the source wiring 64. By doing so, the aperture ratio is improved, and a bright image can be displayed. Further, since light can be prevented from being applied to the storage capacitor, leakage of electric charge from the storage capacitor can be prevented.

In this embodiment, the semiconductor film is patterned so that the pixel TFT has a triple gate structure. However, the present embodiment is not limited to this.

The structure of this embodiment is similar to those of the first to eleventh embodiments.
Can be freely combined with any of the embodiments.

[Embodiment 14] In this embodiment, an embodiment relating to a position where a storage capacitor is formed in a pixel portion will be described. FIG. 17 is used for the description.

In FIG. 17, reference numeral 71 denotes a lower electrode of a storage capacitor; 72, a semiconductor film; 73a and 73b, gate wirings;
Denotes a source wiring, and 75 denotes a drain wiring.

The lower electrode 71 of the storage capacitor is connected to the gate wiring 73
A and 73b are formed so as to overlap below the source wiring 74, and have a mesh (matrix) pattern. That is, the entire lower electrode 71 of the storage capacitor has the same potential (preferably the lowest power supply potential).

On top of this, a semiconductor film 72 is formed via a base film and a dielectric for a storage capacitor. In the storage capacitor portion, the base film is removed, and the storage capacitor lower electrode 71, the storage capacitor dielectric, and the semiconductor film 72 form a storage capacitor.

The present embodiment is characterized in that the storage capacitor is formed below the second wiring 73b and below the source wiring 74. The difference from the twelfth and thirteenth embodiments is that, when a storage capacitor is formed below the gate wiring, the lower part of the gate wiring that is not selected (the gate wiring 73b next to the selected gate wiring 73a) is used.

In the case of the present embodiment, when charges are stored in the storage capacitor portion, the gate wiring thereon is not selected.
It is possible to prevent the charge accumulated in the storage capacitor from fluctuating due to the parasitic capacitance.

Further, by adopting such a structure, the aperture ratio is improved, and a bright image can be displayed. Further, since light can be prevented from being applied to the storage capacitor, leakage of electric charge from the storage capacitor can be prevented.

In the present embodiment, the semiconductor film is patterned so that the pixel TFT has a triple gate structure. However, the present embodiment is not limited to this.

The structure of this embodiment is similar to those of the first to eleventh embodiments.
Can be freely combined with any of the embodiments.

[Embodiment 15] This embodiment is different from the first embodiment.
An example in which the first interlayer insulating film is formed by a different method will be described.
I do. FIG. 18 is used for the description.

First, according to the manufacturing process of Example 1, FIG.
The steps up to the activation step shown in FIG. Next, 5
0-100 nm (70 nm in this embodiment) silicon nitride oxide
A base film (A) 1801 is formed, and 600 nm-1
μm (800 nm in this embodiment) silicon nitride oxide film
(B) 1802 is formed. Furthermore, resist on it
A mask 1803 is formed. (FIG. 18A)

Note that the silicon nitride oxide film (A) 1801
Nitrogen and acid contained in the silicon oxide film (B) 1802
The composition ratios of element, hydrogen and silicon are different. Silicon nitride oxide film
(A) 1801 is nitrogen 7%, oxygen 59%, hydrogen 2%, silicon
Silicon nitride oxide film (B) 1802
Is 33% nitrogen, 15% oxygen, 23% hydrogen, 29% silicon
Has become. Of course, it is not limited to this composition ratio.
No.

The resist mask 1803 has a large thickness.
Therefore, the surface of the silicon nitride oxide film (B) 1802
It can be completely flattened.

Next, a mixed gas of carbon tetrafluoride and oxygen is supplied.
The resist mask 180 is formed by the used dry etching method.
3 and the silicon nitride oxide film (B) 1802 are etched.
U. In the case of this embodiment, a mixed gas of carbon tetrafluoride and oxygen
Silicon nitride oxide film in dry etching using
(B) Etching of 1802 and resist mask 1803
The rates are almost equal.

By this etching step, FIG.
As shown, the resist mask 1803 is completely removed,
Part of the silicon nitride oxide film (B) 1802 (in this embodiment,
(From the surface to a depth of 300 nm). That
As a result, the flatness of the surface of the resist mask 1803 remains unchanged.
The surface of the etched silicon nitride oxide film (B) is flat
Will be reflected in the degree.

As described above, the first interlayer insulation having extremely high flatness is obtained.
A membrane 1804 is obtained. In the case of the present embodiment, the first interlayer insulating film 1
The film thickness of 804 is 500 nm. The subsequent steps are actually
Refer to the manufacturing process of Embodiment 1.

The structure of this embodiment is similar to that of the first to fourteenth embodiments.
Can be freely combined with any of the embodiments.
is there.

[0230] Example 16 The present invention is conventional MOSF
It is also possible to form an interlayer insulating film on the ET and use it when forming a TFT thereon. That is, it is also possible to realize a semiconductor device having a three-dimensional structure in which a reflective AM-LCD is formed on a semiconductor circuit.

Further, the semiconductor circuit is a SIMOX, Sm
art-Cut (registered trademark of SOITEC), ELTRAN
(A registered trademark of Canon Inc.) may be formed on an SOI substrate.

In implementing this embodiment, any of the configurations of Embodiments 1 to 14 may be combined.

[Embodiment 17] The present invention can also be applied to an active matrix EL display. An example is shown in FIG.

FIG. 19 is a circuit diagram of an active matrix type EL display. Reference numeral 81 denotes a display area, around which an X-direction (gate) drive circuit 82 and a Y-direction (source) drive circuit 83 are provided. Each pixel in the display area 81 has a switching TFT 84, a capacitor 85, a current control TFT 86, and an EL element 87, and the switching TFT 84 has an X direction (gate) signal line 88a (or 88b) and a Y direction (source). ) Signal line 8
9a (or 89b, 89c) is connected. The power supply lines 90a and 90b are connected to the current control TFT 86.

The switching TFT 84 has n channels.
No matter whether a tunnel type TFT or a p-channel type TFT is used,
good. The current control TFT 86 is an n-channel TF
T or p channel type TFT may be used, and
When a TFT is used, the cathode of the EL element 87 is
When a channel type TFT is used, it is connected to the anode of the EL element 87.
Continue. The EL element 87 and the current control TFT 86
It is also possible to provide a resistor or a TFT between them.

In the active matrix type EL display of this embodiment, the gate insulating films of the TFTs used in the X-direction driving circuit 82 and the Y-direction driving circuit 83 are thinner than the gate insulating films of the switching TFT 84 and the current controlling TFT 86. Has become. Further, the capacitor 85 is the first embodiment,
The storage capacitor has the structure described in 4, 7 to 9.

The active matrix EL display of this embodiment may be combined with any of the structures of Embodiments 1 to 16.

[Embodiment 18] In this embodiment, the present invention will be described.
EL (electroluminescence) display device using
An example will be described. Note that FIG.
FIG. 20B is a top view of the light emitting EL display device, and FIG.
It is sectional drawing.

In FIG. 20A, reference numeral 4001 denotes a substrate;
4002 is a pixel portion, 4003 is a source side driver circuit, 40
04 is a gate side drive circuit, and each drive circuit is
FPC (Flexible Print Server) via Wiring 4005
(Kit) 4006, and connected to an external device.

At this time, the pixel portion 4002 is driven by the source side.
Circuit 4003 and the gate side drive circuit 4004
First sealing material 4101, cover material 4102, filling
Material 4103 and a second sealing material 4104 are provided.
You.

FIG. 20 (B) shows FIG. 20 (A) as A-
This corresponds to a cross-sectional view cut along A ′,
Drive TFT included in the source-side drive circuit 4003 (however,
Here, an n-channel TFT and a p-channel TFT are shown.
Is shown. ) 4201 and the pixel portion 4002
Pixel TFT (However, here, the current to the EL element is controlled.
FIG. ) 4202 is formed
You.

In this embodiment, the driving TFT 4201 is
A TFT having the same structure as that of the first driving circuit is used. Also,
The pixel TFT 4202 has a TF having the same structure as the pixel portion of FIG.
T is used.

Driving TFT 4201 and Pixel TFT 420
An interlayer insulating film (flattening film) 43 made of a resin material is formed on
01 is formed, and a drain of the pixel TFT 4202 is formed thereon.
Pixel electrode (cathode) 4302 electrically connected to
Is done. As the pixel electrode 4302, a light-blocking conductive material
Film (typically containing aluminum, copper or silver as the main component)
Conductive film or a laminated film of them and another conductive film)
Can be. In this embodiment, an aluminum alloy is
Used as elementary electrodes.

An insulating film is formed on the pixel electrode 4302.
4303 is formed, and the insulating film 4303 is formed on the pixel electrode 430.
2, an opening is formed. In this opening
Therefore, an EL (electroluminescence) is formed on the pixel electrode 4302.
Layer 4304 is formed. The EL layer 4304
It is possible to use a known organic EL material or inorganic EL material.
it can. In addition, low molecular weight (monomer)
System) material and high polymer (polymer) material
May be used.

The method for forming the EL layer 4304 is based on a known technique.
You can use it. The structure of the EL layer is a hole injection layer,
Free transport layer, light emitting layer, electron transport layer or electron injection layer
A stacked structure or a single-layer structure may be used in combination.

On the EL layer 4304, a transparent conductive film is used.
An anode 4305 is formed. As the transparent conductive film, acid
Compound of indium oxide and tin oxide or indium oxide
And a compound of zinc oxide and zinc oxide. Also,
Moisture present at the interface between the anode 4305 and the EL layer 4304
It is desirable to exclude oxygen as much as possible. Therefore, vacuum
In either, the two layers are continuously formed, or the EL layer 4304 is
Is formed in a rare gas atmosphere and must not be exposed to oxygen or moisture.
In addition, a device such as formation of the anode 4305 is required.
In this embodiment, the multi-chamber method (cluster tool
The above-mentioned film formation is possible by using the film formation system of (method).
Noh.

The anode 4305 is indicated by 4306.
The region is electrically connected to the wiring 4005. wiring
4005 is a circuit for applying a predetermined voltage to the anode 4305.
A FPC 4006 via a conductive material 4307.
Is electrically connected to

As described above, the pixel electrode (cathode) 43
02, EL element composed of EL layer 4304 and anode 4305
A child is formed. This EL element has a first sealing material 410
Affixed to the substrate 4001 with the first and first sealing materials 4101
Surrounded by the joined cover material 4102, the filler 410
3 enclosed.

As the cover material 4102, a glass plate, F
RP (Fiberglass-Reinforced)
Plastics) plate, PVF (polyvinylfluoride)
D) Film, mylar film, polyester fill
Or an acrylic film. Real truth
In the case of the embodiment, the direction of light emission from the EL element is
A light-transmitting material is used in order to move toward 102.

However, the direction of light emission from the EL element is not
When going to the opposite side of the material, a translucent material must be used.
No need, metal plate (typically stainless steel plate), ceramic
Board or aluminum foil with PVF film
And sheets with a structure sandwiched between mylar films
Can be.

As the filler 4103, ultraviolet curing
Resin or thermosetting resin can be used,
(Vinyl chloride), acrylic, polyimide, epoxy
Resin, silicone resin, PVB (polyvinyl butyral)
Or EVA (ethylene vinyl acetate)
Can be The inside of the filler 4103 contains a hygroscopic substance.
Quality (preferably barium oxide) provided that the EL element
Degradation can be suppressed. In this embodiment, the EL element
Transparent material so that the light can pass through the filler 4103.
Is used.

[0252] The filler 4103 contains a spacer.
You may have. At this time, the spacer is made of barium oxide.
If formed, the spacer itself can be made hygroscopic
It is. When a spacer is provided,
Resin on anode 4305 as buffer layer to relieve pressure
It is also effective to provide a film.

Further, the wiring 4005 is formed of a conductive material 4305.
Is electrically connected to the FPC 4006 via the. Wiring 4
005 is a pixel portion 4002, a source side driver circuit 4003,
And the signal sent to the gate side drive circuit 4004 is FPC4
006, and the FPC4006 electrically connects to external devices.
Connected to.

Further, in this embodiment, the first sealing material 4101
To cover the exposed part of FPC400 and part of FPC4006.
The EL element is thoroughly shielded from the outside air
It has a structure to cut off. Thus, the cross section of FIG.
An EL display device having a structure is obtained. In addition, E of this embodiment
The L display device is any of the first to fourth or sixth to sixteenth embodiments.
May be combined with each other.

[Embodiment 19] In this embodiment, Embodiment 18 will be described.
The image which can be used for the pixel portion of the EL display device shown in FIG.
Examples of elementary structures are shown in FIGS. In addition, the real
In the embodiment, 4401 is a switching TFT 440.
Reference numeral 4403 denotes a switching TFT 443.
02, a gate wiring 4404, a current controlling TFT 44,
05 is a capacitor, 4406 and 4408 are current supply lines,
Reference numeral 4407 denotes an EL element.

FIG. 21A shows the current supply between two pixels.
This is an example in which the line 4406 is shared. That is, two
So that the pixel is line-symmetric about the current supply line 4406
The feature is that it is formed. In this case, the power supply line
The pixel part can be reduced
It can be thinned.

FIG. 21B shows the current supply line 440.
8 is provided in parallel with the gate wiring 4403.
You. Note that in FIG. 21B, the current supply line 4408 and the gate are connected.
Wiring 4403 is provided so as not to overlap.
However, if both are formed on different layers,
They can be provided so as to overlap with each other via an insulating film. this
In this case, the power supply line 4408 and the gate wiring 4403 are exclusively used.
Since the area can be shared, the pixel section
High definition can be achieved.

FIG. 21 (C) shows the structure of FIG. 21 (B).
Current supply line 4408 and gate line 4403
In parallel, two pixels are connected to a current supply line 4408.
It is characterized in that it is formed so as to be line-symmetric with respect to.
Further, the current supply line 4408 is connected to any of the gate lines 4403.
It is also effective to provide them so as to overlap one of them. this
In this case, the number of power supply lines can be reduced.
The element portion can be further refined.

[Embodiment 20] The electro-optical device of the present invention,
Specifically, a nematic liquid crystal is used in the liquid crystal display device of the present invention.
In addition, various liquid crystals can be used. example
See, 1998, SID, "Characteristics and Driving Scheme
 of Polymer-Stabilized Monostable FLCD Exhibiting
Fast Response Time and High Contrast Ratio with Gr
ay-Scale Capability "by H. Furue et al., 1997, S
ID DIGEST, 841, "A Full-Color Thresholdless Antife
rroelectric LCD Exhibiting Wide Viewing Angle with
 Fast Response Time "by T. Yoshida et al., 1996,
 J. Mater. Chem. 6 (4), 671-673, "Thresholdless ant
iferroelectricity in liquid crystals and its appli
cation to displays "by S. Inui et al. and US patents
It is possible to use the liquid crystal disclosed in US Pat.
You.

Further, the isotropic phase-cholesteric phase-kaira
Ferroelectric liquid crystal (FL)
C), using a DC voltage while applying a cholesteric phase
A chiral smectic phase transition and
Of the monostable FLC with the edge almost aligned with the rubbing direction.
FIG. 22 shows the aero-optical characteristics.

A table using a ferroelectric liquid crystal as shown in FIG.
The display mode is called “Half-V switching mode”.
Have been broken. The vertical axis of the graph shown in FIG.
Unit) and the horizontal axis is the applied voltage. "Half-V Sui
"Tching mode" is described in Terada et al.'S "Half-V
Character switching mode FLCD ”, 46th Applied Physics
Preliminary Proceedings of the Related Alliance Lecture Meeting, March 1999, 131st
Page 6, and Yoshihara et al., "Time-Division Full Using Ferroelectric Liquid Crystals"
Color LCD ”, Liquid Crystal Vol. 3, No. 3, page 190
No.

[0262] As shown in FIG.
Low voltage driving and gradation display are possible by using an electrically mixed liquid crystal.
You can see that it works. The liquid crystal display device of the present invention includes:
A ferroelectric liquid crystal exhibiting such electro-optical characteristics should also be used.
Can be.

Further, an antiferroelectric phase is exhibited in a certain temperature range.
The liquid crystal is called an antiferroelectric liquid crystal (AFLC). Antiferroelectric
The transmittance of a mixed liquid crystal with a transparent liquid crystal is
Thresholdless threshold voltage with continuously changing electro-optical response characteristics
There is a so-called ferroelectric mixed liquid crystal. This no threshold
Value antiferroelectric mixed liquid crystal is a so-called V-shaped electro-optical
Response voltage, and its driving voltage is about ± 2.5V
(About 1 μm to 2 μm in cell thickness)
You.

In general, thresholdless antiferroelectric mixing
The liquid crystal has a large spontaneous polarization and a high dielectric constant of the liquid crystal itself. This
Thresholdless antiferroelectric mixed liquid crystal for liquid crystal display
Pixel requires a relatively large storage capacity
It becomes. Therefore, the thresholdless anti-threshold with small spontaneous polarization
It is preferable to use a ferroelectric mixed liquid crystal.

Note that such a thresholdless antiferroelectric mixture
By using the combined liquid crystal for the liquid crystal display device of the present invention,
Low-voltage driving realizes low power consumption.
You.

The liquid crystal shown in this embodiment is the same as that of the first to third embodiments.
16 for a liquid crystal display device having any of the above configurations.
Is possible.

[Embodiment 21] The electro-optical device of the present invention and
Semiconductor circuits are used as display units and signal processing circuits for electrical appliances.
Can be. Such appliances include bidets
Camera, digital camera, projector, project
Action TV, goggle type display (head mounted
Display), navigation system, sound reproduction
Equipment, notebook personal computers, game machines,
Personal digital assistants (mobile computers, mobile phones, mobile
Type game machine or electronic book, etc.), images with recording media
A reproduction device is exemplified. Examples of these appliances
As shown in FIGS.

FIG. 23 (A) shows a mobile phone,
01, audio output unit 2002, audio input unit 2003, display
Unit 2004, operation switch 2005, antenna 2006
It is composed of The electro-optical device according to the present invention includes the display unit 200.
4, the semiconductor circuit according to the present invention includes an audio output unit 2002,
Use as voice input unit 2003 or CPU or memory
Can be.

FIG. 23B shows a video camera,
2101, display unit 2102, voice input unit 2103, operation
Switch 2104, battery 2105, image receiving unit 210
6. The electro-optical device according to the present invention has a display unit 21.
02, the semiconductor circuit of the present invention includes the audio input unit 2103
Alternatively, it can be used for a CPU, a memory, and the like.

FIG. 23C shows a mobile computer (mode).
-Building computer), main body 2201, camera unit
2202, image receiving unit 2203, operation switch 2204, table
And a display unit 2205. The electro-optical device of the present invention is
The display portion 2205 displays the semiconductor circuit of the present invention on a CPU or a memory.
It can be used for moly and the like.

FIG. 23D shows a goggle type display.
Yes, body 2301, display unit 2302, arm unit 230
3 The electro-optical device according to the present invention has a display unit 23.
02, the semiconductor circuit of the present invention is used for a CPU, a memory, and the like.
Can be.

FIG. 23E shows a rear projector (pro
Injection TV), a main body 2401, a light source 240
2, liquid crystal display device 2403, polarizing beam splitter 24
04, reflectors 2405, 2406, screen 2
407. The present invention is applied to a liquid crystal display device 2403.
The semiconductor circuit of the present invention can be used for a CPU or a memory.
It can be used for moly and the like.

FIG. 23F shows a front projector.
Yes, body 2501, light source 2502, liquid crystal display device 25
03, an optical system 2504, and a screen 2505
You. The present invention can be used for the liquid crystal display device 2502.
The semiconductor circuit of the present invention is used for a CPU, a memory, and the like.
be able to.

FIG. 24A shows a personal computer.
Yes, main body 2601, video input unit 2602, display unit 26
03, a keyboard 2604, and the like. Electric light of the present invention
Display device 2603, the semiconductor circuit of the present invention is C
It can be used for PUs and memories.

FIG. 24B shows an electronic game machine (game machine).
Unit), a main body 2701, a recording medium 2702, a display unit
2703 and a controller 2704. This electron
The audio and video output from the gaming device are
Reproduced on the display including the display unit 2706
You. Communication between the controller 2704 and the main unit 2701
Communication means or between the electronic gaming device and the display
Communication means can be wired, wireless or optical
You. In this embodiment, infrared rays are transmitted to the sensor units 2707 and 2708.
It is configured to detect by. Electro-optical device of the present invention
Indicates the semiconductor circuit of the present invention in the display portions 2703 and 2706.
Can be used for a CPU, a memory, and the like.

FIG. 24C shows the recording of the program.
Media (hereinafter referred to as a recording medium).
Image reproducing device), a main body 2801, a display portion 2802,
The speaker unit 2803, the recording medium 2804, and the operation switch
H2805. This image reproducing apparatus is a recording medium.
DVD (Digital VersatileD)
isc), CD, etc., to enjoy music, movies, games
And can do the Internet. Electricity of the present invention
The optical device is used for the display portion 2802, the CPU, the memory, and the like.
be able to.

FIG. 24D shows a digital camera,
Body 2901, display 2902, eyepiece 2903,
The switch 2904 includes an image receiving unit (not shown). Invention of the present application
Electro-optical device is used for the display unit 2902, CPU, memory, etc.
Can be used.

The rear projector shown in FIG.
Or for the front projector of FIG. 23 (F)
FIG. 25 shows a detailed description of the optical engine that can be used.
Show. FIG. 25A shows an optical engine, and FIG.
5 (B) is a light source optical system built in the optical engine.
You.

The optical engine shown in FIG.
Optical system 3001, mirrors 3002, 3005-300
7, dichroic mirrors 3003, 3004, optical
Lenses 3008a to 3008c, prism 3011, liquid crystal display
The display device 3010 includes a projection optical system 3012. Projection optics
The system 3012 is an optical system including a projection lens. Real truth
The embodiment is an example of a three-plate type using three liquid crystal display devices 3010.
However, a single plate type may be used. FIG. 25
In the optical path indicated by the arrow in (A), an optical lens,
Film with polarizing function, film for adjusting retardation
A film or an IR film may be provided.

Further, as shown in FIG.
Science 3001 is composed of light sources 3013 and 3014, synthetic prism
3015, collimator lenses 3016 and 3020,
Arrays 3017, 3018, polarization conversion element 3019
including. Note that the light source optical system shown in FIG.
Although two were used, one may be used or three or more may be used.
No. Also, somewhere in the optical path of the light source optical system, an optical lens,
Film with polarization function, film to adjust retardation
Alternatively, an IR film or the like may be provided.

As described above, the applicable range of the present invention is extremely
Widely applicable to all kinds of electric appliances
is there. Moreover, the electric appliance of this embodiment is the
Can be realized by using a configuration consisting of
Can be.

[0282]

According to the present invention, on the same substrate,
TFTs having gate insulating films with different thicknesses can be formed. Therefore, in an electro-optical device typified by an AM-LCD or a semiconductor device including an electric appliance having such an electro-optical device as a display unit, a circuit having an appropriate performance should be arranged according to a specification required by the circuit. And the performance and reliability of the semiconductor device can be significantly improved.

Further, in the pixel portion of the electro-optical device, the dielectric of the storage capacitor can be made thin, and a storage capacitor having a large area and a large capacity can be formed. Further, the storage capacitor can be hidden below the gate wiring and the source wiring. Therefore, even in an electro-optical device having a diagonal width of 1 inch or less, it is possible to secure a sufficient storage capacity without reducing the aperture ratio.

[Brief description of the drawings]

FIG. 1 is a diagram showing a cross-sectional structure of an AM-LCD.

FIG. 2 is a diagram showing a manufacturing process of an AM-LCD.

FIG. 3 is a view showing a manufacturing process of an AM-LCD.

FIG. 4 is a diagram showing a manufacturing process of an AM-LCD.

FIG. 5 is a diagram showing a manufacturing process of an AM-LCD.

FIG. 6 is a diagram showing a block diagram and a circuit arrangement of an AM-LCD.

FIG. 7 is a diagram showing a structure of a driving TFT (CMOS circuit).

FIG. 8 is a diagram showing a cross-sectional structure of an AM-LCD.

FIG. 9 is a diagram showing a relationship between concentration distributions when an impurity element is added.

FIG. 10 is a diagram showing an appearance of an AM-LCD.

FIG. 11 is a diagram showing a cross-sectional structure of an AM-LCD.

FIG. 12 is a diagram showing a cross-sectional structure of an AM-LCD.

FIG. 13 is a diagram showing a cross-sectional structure of an AM-LCD.

FIG. 14 illustrates a cross-sectional structure of a driver circuit and a pixel portion.

FIG. 15 illustrates a top structure of a pixel portion.

FIG. 16 is a diagram illustrating a top structure of a pixel portion.

FIG. 17 illustrates a top structure of a pixel portion.

FIG. 18 is a diagram showing a manufacturing process of an AM-LCD.

FIG. 19 illustrates a circuit configuration of an EL display device.

FIG. 20 illustrates a top structure and a cross-sectional structure of an EL display device.

FIG. 21 illustrates a structure of a pixel portion of an EL display device.

FIG. 22 is a diagram showing optical response characteristics of a liquid crystal.

FIG. 23 illustrates an example of an electric appliance.

FIG. 24 illustrates an example of an electric appliance.

FIG. 25 is a diagram showing a configuration of an optical engine.

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification FI FI Theme Court II (Reference) H01L 29/78 617S (72) Inventor Kenji 398 Hase, Atsugi-shi, Kanagawa Pref.

Claims (13)

[Claims] 1. Each pixel has a pixel TFT and a storage capacitor.
In a semiconductor device including a pixel portion, The active layer of the pixel TFT is laminated in at least two layers.
Formed above the light-shielding film with the insulating film interposed therebetween, The storage capacitor is formed by an electric current formed in the same layer as the light shielding film.
Same as the pole, dielectric and drain region of the pixel TFT
Formed of a semiconductor film having a composition The dielectric is an insulation layered in at least two layers.
A semiconductor device comprising a partial layer of a film. 2. Each pixel has a pixel TFT and a storage capacitor.
In a semiconductor device including a pixel portion, The active layer of the pixel TFT is laminated in at least two layers.
Formed above the light-shielding film with the insulating film interposed therebetween, The storage capacitor is formed by an electric current formed in the same layer as the light shielding film.
Same as the pole, dielectric and drain region of the pixel TFT
Formed of a semiconductor film having a composition The dielectric is an insulation layered in at least two layers.
It is characterized by consisting of the remaining layer after removing some layers of the film
Semiconductor device. 3. Each pixel has a pixel TFT and a storage capacitor.
In a semiconductor device including a pixel portion, The active layer of the pixel TFT is a first insulating film in contact with the light-shielding film.
And on a light shielding film with a second insulating film in contact with the active layer interposed therebetween.
Formed towards The storage capacitor is formed by an electric current formed in the same layer as the light shielding film.
A pole, the second insulating film, and a drain region of the pixel TFT
Characterized by being formed of a semiconductor film having the same composition as
Semiconductor device. 4. The film thickness of the second insulating film according to claim 3,
Is a laminated film composed of the first insulating film and the second insulating film.
Semiconductor device characterized in that the thickness is 1/5 or less of the film thickness
Place. 5. The method according to claim 1, wherein:
The semiconductor device has a drive circuit unit and the
Having a pixel portion, Of the gate insulating film of the driving TFT included in the driving circuit portion
The film thickness is smaller than the film thickness of the gate insulating film of the pixel TFT
A semiconductor device characterized by the above-mentioned. 6. The gate TFT of claim 5, wherein
The drive TF has a thickness of 50 to 200 nm.
The gate insulating film of T has a thickness of 5 to 50 nm.
Semiconductor device. 7. The method according to claim 1, wherein:
And an EL element is electrically connected to the pixel TFT.
An EL display device, comprising: 8. The method according to claim 1, wherein
Characterized in that the semiconductor device is used as a display unit.
Electrical appliances. 9. Each pixel has a pixel TFT and a storage capacitor.
A method for manufacturing a semiconductor device including a pixel portion, A light-shielding film and an electrode made of the same material as the light-shielding film on a substrate
Forming a; Forming a first insulating film covering the light shielding film and the electrode;
Process and Etching the first insulating film to form an opening on the electrode;
Forming a; Forming a second insulating film covering the first insulating film and the opening;
The process of Forming a semiconductor film on the second insulating film; A method for manufacturing a semiconductor device, comprising: 10. A driving circuit and a pixel TFT for each pixel.
Of a semiconductor device including a pixel portion having a capacitor and a storage capacitor
And A light-shielding film and an electrode made of the same material as the light-shielding film on a substrate
Forming a; Forming a first insulating film covering the light shielding film and the electrode;
Process and Etching the first insulating film to form an opening on the electrode;
Forming a; Forming a second insulating film covering the first insulating film and the opening;
The process of Forming a semiconductor film on the second insulating film; Forming a gate insulating film covering the semiconductor film; A part of the gate insulating film is etched, and the driving circuit
Exposed part of the semiconductor film and part of the semiconductor film of the pixel part
And the process of By etching the gate insulating film by thermal oxidation
Forming a thermal oxide film on the exposed surface of the semiconductor film
When, A method for manufacturing a semiconductor device, comprising: 11. A driving circuit unit and a pixel TFT for each pixel.
Of a semiconductor device including a pixel portion having a capacitor and a storage capacitor
And A light-shielding film and an electrode made of the same material as the light-shielding film on a substrate
Forming a; Forming a first insulating film covering the light shielding film and the electrode;
Process and Etching the first insulating film to form an opening on the electrode;
Forming a; Forming a second insulating film covering the first insulating film and the opening;
The process of Forming a semiconductor film on the second insulating film; Forming a gate insulating film covering the semiconductor film; A part of the gate insulating film is etched, and the driving circuit
Exposed part of the semiconductor film and part of the semiconductor film of the pixel part
And the process of By etching the gate insulating film by thermal oxidation
Forming a thermal oxide film on the exposed surface of the semiconductor film
When, In the semiconductor film of the drive circuit portion and the semiconductor film of the pixel portion,
Forming an LDD region; The length of the LDD region differs between the driving circuit portion and the pixel portion.
A method for manufacturing a semiconductor device, comprising: 12. The method according to claim 10, wherein
The interface between the second insulating film and the semiconductor film is not open to the atmosphere.
A method for manufacturing a semiconductor device. 13. The method according to claim 10, wherein
The thickness of the second insulating film is determined by the first insulating film
The thickness of the laminated film composed of the edge film should be set to 1/5 or less
A method for manufacturing a semiconductor device.