JP6068767B2 - Semiconductor device - Google Patents

Description

The present invention relates to a semiconductor device having a circuit formed of a thin film transistor (hereinafter referred to as TFT) and a manufacturing method thereof. In particular, the present invention relates to an electro-optical device typified by a liquid crystal display device, a semiconductor device in which such an electro-optical device is mounted as a component, and a manufacturing method thereof. Note that in this specification, a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics, and an electro-optical device, a semiconductor circuit, and an electronic device are all semiconductor devices.

In recent years, a thin film (thickness of about several to several hundred nm) formed on a substrate having an insulating surface is used for T
Development of a semiconductor device having an FT and having a large-area integrated circuit formed of the TFT is in progress. As typical examples, an active matrix liquid crystal display device and a light emitting device are known. In particular, a TFT having a crystalline silicon film as an active region has high field effect mobility, and thus various functional circuits can be formed.

For example, in an active matrix liquid crystal display device, a pixel circuit that displays an image for each functional block, or a pixel circuit such as a shift register circuit based on a CMOS circuit, a level shifter circuit, a buffer circuit, or a sampling circuit is controlled. Are formed on a single substrate.

The TFT includes at least a semiconductor film, an insulating film made of a silicon oxide film, a silicon oxynitride film, or the like, and wiring made of various metal materials. Examples of the wiring include a source wiring and a gate wiring (including a gate electrode). Since the thickness of these films is about several to several hundred nm, it can be said to be a thin film.

These thin films are formed by a known film forming technique such as CVD (chemical vapor deposition) or sputtering. However, it is known that the thin film has internal stress. The internal stress includes intrinsic stress and thermal stress resulting from the difference in thermal expansion coefficient between the thin film and the substrate.

The effect of thermal stress can be ignored by considering the substrate material, process temperature, pressure, etc., but the mechanism of generation of intrinsic stress is not necessarily clear, rather the film growth process and It is considered that the phase change and composition change due to subsequent heat treatment and the like are complicatedly entangled.

Generally, the internal stress includes a compressive stress and a tensile stress. As shown in FIG.
When the thin film 311 is to be stretched, the substrate 312 is compressed and formed with the thin film 311 facing outside, and this is called compressive stress. On the other hand, as shown in FIG. 5B, when the thin film 311 is about to contract with respect to the substrate 312, the substrate 312 is deformed with the thin film inside because the substrate 312 is pulled in a direction to prevent it, and this is called tensile stress. It is out. In general, the value of tensile stress is often indicated by +, and the value of compressive stress is often indicated by-.

Regarding the influence of such internal stress on the electrical characteristics of the transistor, for example, “0
. Influence of stress of etch stop nitride film on 13 μm CMOS transistor performance; 25 Special Issue on ULSI Devices (200
1) pp 36-39 ". According to this, it has been reported that the mobility of the NMOS transistor is improved when the channel formation region is subjected to tensile stress, and the mobility is improved when the PMOS transistor is subjected to compressive stress.

As described above, the TFT wiring is also formed of a thin film. Therefore, the wiring also has internal stress, and peeling may occur when the internal stress is strong.
Further, the gate electrode formed of the same material as the wiring is formed on the semiconductor film with an insulating film interposed therebetween. The internal stress of the gate electrode acts on the semiconductor film, and the electric field represented by the threshold voltage and the field effect mobility is applied to the interface between the insulating film and the semiconductor film and by distorting the semiconductor film. May adversely affect physical properties.

The present invention is a technique for solving such a problem, and in an electro-optical device and a semiconductor device typified by an active matrix liquid crystal display device having wiring, the operating characteristics and reliability of the semiconductor device are improved. The goal is to improve yield.

The present invention makes it possible to control the wiring to a desired internal stress by introducing an impurity element into the TFT wiring or by performing both the impurity element introduction and heat treatment. In particular, the present invention
Application to the gate electrode is extremely effective. Further, an impurity element can be introduced only in a desired region, or heat treatment can be performed to control a desired internal stress.

For example, by applying the present invention, a stress applied to a channel formation region in an n-channel TFT can be referred to as a tensile stress, and a stress applied to a channel formation region in a p-channel TFT can be referred to as a compressive stress. Further, the channel formation region in the n-channel TFT has a stronger tensile stress than the channel formation region in the p-channel TFT, and the channel formation region in the p-channel TFT has an n-channel type. TFT
It is also possible to make the compressive stress relatively stronger than the channel formation region. In this way, the electrical characteristics of the TFT can be improved, and the operating characteristics of the semiconductor device can be greatly improved.

As a method for introducing the impurity element, a plasma doping method, an ion implantation method, an ion shower doping method, or the like may be used. In such a method for introducing an impurity element, the energy of ions implanted into the thin film is very large compared to the binding energy of the elements forming the thin film. Therefore, the ions that are implanted into the thin film may be present at the lattice position by blowing off the atoms that form the semiconductor film from the lattice points, or the ions that are implanted or atoms that are ejected from the lattice points may be located at the interstitial positions. To come to exist. Since the thin film stretches in this way, the compressive stress increases when the thin film has compressive stress, and the tensile stress is relaxed when the thin film has tensile stress.

In addition, since the atoms present at the interstitial positions return to the lattice positions by the heat treatment, the regularity of the arrangement of atoms is improved. Therefore, since the thin film contracts, the tensile stress increases when the thin film has tensile stress, and the compressive stress is relaxed when the thin film has compressive stress.

Further, when the impurity element is introduced after the heat treatment, accelerated ions are implanted into the film with improved regularity of atomic arrangement, so that the ions do not collide along the gap of the crystal lattice. It is possible to enter deeper. (Channeling) Therefore,
In the introduction of impurity elements to control internal stress, the dose amount is small, and
It is possible to carry out with a low acceleration voltage.

In addition, when the heat treatment is performed after introducing the impurity element, more atoms are introduced into the thin film than the atoms that form the thin film, so that the atoms that existed at the interstitial position return more than the lattice position. There will be atoms. Therefore, since the shrinkage of the thin film is smaller than when no impurity element is introduced, the increase in tensile stress is also small. That is, if it is known that heat treatment is performed in a later process, the amount of change in internal stress can be reduced by introducing an impurity element in advance.

As described above, it is possible to control to a desired internal stress by introducing the impurity element or both the impurity element introduction and the heat treatment. Of course, the introduction of impurities and the heat treatment are not limited to one time but may be performed a plurality of times. The present invention improves the operating characteristics and reliability of the semiconductor device by applying these characteristics to the wiring and controlling the stress of the wiring. In particular, the stress applied to the semiconductor film can be controlled by controlling the internal stress in the gate electrode of the TFT. Therefore, it is possible to improve electrical characteristics represented by threshold voltage and field effect mobility. In addition, since the stress of each gate electrode can be controlled, variation in electrical characteristics can be suppressed.

The manufacturing method of the present invention disclosed in this specification is characterized in that an impurity element is introduced into a conductive film so that an internal stress in the conductive film is ± 1 GPa or less.

Another manufacturing method of the present invention is characterized in that an impurity element is introduced into a conductive film and heat treatment is performed on the conductive film so that an internal stress in the conductive film is ± 1 GPa or less.

Another manufacturing method of the present invention is characterized in that a heat treatment is performed on the conductive film, an impurity element is introduced into the conductive film, and an internal stress in the conductive film is set to ± 1 GPa or less.

In each of the above manufacturing methods, the impurity element can be introduced by a plasma doping method, an ion implantation method, an ion shower doping method, or the like.

In each of the above manufacturing methods, the impurity element is not particularly limited, but may be one or more elements selected from an impurity element imparting n-type, an impurity element imparting p-type, and a rare gas element. It is desirable. An impurity element imparting n-type conductivity or an impurity element imparting p-type conductivity is an impurity element indispensable for forming a source region and a drain region. Therefore, it is economical because it is not necessary to prepare another impurity element. In particular, when an impurity element is introduced into the gate electrode, the impurity element can be introduced at the same time as the step of introducing the impurity element into the source region and the drain region. Further, since the rare gas element is an inert element, it is preferable because it does not affect the electrical characteristics of the TFT.

In addition, as the amount of the impurity element introduced is larger, the internal stress in the thin film is a compressive stress, and the compressive stress is increased.If the internal stress in the thin film is a tensile stress, the tensile stress is relaxed, It may have compressive stress. That is, depending on the amount of impurity element introduced, the internal stress in the thin film may be a compressive stress or a tensile stress.

In each of the above manufacturing methods, the value of internal stress in the conductive film is preferably ± 1 GPa or less. It is known that peeling is generated when the internal stress of the conductive film is strong, and generally a standard capable of suppressing the occurrence of peeling is ± 1 GPa or less. Of course, the occurrence of peeling greatly affects the conditions under which the conductive film is formed.

In each of the above manufacturing methods, the conductive film is not limited to a single layer and may have a stacked structure of two or more layers.

In each of the above manufacturing methods, an RTA method, a laser annealing method, a thermal annealing method using a furnace annealing furnace, or the like can be applied as the heat treatment.

The heat treatment greatly affects the change of internal stress in the thin film depending on time and temperature. The longer the heat treatment time and the higher the heat treatment temperature, the higher the tensile stress when the internal stress in the thin film is a tensile stress, and the lower the compressive stress when the internal stress in the thin film is a compressive stress. After relaxation, it may have tensile stress. That is, depending on the heat treatment conditions, the internal stress in the thin film may be a compressive stress or a tensile stress.

  Moreover, the structure of this invention is shown below.

A semiconductor device having an n-channel TFT, wherein the n-channel TFT has a semiconductor film and a conductive film, the semiconductor film is subjected to tensile stress, and an impurity element is introduced into the conductive film It is characterized by.

A semiconductor device having a p-channel TFT, wherein the p-channel TFT has a semiconductor film and a conductive film, the semiconductor film is subjected to compressive stress, and an impurity element is introduced into the conductive film It is characterized by.

A semiconductor device having an n-channel TFT and a p-channel TFT, wherein the n-channel TFT includes a first semiconductor film and a first conductive film formed on the first semiconductor film. The p-channel TFT includes a second semiconductor film and a second conductive film formed on the second semiconductor film, and the first semiconductor film receives a tensile stress. The second
The semiconductor film is subjected to compressive stress, and an impurity element is introduced into the first conductive film and the second conductive film.

In each of the above structures, the impurity element is not particularly limited, but is preferably one or more elements selected from an impurity element imparting n-type, an impurity element imparting p-type, and a rare gas element. . An impurity element imparting n-type conductivity or an impurity element imparting p-type conductivity is an impurity element indispensable for forming a source region and a drain region. Therefore, it is economical because it is not necessary to prepare another impurity element. In particular, when an impurity element is introduced into the gate electrode, the impurity element can be introduced at the same time as the step of introducing the impurity element into the source region and the drain region. Further, since the rare gas element is an inert element, it is preferable because it does not affect the electrical characteristics of the TFT.

In addition, a semiconductor device typified by a liquid crystal display device or a light-emitting device is formed using a TFT having the above-described structures.

By adopting the configuration of the present invention, the following basic significance can be obtained.
(A) It is a simple method adapted to the conventional manufacturing process.
(B) The formation of wiring having a desired internal stress can be realized. Therefore, stress in other films can be reduced. In addition, the patterning process of the wiring can be performed well.
(C) In a semiconductor device typified by an active matrix liquid crystal display device, the operating characteristics and reliability of the semiconductor device can be improved and the yield can be improved while satisfying the above advantages.

The figure which shows an example of the concept of this invention. The figure which shows an example of the concept of this invention. The figure which shows the example of the variation | change_quantity to the direction of the compressive stress by introduction | transduction of an impurity element. The figure which shows the example of the variation | change_quantity to the direction of the tensile stress by heat processing. The figure explaining tensile stress and compressive stress. The figure which shows an example of the concept of this invention. The figure which shows an example of the concept of this invention. Sectional drawing which shows the manufacturing process of TFT of a pixel TFT and a driver circuit. Sectional drawing which shows the manufacturing process of TFT of a pixel TFT and a driver circuit. Sectional drawing which shows the manufacturing process of TFT of a pixel TFT and a driver circuit. Sectional drawing which shows the manufacturing process of TFT of a pixel TFT and a driver circuit. Sectional drawing which shows the manufacturing process of TFT of a pixel TFT and a driver circuit. FIG. 6 is a top view illustrating a configuration of a pixel TFT. Sectional drawing which shows the manufacturing process of TFT of a pixel TFT and a driver circuit. Sectional drawing which shows the manufacturing process of an active-matrix liquid crystal display device. FIG. 6 is a cross-sectional view of a driver circuit and a pixel portion of a light emitting device. FIG. 4A is a top view of a light-emitting device. FIG. 5B is a cross-sectional structure diagram of a driver circuit and a pixel portion of a light-emitting device. FIG. 11 illustrates an example of a semiconductor device. FIG. 11 illustrates an example of a semiconductor device. FIG. 11 illustrates an example of a semiconductor device. Sectional drawing which shows the preparation process of MOSFET. Sectional drawing which shows the preparation process of MOSFET. Sectional drawing which shows the preparation process of MOSFET.

[Embodiment 1]
An embodiment of the present invention will be described with reference to FIG. In this embodiment, the present invention is applied to a TFT.
A case where the present invention is applied to the gate electrode will be described.

First, the base insulating film 11 is formed on the substrate 10. As the substrate 10, a glass substrate, a quartz substrate, a single crystal silicon substrate, a metal substrate, or a stainless substrate on which an insulating film is formed may be used. Alternatively, a plastic substrate having heat resistance that can withstand the processing temperature may be used.

As the base insulating film 11, a base insulating film 11 made of an insulating film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film is formed. Although an example in which a single layer structure is used as the base film 11 is shown here, a structure in which two or more insulating films are stacked may be used. The base insulating film 1
1 may not be formed.

Next, the semiconductor film 12 is formed over the base insulating film 11. As the semiconductor film 12, a semiconductor film having an amorphous structure is formed by a known means (sputtering method, LPCVD method, plasma CVD method or the like).
Then, a known crystallization process (laser crystallization method, thermal crystallization method, or thermal crystallization method using a catalyst such as nickel) is performed to form a crystalline semiconductor film. This semiconductor film 12
Is formed with a thickness of 25 to 200 nm (preferably 30 to 100 nm). There is no limitation on the material of the semiconductor film, but it is preferably formed of silicon or a silicon germanium (SiGe) alloy.

Next, an insulating film 13 is formed on the semiconductor film 12. The insulating film 13 is formed by a single layer or a laminated structure of an insulating film containing silicon with a thickness of 40 to 150 nm using a plasma CVD method, a sputtering method, or the like. The insulating film 13 becomes a gate insulating film.

Next, a film thickness of 250 to 600 is formed on the insulating film 13 by using a sputtering method, a plasma CVD method, or the like.
A conductive film 14 of nm is formed. Here, an example in which a single layer structure is used as the conductive film 14 is shown, but a structure in which two or more conductive films are stacked may be used.

However, when the conductive film 14 is formed by the CVD method, the tensile stress 15 may be strong. Therefore, an impurity element is introduced to relieve internal stress in the conductive film 14 to obtain a desired internal stress. The introduction of the impurity element may be performed by a plasma doping method, an ion implantation method, an ion shower doping method, or the like. As the impurity element to be introduced, one or more elements selected from an impurity element imparting n-type, an impurity element imparting p-type, and a rare gas element are used, and an acceleration voltage is set to 30 to 120 keV and a dose amount is set. It is set to 1 × 10 ^{12 to} 9 × 10 ¹⁶ / cm ² , and the peak concentration is 1 × 10 ¹⁷ to 1 × 10 ²² / cm ³ .
(FIG. 1C) Of course, the optimum impurity element introduction conditions vary depending on the state of the conductive film and the desired internal stress. In addition, if an impurity element is introduced only into a desired region using a resist mask, the internal stress only in the desired region can be changed.

The internal stress of the conductive film thus formed becomes a desired internal stress, and the stress exerted on the semiconductor film can be reduced. When a TFT is manufactured using such a conductive film, the electrical characteristics are improved, and the operating characteristics of the semiconductor device can be greatly improved.

[Embodiment 2]
An embodiment of the present invention will be described with reference to FIG. In the present embodiment, a case will be described in which the internal stress is controlled by performing a heat treatment after introducing an impurity element.

  First, the steps up to introduction of an impurity element are performed in accordance with Embodiment Mode 1.

Subsequently, heat treatment is performed to increase if the internal stress in the conductive film 14 is a tensile stress, and relax if it is a compressive stress. The heat treatment may be performed by a known method such as a thermal annealing method using a furnace annealing furnace, a laser annealing method, or an RTA method. For example, if a thermal annealing method using a furnace annealing furnace is performed, it may be exposed to a nitrogen atmosphere at a temperature of about 500 to 1000 ° C. for about 3 minutes to 12 hours. Of course, the optimum heat treatment conditions vary depending on the state of the conductive film and the desired internal stress. Further, if the heat treatment for a long time is performed at the same time as the crystallization of the semiconductor film or the activation of the impurity element in the TFT manufacturing process, it can be performed without increasing the number of processes, and the efficiency is high.

Further, if heat treatment is performed only on a desired region by laser annealing or the like, it is possible to change the internal stress only on the desired region.

The internal stress of the conductive film thus formed becomes a desired internal stress, and the stress exerted on the semiconductor film can be reduced. When a TFT is manufactured using such a conductive film, the electrical characteristics are improved, and the operating characteristics of the semiconductor device can be greatly improved.

[Embodiment 3]
An embodiment of the present invention will be described with reference to FIG. In the present embodiment, a case will be described in which the internal stress is controlled by performing a heat treatment after introducing an impurity element.

  First, according to the first embodiment, the formation up to the formation of the insulating film 13 is performed.

Next, a film thickness of 250 to 600 is formed on the insulating film 13 by using a sputtering method, a plasma CVD method, or the like.
A conductive film 17 of nm is formed. Here, an example in which a single layer structure is used as the conductive film 17 is shown, but a structure in which two or more conductive films are stacked may be used.

However, the conductive film 17 formed by sputtering may have a strong compressive stress 15. Therefore, heat treatment is performed to change the internal stress in the conductive film 17. The heat treatment includes a thermal annealing method using a furnace annealing furnace, an RTA method, a laser annealing method, etc.
A known method may be used. (Fig. 2 (B))

If heat treatment is subsequently performed, the internal stress in the conductive film 14 increases if it is a tensile stress, and relaxes if it is a compressive stress. (FIG. 2C) The heat treatment may be performed by a known method such as a thermal annealing method using a furnace annealing furnace, a laser annealing method, or an RTA method. For example, if a thermal annealing method using a furnace annealing furnace is performed, a temperature of 500 to 10 is used.
What is necessary is just to expose for about 3 minutes-12 hours in nitrogen atmosphere at about 00 degreeC. Of course, the optimum heat treatment conditions vary depending on the state of the conductive film and the desired internal stress.

Further, an impurity element is introduced to change the internal stress. The introduction of the impurity element may be performed by a plasma doping method, an ion implantation method, an ion shower doping method, or the like. As the impurity element to be introduced, one or a plurality of elements selected from an impurity element imparting n-type, an impurity element imparting p-type, and a rare gas element are used, and an acceleration voltage of 30 to
120 keV, the dose is 1 × 10 ^{12 to} 9 × 10 ¹⁶ / cm ² , and the peak concentration is 1 × 1
0 ¹⁷ to 1 × 10 ²² / cm ³ . In addition, by introducing the impurity element after the heat treatment, the internal stress can be changed with a small dose and a low acceleration voltage by channeling.

The internal stress of the conductive film thus formed becomes a desired internal stress, and the stress exerted on the semiconductor film can be reduced. When a TFT is manufactured using such a conductive film, the electrical characteristics are improved, and the operating characteristics of the semiconductor device can be greatly improved.

The present invention configured as described above will be described in more detail with reference to the following examples.

Examples of the present invention will be described below, but it is needless to say that the present invention is not limited to these examples.

Experiments conducted to show the effectiveness of the present invention will be described. In this embodiment, W (tungsten) is used for the conductive film and Ar is used as the impurity element. However, the present invention is not particularly limited to these.

First, W was formed with a film thickness of 300 nm on the synthetic quartz substrate 10 by sputtering. Next, a silicon nitride oxide film having a thickness of 70 nm (composition ratio: Si = 32.8%, O = 63.
7%, H = 3.5%), and heat treatment was performed at 950 ° C. for 30 minutes. Then, the silicon nitride oxide film was removed. The reason why the silicon nitride oxide film is formed on W is to prevent W from peeling by heat treatment. Impurity elements are introduced by ion shower doping, and the conditions are shown in Table 1. The introduction of the impurity element was performed under three conditions before the heat treatment, after the heat treatment, and after the silicon nitride oxide film was removed. The result is shown in FIG. Here, when the change in internal stress is an increase in tensile stress, it is +, and when it is an increase in compressive stress, it is-.

FIG. 3 shows that when Ar is introduced, the internal stress changes in the direction of compressive stress under any conditions. When the impurity element is introduced after the heat treatment, the crystallinity is improved by the heat treatment, so that the impurity element is easily introduced deep into the film, and the internal stress greatly changes in the direction of the compressive stress. However, when Ar is introduced through the silicon nitride oxide film, since the substantial amount of Ar introduced in W is small, the change in the direction of compressive stress is small.

Next, FIG. 4 shows changes in internal stress before and after the heat treatment in the above experiment. In addition, the change in internal stress was also examined when only the heat treatment was performed without introducing the impurity element. From FIG. 4, at the acceleration voltage of 30 keV, the increase in tensile stress is larger than when no impurity element is introduced. This is probably because the tensile stress due to the heat treatment was increased by the amount of the compressive stress increased by the introduction of the impurity element. Further, since the change in the direction of tensile stress is small at 80 keV, if the acceleration voltage is high, the impurity element is introduced deeply into the film, so that it is considered that it is hardly affected by the heat treatment.

Thus, it was confirmed that the internal stress increases the compressive stress by introducing the impurity element, and the internal stress increases the tensile stress by the heat treatment. That is, by introducing the impurity element, or both the introduction of the impurity element and the heat treatment, the internal stress can be controlled, and a conductive film having a desired internal stress can be obtained.

In this embodiment, the case where the present invention is applied to a gate electrode of a TFT will be described with reference to FIG.

First, the base insulating film 11 is formed on the substrate 10. As the substrate 10, a glass substrate, a quartz substrate, a single crystal silicon substrate, a metal substrate, or a stainless substrate on which an insulating film is formed may be used. Alternatively, a plastic substrate having heat resistance that can withstand the processing temperature may be used.

As the base insulating film 11, a base insulating film 11 made of an insulating film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film is formed. Here, an example in which a single layer structure is used as the base insulating film 11 is shown, but a structure in which two or more layers of the insulating film are stacked may be used. Note that the base insulating film is not necessarily formed. In this embodiment, the silicon oxynitride film 11 (
(Composition ratio Si = 32%, O = 27%, N = 24%, H = 17%).

Next, a semiconductor film is formed on the base insulating film 11 and then etched to perform the semiconductor layer 20.
Get 21. Here, it is assumed that the semiconductor layer 20 forms an n-channel TFT and the semiconductor layer 21 forms a p-channel TFT. The semiconductor film is formed by forming a semiconductor film having an amorphous structure by a known means (sputtering method, LPCVD method, plasma CVD method, etc.), and then known crystallization treatment (laser crystallization method, thermal crystallization method). Or a thermal crystallization method using a catalyst such as nickel) to form a crystalline semiconductor film. The thickness of the semiconductor film 12 is 2
The film is formed with a thickness of 5 to 200 nm (preferably 30 to 100 nm). There is no limitation on the material of the semiconductor film, but it is preferably formed of silicon or a silicon germanium (SiGe) alloy.
In this embodiment, a semiconductor film having a crystal structure is formed by irradiation with laser light, and patterning is performed to form the semiconductor layers 20 and 21.

Then, an insulating film 22 that covers the semiconductor layer 12 is formed. The insulating film 22 is formed by a single layer or a laminated structure of an insulating film containing silicon with a thickness of 40 to 150 nm using a plasma CVD method or a sputtering method. The insulating film 13 becomes a gate insulating film. In this embodiment, a silicon oxynitride film (composition ratio Si = 32%, O = 59%) is formed to a thickness of 110 nm by plasma CVD.
, N = 7%, H = 2%).

Subsequently, a film thickness of 250 to 600 is formed on the insulating film 22 using a sputtering method, a plasma CVD method, or the like.
A conductive film 23 of nm is formed. Here, an example in which a single layer structure is used as the conductive film 23 is shown, but a structure in which two or more conductive films 23 are stacked may be used.
The conductive film may be formed of an element selected from Ta, W, Ti, Mo, Al, Cu, Cr, and Nd, or an alloy material or a compound material containing the element as a main component. Also,
A semiconductor film typified by a polycrystalline silicon film into which an impurity element such as phosphorus is introduced may be used. Further, an AgPdCu alloy may be used. In this embodiment, the film thickness is 400 nm by sputtering.
A Ta film is formed. A film formed by sputtering often has a compressive stress.

Next, the conductive film 23 is etched by a patterning process using a photolithography method to form a first conductive film 24 and a second conductive film 25. (Fig. 6 (
B))

Then, an impurity region 27 is formed in the semiconductor film by introducing the first impurity element. The introduction of the impurity element may be performed by a plasma doping method, an ion implantation method, an ion shower doping method, or the like. In this embodiment, As is used as the impurity element imparting n-type.
In addition, in the introduction of the first impurity element, the introduction amount in the introduction of the first impurity element is set larger than the amount of the impurity element introduced in the introduction of the second impurity element. By introducing the first impurity element, an impurity region 27 for functioning as an n-channel TFT is formed.
As is also introduced into the first conductive film 24 and the second conductive film 25, and the compressive stress 15 increases.

Subsequently, a second impurity element is introduced to form an impurity region 28 in the semiconductor film. At this time, since the semiconductor layer 20 forming the n-channel TFT is covered with the mask 26b made of a resist, no impurity element is introduced. In this embodiment, B is used as the impurity element imparting p-type. By introducing the second impurity element, a p-channel TFT
Although the impurity region 28 for functioning as an impurity is formed, B is also introduced into the second conductive film 25, and the compressive stress 15 of the second conductive film 25 further increases.

In this manner, impurity regions are formed, and more impurity elements are introduced into the second conductive film 25 than in the first conductive film 24.

Subsequently, when heat treatment is performed, the crystallinity of the semiconductor film is restored and the impurity elements are activated. Further, the internal stress in the first conductive film 24 and the second conductive film 25 also changes by the heat treatment. However, since the amounts of impurity elements introduced into the first conductive film 24 and the second conductive film 25 are different, the internal stress after the heat treatment is also different. Since the first conductive film 24 has a small amount of impurity element introduced, it undergoes a large change in the direction 16 of increase in tensile stress due to heat treatment, and the internal stress in the first conductive film 24 becomes tensile stress. for that reason,
The stress received by the semiconductor film forming the n-channel TFT is tensile stress. Second
Since the conductive film 25 has a large amount of impurity element introduced, the internal stress does not change much by heat treatment, and the internal stress in the second conductive film 25 becomes a compressive stress. Therefore, the stress received by the semiconductor film forming the n-channel TFT is a compressive stress.

In this way, by controlling the internal stress of the conductive film, the stress received by the semiconductor film forming the n-channel TFT is defined as tensile stress, and the stress received by the semiconductor film forming the p-channel TFT is defined as compressive stress. Can do. When a TFT is manufactured using such a semiconductor film, the electrical characteristics are improved, and the operating characteristics of the semiconductor device can be greatly improved.

In this embodiment, the case where the present invention is applied to a wiring of a TFT will be described with reference to FIG.

A base insulating film is formed on a substrate, a semiconductor layer is formed on the base insulating film, an insulating film is formed to cover the semiconductor layer, and a conductive layer is formed on the semiconductor layer through the insulating film Thereafter, an impurity element is introduced into the semiconductor film using the conductive layer as a mask. Further, the method shown in Embodiment 2 may be followed.

Subsequently, an interlayer insulating film 29 made of an inorganic insulating film material or an organic insulating material is formed. In this embodiment, the interlayer insulating film 29 has a single layer structure, but may have a laminated structure of two or more layers.

Then, a conductive film electrically connected to each impurity region is formed. The conductive film may have a high tensile stress. Therefore, an impurity element is introduced to change the internal stress of the conductive film in the direction of increasing compressive stress. By controlling the internal stress by such a method, a conductive film having an internal stress of ± 1 GPa or less can be formed, and patterning is performed to form wirings 31 to 33.
The wiring pattern is prevented from shifting when forming the wiring.

In addition, the internal stress of the conductive layer formed in this way is ± 1 GPa or less, and the stress exerted on the interlayer insulating film and the semiconductor film can be reduced.
When a TFT is manufactured using such a conductive layer, its electrical characteristics are good, and the operating characteristics of the semiconductor device can be greatly improved.

In this embodiment, the case where the present invention is applied to a gate electrode of a TFT having a structure different from that of Embodiment 2 will be described with reference to FIG.

First, the conductive film 35 is formed on the substrate 10. As the substrate 10, a glass substrate, a quartz substrate, a single crystal silicon substrate, a metal substrate, or a stainless substrate on which an insulating film is formed may be used. Alternatively, a plastic substrate having heat resistance that can withstand the processing temperature may be used.

Further, as the conductive film 35, a sputtering method, a plasma CVD method, or the like is used, and a film thickness of 250 to 6 is used.
After the 00 nm conductive film 20 is formed, patterning is performed by photolithography. Here, an example in which a single layer structure is used as the conductive film 35 is shown, but a structure in which two or more conductive films are stacked may be used. As the conductive film, Ta, W, Ti, Mo,
You may form with the element selected from Al, Cu, Cr, Nd, or the alloy material or compound material which has the said element as a main component.
Alternatively, a semiconductor film typified by a polycrystalline silicon film into which an impurity element such as phosphorus is introduced may be used. Further, an AgPdCu alloy may be used. In this embodiment, the film thickness is 40 by sputtering.
A 0-nm Al—Ti film is formed.

Subsequently, an impurity element is introduced, and the internal stress in the conductive film is reduced in the direction of increasing the compressive stress 15.
To change. Since the internal stress in the conductive film changes in the direction of increasing tensile stress due to the heat treatment in the subsequent process, this is a process performed in advance in order to relieve the internal stress.

Then, an insulating film 36 that covers the conductive film 35 is formed. The insulating film 36 is formed by a single layer or a laminated structure of an insulating film containing silicon with a thickness of 40 to 150 nm by using a plasma CVD method or a sputtering method. The insulating film 36 becomes a gate insulating film. In this embodiment, a silicon oxynitride film (composition ratio Si = 32%, O = 59%, with a thickness of 110 nm by plasma CVD method)
N = 7%, H = 2%).

Next, a semiconductor film 37 is formed over the insulating film 36. The semiconductor film 37 is formed by forming a semiconductor film having an amorphous structure by a known means (sputtering method, LPCVD method, plasma CVD method, etc.), and then known crystallization treatment (laser crystallization method, thermal crystallization method). Or a thermal crystallization method using a catalyst such as nickel) to form a crystalline semiconductor film. The thickness of the semiconductor film 37 is 25 to 200 nm (preferably 30 to 100 nm). There is no limitation on the material of the semiconductor film, but it is preferably formed of silicon or a silicon germanium (SiGe) alloy. In this example, a 55 nm amorphous silicon film was formed using plasma CVD,
A solution containing nickel is held on the amorphous silicon film. This amorphous silicon film is dehydrogenated (50
After performing 0 ° C for 1 hour, thermal crystallization (550 ° C for 4 hours) is performed. By the heat treatment, the semiconductor film 37 becomes a semiconductor film having a crystal structure. Further, since the impurity element is introduced in advance, the amount of change in internal stress in the conductive film 35 can be small.

The internal stress of the conductive film thus formed becomes a desired internal stress, and the stress exerted on the semiconductor film can be reduced. When a TFT is manufactured using such a conductive film, the electrical characteristics are improved, and the operating characteristics of the semiconductor device can be greatly improved.

In this embodiment, the present invention is applied to an insulated gate field effect transistor (MOSFET or IG).
An example in which a CMOS circuit is configured by application to an FET will be described with reference to FIGS.

First, a single crystal silicon substrate 401 is prepared, an impurity element is implanted, and a P-type well 402,
An N-type well 403 is formed. The single crystal silicon substrate may be P-type or N-type. Such a structure is a so-called twin tab structure, and the well concentration is 1 × 10 ¹⁸ / cm ³ or less (typically 1 × 10 ^{16 to} 5 × 10 ¹⁷ / cm ³ ).

Next, after selective oxidation is performed by a known LOCOS method or the like to form a field oxide film 404, an oxide film (later gate insulating film) 4 having a thickness of 30 nm is formed on the silicon surface by a thermal oxidation process.
05 is formed. (FIG. 21 (A))

Next, a first gate electrode 406 and a second gate electrode 407 are formed. In this embodiment, a conductive silicon film is used as a material constituting the gate electrode, but Ta,
An element selected from W, Ti, Mo, Al, Cu, Cr, and Nd, or an alloy material or a compound material containing the element as a main component can be used.

After the formation of the first gate electrode 406 and the second gate electrode 407, a region to be a p-channel MOSFET (on the right side in the drawing) is covered with a resist mask 408, and an n-type is formed with respect to the single crystal silicon substrate 401. Impurity elements to be introduced are introduced. (FIG. 21B) The impurity element is introduced by any one of a laser doping method, a plasma doping method, an ion implantation method, and an ion shower doping method, and has a concentration of 5 × 10 ¹⁸ to 1 × 10.
It introduce | transduces so that it may become ¹⁹ / cm < ³ >. In this embodiment, As an impurity element imparting n-type conductivity is As.
Is used. Part of the impurity regions 410 and 411 thus formed (the end on the side in contact with the channel formation region) functions later as an LDD region of the n-channel MOSFET.

Next, a region to be an n-channel MOSFET is covered with a resist mask 412.
Then, an impurity element imparting p-type conductivity is introduced into the single crystal silicon substrate 401. (FIG. 21C) In this example, B (boron) is used as an impurity element imparting n-type conductivity.
In this manner, impurity regions 414 and 415 that later function as LDD regions of the p-channel MOSFET are formed.

When the state of FIG. 21C is obtained, a silicon oxide film (not shown) is deposited and etched back to form sidewalls 416 and 417. (FIG. 22 (A)
)

Next, a region to be a p-channel MOSFET is again covered with a resist mask 418, and an impurity element imparting n-type conductivity is introduced at a concentration of 1 × 10 ²⁰ / cm ³ . Thus, the source region 41
9, a drain region 420 is formed, and an LDD region 421 is formed under the sidewall 416. (Fig. 22 (B))

Similarly, a region to be an n-channel MOSFET is covered with a resist mask 422, and an impurity element imparting p-type conductivity is introduced at a concentration of 1 × 10 ²⁰ / cm ³ . Thus, the drain region 42
3. A source region 424 is formed, and an LDD region 425 is formed under the sidewall 417. (FIG. 22C) Further, one or more elements selected from rare gas elements are introduced while being covered with the resist mask 422. In this way, the second gate electrode 40
7, a larger amount of an impurity element is introduced than the first gate electrode 406. As a result, the second
The compressive stress of the gate electrode 407 is stronger than that of the first gate electrode 406, and the p-channel type M
The compressive stress received by the channel formation region in the OSFET is also stronger than the stress received by the channel formation region in the n-channel MOSFET.

When the state of FIG. 22C is obtained, a first heat treatment is performed to activate the introduced impurity element.

Subsequently, a titanium film is formed and second heat treatment is performed to form a titanium silicide layer 426 on the surfaces of the source region, the drain region, and the gate electrode. Of course, a metal silicide using another metal film can also be formed. After the silicide layer is formed, the titanium film is removed.

By the first heat treatment and the second heat treatment, the first gate electrode 406 and the second heat treatment
Although the internal stress of the gate electrode 407 also changes, the change in the internal stress is small in the second gate electrode 407 because the introduction amount of the impurity element is larger than that in the first gate electrode 406. Therefore, the second
The compressive stress of the gate electrode 407 is stronger than that of the first gate electrode 406, and the p-channel MOS
The compressive stress received by the channel formation region in the FET is also stronger than the stress received by the channel formation region in the n-channel MOSFET.

Next, an interlayer insulating film 427 is formed, contact holes are opened, and source electrodes 428 and 42 are formed.
9. A drain electrode 430 is formed. Of course, it is also effective to perform hydrogenation after electrode formation.

Through the steps as described above, a CMOS circuit as shown in FIG. 23 can be obtained. The electrical characteristics of the CMOS circuit in which the internal stress of the gate electrode is controlled are good, and the operating characteristics of the semiconductor device can be greatly improved.

In this embodiment, a method for manufacturing an active matrix substrate will be described with reference to FIGS. In this specification, a substrate in which a pixel portion having a CMOS circuit, a driver circuit, a pixel TFT, and a storage capacitor is formed over the same substrate is referred to as an active matrix substrate for convenience.

First, in this embodiment, a substrate 501 made of glass such as barium borosilicate glass represented by Corning # 7059 glass or # 1737 glass or aluminoborosilicate glass is used. Note that the substrate 501 may be a quartz substrate, a single crystal silicon substrate, a metal substrate, or a stainless substrate on which an insulating film is formed. Further, a plastic substrate having heat resistance that can withstand the processing temperature of this embodiment may be used. In this embodiment, a synthetic quartz glass substrate is used.

Next, a lower light shielding film is formed on the quartz substrate 501. First, a film thickness of 10 to 150 nm (preferably 50 to 10 nm) made of an insulating film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film.
0 nm) is formed. And Ta, W, Cr, which can withstand the processing temperature of this embodiment
A lower light-shielding film is formed with a film thickness of about 300 nm by a conductive material such as Mo and its laminated structure. The lower light shielding film also has a function as a gate wiring. In this embodiment, a crystalline silicon film having a thickness of 75 nm is formed, and then a WSix (x = 2.0 to 2.8) having a thickness of 150 nm is formed, and then unnecessary portions are etched to form a lower light shielding film. 503 is formed. In this example,
A single layer structure is used as the lower light shielding film 503, but a structure in which two or more insulating films are stacked may be used.

Then, a base film 504 having a thickness of 10 to 650 nm (preferably 50 to 600 nm) made of an insulating film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film is formed over the substrate 501 and the lower light shielding film 503. Although a single layer structure is used as the base film 504 in this embodiment, a structure in which two or more insulating films are stacked may be used. In this embodiment, as the base film 504, a film thickness of 5 is formed by using a plasma CVD method using SiH ₄ , NH ₃ , and N ₂ O as reaction gases.
80 nm silicon oxynitride film 504 (composition ratio Si = 32%, O = 27%, N = 24%, H =
17%) at 350 ° C.

Next, a semiconductor film 505 is formed over the base film 504. As the semiconductor film 505, a semiconductor film having an amorphous structure is formed with a thickness of 25 to 80 nm (preferably 30 to 60 nm) by a known means (such as sputtering, LPCVD, or plasma CVD). There is no limitation on the material of the semiconductor film, but it is preferably formed of silicon or a silicon germanium (SiGe) alloy.

Then, a thermal crystallization method using a catalyst such as nickel is performed to crystallize the semiconductor film. In addition to a thermal crystallization method using a catalyst such as nickel, a known crystallization treatment (laser crystallization method, thermal crystallization method, etc.) may be performed in combination. In this embodiment, a nickel acetate solution (weight-concentrated concentration 10 ppm, volume 5 ml) is applied to the entire surface of the film by spin coating to form a metal-containing layer 405, which is exposed to a nitrogen atmosphere at a temperature of 600 degrees for 12 hours.

In the case where a laser crystallization method is also applied, a pulse oscillation type or a continuous emission type excimer laser, a YAG laser, a YVO ₄ laser, or the like can be used. In the case of using these lasers, it is preferable to use a method in which a laser beam emitted from a laser oscillator is linearly collected by an optical system and irradiated onto a semiconductor film. The crystallization conditions are appropriately selected by the practitioner. When an excimer laser is used, the pulse oscillation frequency is 300 Hz, and the laser energy density is 100 to 800 mJ / cm ² (typically 200 to 700 mJ / cm ^2). ). When a YAG laser is used, the second harmonic is used and the pulse oscillation frequency is 1 to 300 Hz, and the laser energy density is 300 to 1000 mJ / cm ² (typically 350 to 800 mJ / cm ² ). Then, a laser beam condensed linearly with a width of 100 to 1000 μm, for example 400 μm, is irradiated over the entire surface of the substrate, and the superposition ratio (overlap ratio) of the linear laser beam at this time is set to 50 to 98%. Also good.

Subsequently, gettering is performed in order to remove or reduce the metal element used to promote crystallization from the semiconductor layer serving as the active region. Regarding gettering, JP-A-10-27.
The method disclosed in Japanese Patent No. 0363 may be applied. In this embodiment, a silicon oxide film having a thickness of 50 nm is formed as a mask and patterned to form a silicon oxide film 50 having a desired shape.
6a-506d are obtained. An element belonging to group 15 selectively (typically P
By introducing (phosphorus)) and performing heat treatment, the metal element can be removed from the semiconductor layer or reduced to the extent that the semiconductor characteristics are not affected. A TFT having an active region manufactured in this manner has a low off-current value and good crystallinity, so that high field-effect mobility can be obtained.
Good properties can be achieved.

Then, the crystalline semiconductor film is etched to form semiconductor layers 507a to 510a. (Figure 9 (D))

Next, it is preferable to remove the masks 506a to 506d, form a new insulating film 511, and perform heat treatment to improve the crystallinity of the semiconductor film to thermally oxidize the upper portion of the semiconductor layer. In this embodiment, after forming a 20 nm silicon oxide film with a low pressure CVD apparatus, heat treatment is performed in a furnace annealing furnace. By this treatment, the upper portions of the semiconductor layers 507a to 510a are oxidized. Then, when the oxidized portion of the silicon oxide film and the semiconductor layer is etched, semiconductor layers 507b to 510b with improved crystallinity are obtained.

After forming the semiconductor layers 507b to 510b, a trace amount of an impurity element (boron or phosphorus) may be introduced in order to control the threshold value of the TFT.

Next, a first gate insulating film 511 is formed to cover the semiconductor layers 507b to 510b. The first gate insulating film 511 is formed using a plasma CVD method or a sputtering method with a thickness of 20 to 15.
The insulating film containing silicon is formed to have a thickness of 0 nm. In this embodiment, 35 is formed by plasma CVD.
Silicon oxynitride film with a thickness of nm (composition ratio Si = 32%, O = 59%, N = 7%, H = 2%)
Formed with. Needless to say, the gate insulating film is not limited to the silicon oxynitride film, and another insulating film containing silicon may be used.

When a silicon oxide film is used, TEOS (Tetraethyl Ortho
It can be formed by mixing silicate) and O ₂ , setting the reaction pressure to 40 Pa, the substrate temperature to 300 to 400 ° C., and discharging at a high frequency (13.56 MHz) power density of 0.5 to 0.8 W / cm ² . The silicon oxide film thus manufactured can obtain good characteristics as a gate insulating film by thermal annealing at 400 to 500 ° C. thereafter.

Then, the gate insulating film is partially etched to expose the semiconductor layer 510a which becomes one of the electrodes of the storage capacitor, and an impurity element is introduced into the semiconductor layer 510a. (Fig. 10 (B
)) At this time, a resist 513 is formed in another region, and no impurity element is introduced. In this embodiment, P (phosphorus) is used as the impurity element, and the impurity element is introduced at an acceleration voltage of 10 keV and a dose of 5 × 10 ¹⁴ / cm ² .

Subsequently, a second gate insulating film 512 is formed. The second gate insulating film 512 is formed of an insulating film containing silicon with a thickness of 20 to 150 nm by using a plasma CVD method or a sputtering method. In this embodiment, a silicon oxynitride film (composition ratio Si = 32%, O = 59%, N = 7%, H = 2%) with a thickness of 50 nm by plasma CVD.
Formed with. Needless to say, the gate insulating film is not limited to the silicon oxynitride film, and another insulating film containing silicon may be used.

Then, after forming a contact connected to the lower light shielding film, a first film having a thickness of 20 to 100 nm is formed.
The conductive film 515 and the second conductive film 516a having a thickness of 100 to 400 nm are stacked.
In this embodiment, a first conductive film 515 made of a TaN film with a thickness of 30 nm, and a film thickness of 370 nm.
A second conductive film 516a made of the W film is stacked. The TaN film is formed by sputtering,
Sputtering was performed in a nitrogen-containing atmosphere using a Ta target. The W film is formed by sputtering using a W target. In addition, it can be formed by a thermal CVD method using tungsten hexafluoride (WF ₆ ). In any case, in order to use as a gate electrode, it is necessary to reduce the resistance, and the resistivity of the W film is desirably 20 μΩcm or less.

In this embodiment, the first conductive film 515 is TaN and the second conductive film 516a is W. However, there is no particular limitation, and all of them are Ta, W, Ti, Mo, Al, Cu, Cr, Nd. You may form with the element selected from these, or the alloy material or compound material which has the said element as a main component. Alternatively, a semiconductor film typified by a crystalline silicon film into which an impurity element such as phosphorus is introduced may be used. Further, an AgPdCu alloy may be used. The first conductive film is made of tantalum (Ta
) Film, the second conductive film is a W film, and the first conductive film is titanium nitride (Ti
N) film, the second conductive film is a W film, and the first conductive film is tantalum nitride (
It is also possible to use a combination of a TaN) film and a second conductive film made of an Al film, a first conductive film made of a tantalum nitride (TaN) film, and a second conductive film made of a Cu film.

Here, in order to obtain a desired internal stress in the second conductive film 516a, a third impurity element is introduced. The introduction of the impurity element may be performed by a plasma doping method, an ion implantation method, or an ion shower doping method. As a result, the second conductive film 516b having a desired internal stress can be formed in the direction of increasing compressive stress. (Fig. 10 (
D)) In this embodiment, the acceleration voltage is 70 keV, and the impurity element is introduced using Ar.

Next, a resist mask (not shown) is formed using a photolithography method,
An etching process for forming electrodes and wirings is performed. In this example, ICP (Inductively Coupled Plasma) etching method is used as an etching condition,
CF ₄ , Cl _2, and O ₂ are used as etching gases, and the respective gas flow ratios are 25/25 /
Etching was performed by generating a plasma by generating 500 W of RF (13.56 MHz) power to the coil-type electrode at a pressure of 1 Pa at a pressure of 10 (sccm). 150 on the substrate side (sample stage)
Apply W RF (13.56 MHz) power and apply a substantially negative self-bias voltage.

Then, a fourth impurity element is introduced, and an impurity element imparting n-type conductivity is introduced into the semiconductor layer. (FIG. 11A) The conditions for introducing the impurity element are 1 × 10 ^{13 to} 5 × 10 ¹⁴ / cm ^2.
And an acceleration voltage of 30 to 80 keV. In this embodiment, the dose amount is 1.5 × 10 ^13.
/ Cm ² and an acceleration voltage of 60 keV. As an impurity element imparting n-type, an element belonging to Group 15, typically phosphorus (P) or arsenic (As) is used. Here, phosphorus (P
) Is used. In this case, the conductive layers 517 to 521 serve as a mask for the impurity element imparting n-type, and the low concentration impurity regions 523 to 524 are formed in a self-aligning manner. An impurity element imparting n-type conductivity is added to the low concentration impurity regions 523 to 524 in a concentration range of 1 × 10 ¹⁸ to 1 × 10 ²⁰ / cm ³ . Here, a resist mask 522 is formed in the semiconductor layer forming the p-channel TFT, and an impurity element imparting n-type conductivity is not introduced.

Next, the resist mask is removed, a new mask is formed, and a fifth impurity element is introduced as shown in FIG. Conditions for introducing the impurity element are a dose amount of 1 × 10 ¹³ to 1 × 10 ¹⁵ / cm ² and an acceleration voltage of 30 to 120 keV. At this time, the mask 525b is formed so as not to introduce an impurity element imparting n-type into the semiconductor layer for forming the p-channel TFT, and the semiconductor layer for forming the n-channel TFT is selectively high-concentration Masks 525a and 525c are formed to form impurity regions. In this embodiment, the dose is set to 2 × 10 ¹⁵ / cm ² and the acceleration voltage is set to 50 keV. Thus, high concentration impurity regions 526 and 529 are formed.

Next, after removing the resist mask, a new resist mask 532 is formed.
a and 532b are formed, and a sixth impurity element is introduced as shown in FIG. By the introduction of the sixth impurity element, an impurity region 533 is formed in which an impurity element imparting a conductivity type opposite to the one conductivity type is added to the semiconductor layer that becomes an active layer of the p-channel TFT. Using the second conductive layer 518 as a mask for the impurity element, an impurity element imparting p-type conductivity is added to form an impurity region in a self-aligning manner. In this embodiment, the impurity region 533
Is formed by ion shower doping using diborane (B ₂ H ₆ ). The conditions of the ion shower doping method are a dose of 1 × 10 ¹³ to 1 × 10 ¹⁴ / cm ² and an acceleration voltage of 30 to 1.
This is performed at 20 keV. In the introduction of the sixth impurity element, the semiconductor layer forming the n-channel TFT is covered with resist masks 532a and 532b.

Next, the resist mask is removed, a new mask is formed, and a seventh impurity element is introduced as shown in FIG. The conditions for introducing the impurity element are a dose amount of 1 × 10 ¹³ to 1 × 10 ¹⁵ / cm ² and an acceleration voltage of 20 to 120 keV. At this time, masks 534a and 534c are formed so as not to introduce an impurity element imparting p-type into the semiconductor layer for forming the n-channel TFT, and the semiconductor layer for forming the p-channel TFT is selectively formed. A mask 534b is formed to form a high concentration impurity region. In this embodiment, the dose is set to 1 × 10 ¹⁵ / cm ² and the acceleration voltage is set to 40 keV. Thus, a high concentration impurity region 535 is formed.

Through the above steps, a high concentration impurity region and a low concentration impurity region are formed in each semiconductor layer.

Next, the resist mask 534 is removed, and a first interlayer insulating film 538 is formed. The first interlayer insulating film 538 is formed of an insulating film containing silicon with a thickness of 100 to 200 nm by using a plasma CVD method or a sputtering method.
In this embodiment, a silicon oxynitride film having a thickness of 150 nm is formed by a plasma CVD method. Needless to say, the first interlayer insulating film 538 is not limited to the silicon oxynitride film, and another insulating film containing silicon may be used as a single layer or a stacked structure.

Next, as shown in FIG. 12B, heat treatment is performed to recover the crystallinity of the semiconductor layers and to activate the impurity elements added to the respective semiconductor layers. This heat treatment is performed by a thermal annealing method using a furnace annealing furnace. As the thermal annealing method, an oxygen concentration is 1 ppm or less, preferably 0.1 ppm or less in a nitrogen atmosphere at 400 to 700 ° C., typically 500 to 55.
What is necessary is just to perform at 0 degreeC, and the activation process was performed by heat processing for 4 hours at 550 degreeC in the present Example. In addition to thermal annealing, laser annealing or rapid thermal annealing (RTA)
Law) can be applied.

Further, heat treatment may be performed before forming the first interlayer insulating film. However, when the wiring material used is weak against heat, heat treatment is performed after an interlayer insulating film (insulating film containing silicon as a main component, for example, a silicon nitride film) is formed to protect the wiring and the like as in this embodiment. It is preferable to carry out.

Then, hydrogenation can be performed by heat treatment (heat treatment at 300 to 550 ° C. for 1 to 12 hours). This step is a step of terminating dangling bonds in the semiconductor layer with hydrogen contained in the first interlayer insulating film 461. Of course, the semiconductor layer can be hydrogenated regardless of the presence of the first interlayer insulating film. As other means of hydrogenation, plasma hydrogenation (using hydrogen excited by plasma) or 300 to 450 in an atmosphere containing 3 to 100% hydrogen is used.
You may heat-process at 1 degreeC for 1 to 12 hours.

Next, a second interlayer insulating film 539 made of an inorganic insulating film material or an organic insulating material is formed over the first interlayer insulating film 538. In this embodiment, a silicon nitride oxide film having a thickness of 1 μm is formed.

In the driving circuit 555, the wiring 54 electrically connected to each impurity region.
0-542 are formed. In the pixel portion 556, source wirings 543 and 545 and a drain electrode 544 are formed. Note that these wirings are a Ti film with a thickness of 50 nm and a thickness of 5 nm.
A laminated film of 00 nm alloy film (alloy film of Al and Ti) is formed by patterning.

FIG. 13 shows a top view of the state thus far prepared. In addition, the same code | symbol is used for the part corresponding to FIGS. 9-12. A chain line AA ′ in FIG. 12C corresponds to a cross-sectional view taken along the chain line AA ′ in FIG. A chain line BB ′ in FIG. 12C corresponds to a cross-sectional view taken along the chain line BB ′ in FIG.

Next, a third interlayer insulating film 560 made of an inorganic insulating material or an organic insulating material is formed on the second interlayer insulating film 539. In this embodiment, a silicon nitride oxide film having a thickness of 1.8 μm is formed.

On the third interlayer insulating film 539, a light shielding film 561, 562 is formed by patterning a film having high light shielding properties such as Al, Ti, W, Cr, or black resin into a desired shape. This light shielding film 5
61 and 562 are arranged in a mesh pattern so as to shield light other than the opening of the pixel. Further, a fourth interlayer insulating film 563 is formed of an inorganic insulating material so as to cover the light shielding film 117.

Then, a contact hole leading to the connection wiring 544 is formed, and a transparent conductive film such as ITO is formed by 1
The pixel electrodes 564 and 565 are formed by forming them to a thickness of 00 nm and patterning them in a desired shape.

As described above, an active matrix substrate in which the driver circuit 555 having the n-channel TFT 551 and the p-channel TFT 552, the pixel portion 556 having the pixel TFT 553, and the storage capacitor 554 is formed over the same substrate is completed.

The internal stress of the gate electrode formed as described above becomes a desired internal stress, and the stress exerted on the semiconductor film can be reduced. When a TFT is manufactured using such a gate electrode, the electrical characteristics are improved and the operating characteristics of the semiconductor device can be greatly improved.

Note that this embodiment can be freely combined with Embodiment 2 or Embodiment 3.
Of course, the active matrix substrate can be manufactured using the TFT formed in Embodiment 4 and the MOSFET formed in Embodiment 5.

In this embodiment, a process for manufacturing a reflective liquid crystal display device from the active matrix substrate manufactured in Embodiment 6 will be described below. FIG. 15 is used for the description.

First, after obtaining an active matrix substrate in the state of FIG. 14B according to Example 6, an alignment film 567 is formed on at least the pixel electrodes 564 and 565 on the active matrix substrate, and a rubbing process is performed. In this embodiment, before forming the alignment film 567, an organic resin film such as an acrylic resin film is patterned to form columnar spacers 572 for maintaining a substrate interval at a desired position. Further, instead of the columnar spacers, spherical spacers may be scattered over the entire surface of the substrate.

Next, a counter substrate 569 is prepared. Next, a colored layer 570 and a planarization film 573 are formed over the counter substrate 569.

Next, a counter electrode 576 made of a transparent conductive film was formed over the planarization film 573 in at least the pixel portion, an alignment film 574 was formed over the entire surface of the counter substrate, and a rubbing process was performed.

Then, the active matrix substrate on which the pixel portion and the driver circuit are formed and the counter substrate are attached to each other with a sealant 568. A filler is mixed in the sealing material 568, and two substrates are bonded to each other with a uniform interval by the filler and the columnar spacer. after that,
A liquid crystal material 575 is injected between both substrates and completely sealed with a sealant (not shown). A known liquid crystal material may be used for the liquid crystal material 575. In this way, the reflection type liquid crystal display device shown in FIG. 15 is completed. If necessary, the active matrix substrate or the counter substrate is divided into a desired shape. Further, a polarizing plate (not shown) was attached only to the counter substrate. And FPC was affixed using the well-known technique.

In the liquid crystal display device manufactured as described above, since the internal stress of the gate electrode is controlled to a desired value, it is possible to reduce the stress exerted on the semiconductor film, and the operating characteristics of the liquid crystal display device Can also be greatly improved. And such a liquid crystal display device can be used as a display part of various electronic devices.

Note that this embodiment can be freely combined with Embodiment 2, Embodiment 3, or Embodiment 6.

In this example, an example in which a light-emitting device is manufactured using the present invention will be described. In this specification, the light emitting device includes a display panel in which a light emitting element formed on a substrate is sealed between the substrate and a cover material, and a display module in which an IC (Integrated Circuit) is mounted on the display panel. It is a collective term. Note that the light-emitting element includes a layer (light-emitting layer) containing an organic compound from which luminescence (Electro Luminescence) generated by applying an electric field is obtained, an anode layer, and a cathode layer. Luminescence in organic compounds includes light emission when returning from the singlet excited state to the ground state (fluorescence) and light emission when returning from the triplet excited state to the ground state (phosphorescence).
Including either or both of these emissions.

FIG. 16 is a cross-sectional view of the light emitting device of this example. In FIG. 16, a driver circuit provided on a substrate 700 is formed using the CMOS circuit of FIG. Therefore, the description of the structure may be referred to the description of the n-channel TFT 551 and the p-channel TFT 552, but the internal stress is controlled by introducing Ar into the gate electrodes of the n-channel TFT 551 and the p-channel TFT 552. The stress exerted on the semiconductor film is reduced. Therefore, it is possible to improve the electrical characteristics of the TFT. In this embodiment, a single gate structure is used, but a double gate structure or a triple gate structure may be used.

The switching TFT 603 provided over the substrate 700 is an n-channel type T in FIG.
It is formed using FT551. Therefore, the description of the structure may be referred to the description of the n-channel TFT 551, but the internal stress is controlled by introducing Ar into the gate electrode of the n-channel TFT 551, and the stress exerted on the semiconductor film is reduced. is there. Therefore, it is possible to improve the electrical characteristics of the TFT.

Note that although a double gate structure in which two channel formation regions are formed is used in this embodiment, a single gate structure in which one channel formation region is formed or a triple gate structure in which three channel formation regions are formed may be used.

Further, the wirings 701 and 703 function as source wirings of the CMOS circuit, and the wiring 702 functions as a drain wiring. The wiring 704 functions as a wiring for electrically connecting a source wiring (not shown) and the source region of the switching TFT, and the wiring 705 electrically connects the drain wiring (not shown) and the drain region of the switching TFT. Functions as a wiring to connect to.

Note that the current control TFT 604 is formed using the p-channel TFT 552 in FIG. Therefore, the description of the structure may be referred to the description of the p-channel TFT 552.
The internal stress is controlled by introducing Ar into the gate electrode of the channel type TFT 552,
The stress on the semiconductor film is reduced. Therefore, it is possible to improve the electrical characteristics of the TFT. In this embodiment, a single gate structure is used, but a double gate structure or a triple gate structure may be used.

A wiring 706 is a source wiring (corresponding to a current supply line) of the current control TFT, and is an electrode electrically connected to the pixel electrode 711.

Reference numeral 711 denotes a pixel electrode (anode of the light emitting element) made of a transparent conductive film. As the transparent conductive film, a compound of indium oxide and tin oxide, a compound of indium oxide and zinc oxide, zinc oxide, tin oxide, or indium oxide can be used. Moreover, you may use what added the gallium to the said transparent conductive film. The pixel electrode 711 is formed on the flat interlayer insulating film 710 before forming the wiring. In this embodiment, the planarizing film 7 made of resin.
It is very important to flatten the step due to the TFT using 10. Since the light emitting layer formed later is very thin, the presence of a step may cause a light emission failure. Therefore, it is desirable to planarize the pixel electrode before forming it so that the light emitting layer can be formed as flat as possible.

After the wirings 701 to 707 are formed, a bank 712 is formed as shown in FIG.
The bank 712 may be formed by patterning an insulating film or organic resin film containing silicon of 100 to 400 nm.

Note that since the bank 712 is an insulating film, attention must be paid to electrostatic breakdown of elements during film formation. In this embodiment, carbon particles or metal particles are added to the insulating film that is the material of the bank 712 to reduce the resistivity and suppress the generation of static electricity. At this time, the resistivity is 1 × 10 ⁶ to 1 × 1.
0 ¹² [Omega] m (preferably ^{1 × 10 8 ~1 × 10 10} Ωm) may be adjusted the amount of the composed as carbon particles or metal particles.

A light emitting layer 713 is formed on the pixel electrode 711. Although only one pixel is shown in FIG. 16, in this embodiment, light emitting layers corresponding to the respective colors R (red), G (green), and B (blue) are separately formed. In this embodiment, a low molecular weight organic light emitting material is formed by a vapor deposition method.
Specifically, a copper phthalocyanine (CuPc) film having a thickness of 20 nm is provided as a hole injection layer, and a tris-8-quinolinolato aluminum complex (Alq ₃ ) having a thickness of 70 nm is formed thereon as a light emitting layer.
) A laminated structure provided with a film.
The emission color can be controlled by adding a fluorescent dye such as quinacridone, perylene, or DCM1 to Alq ₃ .

However, the above example is an example of an organic light emitting material that can be used as a light emitting layer, and it is not absolutely necessary to limit to this. A light emitting layer (a layer for emitting light and moving carriers therefor) may be formed by freely combining a light emitting layer, a charge transport layer, or a charge injection layer. For example, in this embodiment, an example in which a low molecular weight organic light emitting material is used as the light emitting layer is shown, but a high molecular weight organic light emitting material may be used. It is also possible to use an inorganic material such as silicon carbide for the charge transport layer or the charge injection layer.
Known materials can be used for these organic light emitting materials and inorganic materials.

Next, a cathode 714 made of a conductive film is provided on the light emitting layer 713. In this embodiment, an alloy film of aluminum and lithium is used as the conductive film. Of course, a known MgAg film (
An alloy film of magnesium and silver) may be used. As the cathode material, a conductive film made of an element belonging to Group 1 or Group 2 of the periodic table or a conductive film added with these elements may be used.

When the cathode 714 is formed, the light emitting element 715 is completed. Note that the light-emitting element 715 here refers to a diode formed of a pixel electrode (anode) 711, a light-emitting layer 713, and a cathode 714.

It is effective to provide a passivation film 716 so as to completely cover the light emitting element 715. As the passivation film 716, an insulating film including a carbon film, a silicon nitride film, or a silicon nitride oxide film is used, and the insulating film is used as a single layer or a combination thereof.

At this time, it is preferable to use a film with good coverage as the passivation film, and it is effective to use a carbon film, particularly a DLC (diamond-like carbon) film. Since the DLC film can be formed in a temperature range from room temperature to 100 ° C., it can be easily formed over the light-emitting layer 713 having low heat resistance. In addition, the DLC film has a high blocking effect against oxygen and can suppress oxidation of the light-emitting layer 713. Therefore, the problem that the light emitting layer 713 is oxidized during the subsequent sealing process can be prevented.

Further, a sealing material 717 is provided over the passivation film 716 and a cover material 718 is attached thereto. As the sealing material 717, an ultraviolet curable resin may be used, and it is effective to provide a substance having a hygroscopic effect or a substance having an antioxidant effect inside. In this embodiment, the cover material 718 is formed by forming a carbon film (preferably a diamond-like carbon film) on both surfaces of a glass substrate, a quartz substrate, or a plastic substrate (including a plastic film).

Thus, a light emitting device having a structure as shown in FIG. 16 is completed. Note that it is effective to continuously process the steps from the formation of the bank 712 to the formation of the passivation film 716 using a multi-chamber type (or in-line type) film formation apparatus without releasing to the atmosphere. . Further, it is possible to continuously process the process up to the step of bonding the cover material 718 without releasing to the atmosphere.

Further, in this embodiment, only the configuration of the pixel portion and the drive circuit is shown. However, according to the manufacturing process of this embodiment, other logic circuits such as a signal dividing circuit, a D / A converter, an operational amplifier, and a γ correction circuit are provided. Can be formed on the same insulator, and a memory and a microprocessor can also be formed.

Further, the light-emitting device of this example after performing the sealing (or sealing) process for protecting the light-emitting element will be described with reference to FIG. In addition, the code | symbol used in FIG. 16 is quoted as needed.

FIG. 17A is a top view showing a state in which the light-emitting element is sealed, and FIG.
It is sectional drawing which cut | disconnected 7 (A) by CC '. Reference numeral 801 indicated by a dotted line denotes a source side driver circuit, 806 denotes a pixel portion, and 807 denotes a gate side driver circuit. Reference numeral 901 denotes a cover material and 902.
Is a first sealing material, 903 is a second sealing material, and a sealing material 907 is provided on the inner side surrounded by the first sealing material 902.

Reference numeral 904 denotes a wiring for transmitting signals input to the source side driver circuit 801 and the gate side driver circuit 807, and receives a video signal and a clock signal from an FPC (flexible printed circuit) 905 serving as an external input terminal. Although only the FPC is shown here, a printed wiring board (PWB) may be attached to the FPC. The light emitting device in this specification includes not only the light emitting device body but also FPC or P
It shall include the state where WB is attached.

Next, a cross-sectional structure will be described with reference to FIG. A pixel portion 806 and a gate side driving circuit 807 are formed above the substrate 700, and the pixel portion 806 includes a current control TFT 60.
4 and a pixel electrode 711 electrically connected to its drain. The gate side driving circuit 807 includes an n-channel TFT 601 and a p-channel TFT 6.
It is formed using a CMOS circuit (see FIG. 16) combined with 02.

The pixel electrode 711 functions as an anode of the light emitting element. Further, banks 712 are formed at both ends of the pixel electrode 711, and the light emitting layer 713 and the cathode 714 of the light emitting element are formed on the pixel electrode 711.
Is formed.

The cathode 714 also functions as a wiring common to all pixels, and is connected to the FPC 9 via the connection wiring 904.
05 is electrically connected. Further, all elements included in the pixel portion 806 and the gate side driver circuit 807 are covered with a cathode 714 and a passivation film 567.

Further, a cover material 901 is bonded to the first seal material 902. Note that a spacer made of a resin film may be provided in order to secure a space between the cover material 901 and the light emitting element.
A sealing material 907 is filled inside the first sealing material 902. Note that an epoxy-based resin is preferably used as the first sealing material 902 and the sealing material 907. The first sealing material 902 is desirably a material that does not transmit moisture and oxygen as much as possible. further,
The sealing material 907 may contain a substance having a moisture absorption effect or a substance having an antioxidant effect.

The sealing material 907 provided so as to cover the light emitting element also functions as an adhesive for bonding the cover material 901. In this embodiment, FRP (Fiberglass-Reinforced Plastics), PVF (polyvinyl fluoride), Mylar, polyester, or acrylic can be used as the material of the plastic substrate 901a constituting the cover material 901.

In addition, after the cover material 901 is bonded using the sealing material 907, the second sealing material 903 is provided so as to cover the side surface (exposed surface) of the sealing material 907. The second sealing material 903 is the first sealing material 90.
The same material as 2 can be used.

By encapsulating the light emitting element in the sealing material 907 with the above structure, the light emitting element can be completely blocked from the outside, and a substance that promotes deterioration due to oxidation of the light emitting layer such as moisture and oxygen enters from the outside. Can be prevented. Therefore, a highly reliable light emitting device can be obtained.

In the light-emitting device manufactured as described above, since the internal stress of the gate electrode is controlled to a desired value, the stress exerted on the semiconductor film can be reduced, and the operating characteristics of the light-emitting device are greatly improved. Can be improved. And such a light-emitting device can be used as a display part of various electronic devices.

Note that this embodiment can be freely combined with Embodiment 2, Embodiment 3, or Embodiment 6.

The CMOS circuit and the pixel portion formed by applying the present invention can be used for various electro-optical devices (active matrix liquid crystal display device, active matrix EC display device, active matrix light emitting device). That is, the present invention can be implemented in all electronic devices in which these electro-optical devices are incorporated in the display unit.

Such electronic devices include video cameras, digital cameras, projectors, head-mounted displays (goggles type displays), car navigation systems, car stereos, personal computers, personal digital assistants (mobile computers, mobile phones, electronic books, etc.), etc. Can be mentioned. Examples of these are shown in FIGS.

FIG. 18A illustrates a personal computer, which includes a main body 3001, an image input unit 3002,
A display portion 3003, a keyboard 3004, and the like are included. The present invention can be applied to the display portion 3003.

FIG. 18B shows a video camera, which includes a main body 3101, a display portion 3102, and an audio input portion 31.
03, an operation switch 3104, a battery 3105, an image receiving unit 3106, and the like. The present invention can be applied to the display portion 3102.

FIG. 18C illustrates a mobile computer (mobile computer).
A camera unit 3202, an image receiving unit 3203, an operation switch 3204, a display unit 3205, and the like. The present invention can be applied to the display portion 3205.

FIG. 18D shows a goggle type display, which includes a main body 3301, a display portion 3302, an arm portion 3303, and the like. The present invention can be applied to the display portion 3302.

FIG. 18E shows a player using a recording medium (hereinafter referred to as a recording medium) on which a program is recorded. The main body 3401, a display portion 3402, a speaker portion 3403, and a recording medium 3404 are used.
Operation switch 3405 and the like. This player uses a DVD (Di as a recording medium).
gial Versatile Disc), CD, etc. can be used to enjoy music, movies, games and the Internet. The present invention can be applied to the display portion 3402.

FIG. 18F illustrates a digital camera, which includes a main body 3501, a display portion 3502, and an eyepiece portion 350.
3, an operation switch 3504, an image receiving unit (not shown), and the like. The present invention can be applied to the display portion 3502.

FIG. 19A shows a front type projector, which includes a projection device 3601 and a screen 36.
02 etc. are included. The present invention can be applied to a liquid crystal display device 3808 constituting a part of the projection device 3601 and other driving circuits.

FIG. 19B shows a rear projector, which includes a main body 3701, a projection device 3702, a mirror 3703, a screen 3704, and the like. The present invention can be applied to the liquid crystal display device 3808 constituting a part of the projection device 2702 and other driving circuits.

Note that FIG. 19C illustrates a projection device 3601 in FIGS. 19A and 19B.
3 is a diagram showing an example of a structure 3702. FIG. The projection devices 3601 and 3702 are light source optical systems 3.
801, mirrors 3802, 3804 to 3806, a dichroic mirror 3803, a prism 3807, a liquid crystal display device 3808, a phase difference plate 3809, and a projection optical system 3810. Projection optical system 2810 includes an optical system including a projection lens. Although the present embodiment shows a three-plate type example, it is not particularly limited, and for example, a single-plate type may be used. In addition, in the optical path indicated by the arrow in FIG.
You may provide optical systems, such as a film for adjusting a phase difference, and an IR film.

FIG. 19D shows an example of the structure of the light source optical system 3801 in FIG. In this embodiment, the light source optical system 3801 includes a reflector 3811 and a light source 38.
12, lens arrays 3813 and 3814, a polarization conversion element 3815, and a condenser lens 3816. Note that the light source optical system illustrated in FIG. 19D is an example and is not particularly limited.
For example, the practitioner may appropriately provide an optical system such as an optical lens, a film having a polarization function, a film for adjusting a phase difference, or an IR film in the light source optical system.

However, the projector shown in FIG. 19 shows a case where a transmissive electro-optical device is used, and an application example in a reflective electro-optical device and a light-emitting device is not shown.

FIG. 20A illustrates a mobile phone, which includes a main body 3901, an audio output unit 3902, and an audio input unit 39.
03, a display portion 3904, an operation switch 3905, an antenna 3906, and the like. The present invention can be applied to the display portion 3904.

FIG. 20B illustrates a portable book (electronic book), which includes a main body 4001 and display portions 4002 and 400.
3, a storage medium 4004, an operation switch 4005, an antenna 4006, and the like. The present invention can be applied to the display portions 4002 and 4003.

FIG. 20C illustrates a display, which includes a main body 4101, a support base 4102, and a display portion 4103.
Etc. The present invention can be applied to the display portion 4103. The display of the present invention is particularly advantageous when the screen is enlarged, and is advantageous for displays having a diagonal of 10 inches or more (particularly 30 inches or more).

As described above, the application range of the present invention is extremely wide and can be applied to electronic devices in various fields. Moreover, the electronic apparatus of a present Example is realizable even if it uses the structure which consists of what combination of Examples 2-7. In addition, the eighth embodiment can be applied to the electronic devices in FIGS.

Claims (2)

A light shielding film on the substrate;
A crystalline semiconductor film having a region overlapping with the light shielding film;
A gate electrode on the crystalline semiconductor film;
A first insulating film on the gate electrode;
A first wiring electrically connected to an impurity region of the crystalline semiconductor film through a first contact hole of the first insulating film;
A second insulating film on the first wiring;
A second wiring on the second insulating film;
A third insulating film on the second wiring;
A pixel electrode electrically connected to the first wiring through a second contact hole of the third insulating film;
The light shielding film overlaps with a channel formation region of the crystalline semiconductor film;
The second wiring has a light shielding property,
The second wiring is arranged in a mesh shape,
The semiconductor device according to claim 1, wherein the first contact hole is shifted from the second contact hole. In claim 1 ,
The semiconductor device according to claim 1, wherein the light shielding film has a conductive material common to a conductive material of the gate electrode.

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