JP2000058838A - Semiconductor device provided with semiconductor circuit composed of semiconductor element and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a semiconductor device provided with a semiconductor circuit composed of semiconductor elements which enhances TFT characteristics and has uniform characteristics, by a method wherein an interface between a region constituting an active layer, in particular a channel formation region, and a gate insulated film is formed superiorly, and its manufacture. SOLUTION: A catalytic element promoting crystallization annexed on a substrate 100 or an underlayer film, and an early semiconductor film 101 is continuously formed to a first gate insulated film 102a. Next, after the early semiconductor film 101 is crystallized by irradiation of infrared beams or ultraviolet beams (laser beams) via the first gate insulated film 102a, it is patterned to obtain an active layer and the first gate insulated film 102a having a desirable shape. Then, a second gate insulated film 102c is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a semiconductor device having a semiconductor circuit including a semiconductor element such as an insulated gate transistor and a method of manufacturing the same. In particular, the present invention relates to a structure of a semiconductor device including a semiconductor circuit including a semiconductor element having a wiring formed of a valve metal film and a method for manufacturing the same. The semiconductor device of the present invention includes not only elements such as thin film transistors (TFTs) and MOS transistors but also electro-optical devices such as display devices and image sensors having a semiconductor circuit composed of these insulated gate transistors. In addition, the semiconductor device of the present invention includes an electronic device equipped with the display device and the electro-optical device.

[0002]

2. Description of the Related Art Active matrix liquid crystal displays, in which a pixel matrix circuit and a driving circuit are formed by thin film transistors (TFTs) formed on an insulating substrate, have received attention. The liquid crystal display is 0.
A display of about 5 to 20 inches is used as a display.

At present, attention has been paid to a TFT using a crystalline semiconductor film represented by polysilicon as an active layer in order to realize a liquid crystal display capable of high-definition display. While a TFT using a crystalline semiconductor film as an active layer has a higher operation speed and a higher driving capability than a TFT using an amorphous semiconductor film represented by amorphous silicon as an active layer,
There is a problem that the variation in the electrical characteristics of each TFT is large.

[0004]

At present, high mobility is required for a TFT, and a crystalline semiconductor film having higher mobility than a semiconductor film having an amorphous structure is used as an active layer of the TFT. Is considered promising. Conventional TFTs are fabricated as outlined below.

[0005] First, an amorphous silicon film is formed on an insulating substrate, and the amorphous silicon film (amorphous silicon film) is subjected to crystallization treatment such as heating or laser light irradiation to form a polysilicon film (polycrystalline film). (Silicon film) is formed. Next, after the polysilicon film is patterned into a desired shape, a gate insulating film and a gate electrode forming material layer are deposited thereon, and these are patterned to form a gate electrode. Next, an impurity imparting conductivity is selectively introduced into the polysilicon film to form an impurity region serving as a source region and a drain region. Subsequently, an interlayer insulating film is deposited,
After forming a contact hole for exposing the source region and the drain region, a metal film is formed, and the metal film is patterned to form a metal wiring in contact with the source region and the drain region. Thus, the manufacturing process of the TFT is completed.

As described above, in the related art, after forming a semiconductor film having an amorphous structure, several steps (for example, a crystallization step and a patterning step) are performed, and then a gate insulating film is formed.

For this reason, before the formation of the gate insulating film, the surface of the crystalline semiconductor film which becomes an active layer may have impurities (such as oxygen,
Moisture or the like) or impurities generated in a process before the formation of the gate insulating film. When a gate insulating film is formed over the contaminated or oxidized crystalline semiconductor film, the interface characteristics between the active layer, particularly the channel formation region and the gate insulating film, are reduced, and the electrical characteristics of the TFT vary or decrease. Was causing it.

According to the present invention, a semiconductor element is provided which improves the characteristics of a TFT and has uniform characteristics by improving the interface between an active layer, particularly a region forming a channel forming region, and a gate insulating film. A semiconductor device provided with a semiconductor circuit and a manufacturing method thereof are provided.

[0009]

In order to achieve the above object, the present invention provides a method for manufacturing a semiconductor device, comprising the steps of: adding a catalyst element for promoting crystallization to a substrate or an underlayer to at least a part thereof; Forming a gate insulating film continuously;
After crystallization of the amorphous semiconductor film by irradiation of infrared light or ultraviolet light (laser light) through the gate insulating film, patterning is performed to form an active layer having a desired shape and a first gate. One feature is that a second gate insulating film is formed after obtaining the insulating film.

Further, according to the present invention, an initial semiconductor film and a first gate insulating film are continuously formed on an insulating surface, and infrared light or ultraviolet light (laser light) is not continuously exposed to the atmosphere. Another feature is that after crystallization by irradiation of GaN, patterning is performed to obtain an active layer having a desired shape and a first gate insulating film, and then a second gate insulating film is formed.

[0011] In the present specification, to form a film continuously means that:
Refers to the sequential formation of films without exposure to air while maintaining a high vacuum.For example, moving between chambers without exposure to air to form films continuously, or within the same chamber Refers to continuously forming a film by changing the reaction gas without exposing it to the atmosphere.

A first configuration of the present invention disclosed in the present invention is as follows.
An active layer made of a crystalline semiconductor film on an insulating surface, a first insulating film on the active layer, a second insulating film on the first insulating film, and the second insulating film A semiconductor device including a semiconductor circuit including a semiconductor element, which includes an upper gate wiring.

Another configuration of the present invention (second configuration)
Are an active layer made of a crystalline semiconductor film on an insulating surface, a first insulating film on the active layer, and a film thickness on the first insulating film as compared with the first insulating film. A second insulating film having a large thickness, and a gate wiring on the second insulating film.

Another configuration of the present invention (third configuration)
An active layer made of a crystalline semiconductor film on an insulating surface, a first insulating film on the active layer, a second insulating film having the same pattern shape as the first insulating film, A semiconductor device comprising a semiconductor circuit including a semiconductor element, wherein the semiconductor device includes a gate wiring on the second insulating film.

In each of the above structures, the crystalline semiconductor film may include a step of adding a catalytic element for promoting crystallization to the initial semiconductor film, and a step of adding the initial semiconductor film on the insulating surface to the first semiconductor film.
At least through a step of continuously forming an insulating film and a step of irradiating infrared light or ultraviolet light through the first insulating film to crystallize the initial semiconductor film without melting the film. It is characterized by being a formed crystalline semiconductor film.

In each of the above structures, the catalyst element is N
It is characterized by being at least one element selected from i, Fe, Co, Pt, Cu, Au and Ge.

In each of the above structures, the initial semiconductor film is an amorphous semiconductor film or a microcrystalline semiconductor film.

In each of the above structures, the impurity concentration at the interface between the first insulating film and the active layer is the first impurity concentration.
Is characterized by being lower than the impurity concentration at the interface between the insulating film and the second insulating film.

In each of the above structures, the gate wiring has a single layer or a laminated structure, and is made of a material mainly composed of one kind of element selected from aluminum, tantalum, molybdenum, titanium, chromium, and silicon. Characterized by having a layer consisting of

In each of the above structures, the thickness of the first insulating film is 1 to 50 nm. Further, in any of the above structures, the semiconductor device includes a semiconductor circuit including a semiconductor element, wherein the thickness of the second insulating film is 100 to 200 nm.

In each of the above structures, the active layer includes a source region, a drain region, and a channel forming region formed between the source region and the drain region.

In each of the above structures, at least a part of the source region and the drain region is made of silicide.

Each of the above structures is characterized in that the source region and the drain region are doped with an impurity imparting N-type conductivity.

Each of the above structures is characterized in that the source region and the drain region are doped with an impurity imparting an N-type conductivity and an impurity imparting a P-type conductivity.

In each of the above structures, the channel forming region contains a catalytic element for promoting crystallization of silicon,
The concentration of the catalytic element is higher in the source region and the drain region than in the channel formation region.

Further, a first configuration of the manufacturing method of the present invention disclosed in the present invention includes a step of contacting at least a part of a base film having an insulating surface with a catalytic element which promotes crystallization; A step of continuously forming an initial semiconductor film and a first insulating film; and irradiating infrared light or ultraviolet light through the first insulating film to crystallize the initial semiconductor film, thereby forming a crystalline semiconductor. Obtaining a film; patterning the crystalline semiconductor film and the first insulating film so that an end surface of the initial semiconductor film and an end surface of the first insulating film are aligned; Forming a second insulating film covering the insulating film, forming a gate wiring on the insulating film, and forming the first insulating film and the second insulating film in the same pattern shape. Circuit comprising a semiconductor element having A method for manufacturing a semiconductor device including.

A second structure of the manufacturing method of the present invention disclosed in the present invention comprises a step of contacting at least a part of a base film having an insulating surface with a catalytic element for promoting crystallization; A step of continuously forming an initial semiconductor film and a first insulating film; and irradiating infrared light or ultraviolet light through the first insulating film to crystallize the initial semiconductor film, thereby forming a crystalline semiconductor. Obtaining a film; patterning the crystalline semiconductor film and the first insulating film so that an end surface of the initial semiconductor film and an end surface of the first insulating film are aligned; Forming a second insulating film covering the insulating film, forming a gate wiring on the insulating film, and selectively removing the first insulating film and the second insulating film. To expose regions that should be source or drain regions And a step of doping a region to be the source region or the drain region with a phosphorus element, and a step of performing a heat treatment to getter the catalyst element. 3 illustrates a method for manufacturing a semiconductor device.

In the first structure or the second structure of the above manufacturing method, the step of obtaining a crystalline semiconductor film is characterized in that the initial semiconductor film is crystallized without melting the initial semiconductor film.

[0029]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a simplified sectional view showing an embodiment of a semiconductor device and a method of manufacturing the same according to the present invention.

First, a substrate 100 is prepared. Substrate 100
Examples thereof include an insulating substrate such as a glass substrate, a quartz substrate, a crystalline glass, a ceramic substrate, and a plastic substrate; a semiconductor substrate having a base film (eg, a silicon substrate); and a metal substrate (eg, a stainless steel substrate). .

Next, a base film 10 having an insulating surface is formed on the substrate 100. As the base film 10, a silicon oxide film, a silicon nitride film, a silicon nitride oxide film (SiO _x N _y ), a stacked film thereof, or the like can be used. The formation method of the base film is a known technique, for example, a low pressure CVD method, a thermal CV method.
A method D, a plasma CVD method, a sputtering method, or the like can be used.

Next, a catalytic element for promoting crystallization of the semiconductor material is added on the entire surface or selectively on the substrate or the underlying film. As a method for adding a catalyst element, a sputtering method, a CVD method, a plasma treatment method, an adsorption method, an ion implantation method, or a method of applying a solution containing a catalyst element can be used. (FIG. 1 (A)) Fe, Co, Ni, Ru, Rh, P
One or more selected from d, Os, Ir, Pt, Cu, and Au can be used. Ge and Pb, which are catalytic elements of the lattice substitution type (or the melting type), can also be used. By using this technique, a crystalline semiconductor film can be manufactured by a low-temperature process. Here, an example in which nickel (Ni) is used as a catalyst element will be specifically described.

Subsequently, an initial semiconductor film 101 and a first gate insulating film 102a are continuously formed. (FIG. 1 (B))

In this specification, the term “initial semiconductor film” is a general term for a semiconductor film, and is typically a semiconductor film having an amorphous property, for example, an amorphous semiconductor film (such as amorphous silicon), Refers to an amorphous semiconductor film and a microcrystalline semiconductor film having microcrystals, and these semiconductor films are a Si film, a Ge film, and a compound semiconductor film [for example, represented by Si _x Ge _1-x (0 <X <1). Amorphous silicon germanium film). This initial semiconductor film is formed by a known technique, for example, low pressure CVD.
Method, thermal CVD method, PCVD method, or the like can be used.

As the first gate insulating film 102a, a silicon oxide film, a silicon nitride film, a silicon nitride oxide film (SiO 2
_X N _y), or 1nm~50nm these laminated films such as
Can be used. The first gate insulating film may be formed by a known technique, for example, a low pressure CVD method or a heat C method.
A VD method, a PCVD method, a sputtering method, or the like can be used. In addition, as the first gate insulating film, an oxide film obtained by plasma oxidation or thermal oxidation of the initial semiconductor film 101, or a nitride film obtained by plasma nitridation or the like can be used.

In the present invention, after the initial semiconductor film was formed, excellent interface characteristics could be obtained by continuously forming the first gate insulating film without exposing it to the air. In addition, it is preferable that the stress between the layers be reduced by making the temperature at the time of formation the same. In addition, in the above-described continuous formation, in order to reduce the hydrogen concentration in the initial semiconductor film, a step of forming a film at a deposition temperature of 400 to 500 ° C. or after the above-described continuous formation Preferably, a step of applying a heat treatment is performed.

Next, crystallization by irradiation of infrared light or ultraviolet light through the first gate insulating film 102a (hereinafter referred to as crystallization)
Laser crystallization), and the amorphous semiconductor film 101 is crystallized to form a crystalline semiconductor film 103. (FIG. 1 (C)) It is preferable that the step of irradiating the infrared light or the ultraviolet light is also performed continuously without being exposed to the atmosphere.

[0038] In this specification, a crystalline semiconductor film is a general term for a semiconductor film having an order in structure, such as a single crystal semiconductor film, a polycrystalline semiconductor film (such as a polycrystalline silicon film), and a microcrystalline semiconductor film. It refers to a crystalline semiconductor film, or a semiconductor film having a partially ordered structure.

When ultraviolet light is used as the crystallization technique, excimer laser light or strong light generated from an ultraviolet lamp may be used. When infrared light is used, infrared laser light or strong light generated from an infrared lamp may be used. I just need. Here, crystal growth proceeds as the catalyst element (Ni) diffuses from the interface between the base film and the amorphous semiconductor film. Also, depending on the conditions of laser crystallization,
When the amorphous semiconductor film is crystallized after passing through a molten state, or when the amorphous semiconductor film is crystallized in a solid state without melting or in an intermediate state between a solid phase and a liquid phase There is. Considering the thickness of the first gate insulating film, the thickness of the amorphous semiconductor film, the substrate temperature, and the like, the conditions for laser crystallization (wavelength of laser light, irradiation intensity, pulse width,
Repetition frequency, irradiation time, etc.) are appropriately adjusted. In addition,
After the laser crystallization, a step of performing a hydrogenation treatment using a known method may be employed.

Next, the first gate insulating film and the crystalline semiconductor film are patterned to have desired shapes to obtain an active layer 104 composed of the first gate insulating film 102b and the crystalline semiconductor film. (Fig. 1 (D))

Next, a second gate insulating film 102c is formed to cover the entire surface of the substrate. (FIG. 1E) As the second gate insulating film, a silicon oxide film, a silicon nitride film, a silicon nitride oxide film (SiO _X N _y ), a laminated film of these, or the like is used.
It can be used in a thickness range of 0 nm to 200 nm.

Next, a conductive film 105 is formed. (Figure 2
(A)) For the conductive film 105, aluminum or a material mainly containing aluminum is 200 to 500 nm.
Can be used. Further, a material mainly composed of a valve metal, for example, tantalum (Ta), niobium (Nb), hafnium (Hf), zirconium (Z
r), a material containing titanium (Ti), chromium (Cr) or the like as a main component can be used. Further, the conductive film may have a stacked structure of tantalum containing nitrogen (TaN), tantalum (Ta), and tantalum containing nitrogen (TaN). Here, an example in which an aluminum film is used as the conductive film will be specifically described.

In this specification, the term "valve metal" refers to a metal in which a barrier type anodic oxide film formed as an anode allows a cathode current to flow but does not allow an anode current to flow, that is, a metal exhibiting a valve action. (Electrochemical Handbook, 4th edition; edited by The Electrochemical Society, P
370, Maruzen, 1985)

Next, a resist mask 106 is formed and the conductive film 105 is patterned to form a wiring layer 107a. (FIG. 2B) The second wiring layer 107a
Constitutes the upper layer of the gate wiring.

Next, a first anodic oxidation is performed by bringing the probe of the anodic oxidation device into contact with the conductive film 107a while leaving the resist mask 106. (FIG. 2C) In the first anodic oxidation, a porous anodic oxide (porous alumina) 108 is formed on the side surface of the wiring layer 107b.

Next, after removing the resist mask 106, the probe of the anodic oxidation device is again brought into contact with the conductive film to perform second anodic oxidation. (FIG. 2D) In this second anodic oxidation, a barrier type anodic oxide (nonporous alumina) 109 is formed on the surface of the wiring layer 107c.

Next, using the wiring layer and its anodic oxide as a mask, the first and second gate insulating films are etched to form a first gate insulating film 110 and a second gate insulating film 1.
11 is formed. (FIG. 3 (A))

Next, while removing the porous anodic oxide 108 and exposing the surface of the active layer 104, impurity ions for imparting conductivity are added to the active layer to form a source region or a drain region. Then, P-type or N-type high-concentration impurity regions 115 and 116 and P-type or N-type low-concentration impurity regions 117 and 118 to be LDD regions are formed.
(FIG. 3B) Addition of ions may be performed by a known means such as an ion implantation method, a plasma doping method, or a laser doping method. Here, an example in which boron is used as an impurity for imparting P-type conductivity and phosphorus is used as an impurity for imparting N-type conductivity will be specifically described.

Thereafter, heat treatment is performed in an inert atmosphere or a dry oxygen atmosphere at 450 ° C. or more for 0.5 to 12 hours, and in this embodiment, 550 ° C. for 2 hours. (FIG. 3
(C))

In the above heating step, Ni intentionally added for crystallization of the amorphous silicon film is removed from the channel forming region to each source region as schematically shown by arrows in FIG. And to the drain region. This is because these regions contain a high concentration of phosphorus element, and Ni that reaches these source and drain regions is captured (gettered) there. 400-600 ° C, 0.5
The heat treatment for up to 4 hours can sufficiently getter Ni.

As a result, the Ni concentration in the channel formation region
Can be reduced. In the channel formation region 119
Ni concentration is 5 × 10, which is the lower limit of detection of SIMS.¹⁷atoms
/ Cm ^ThreeIt can be: Gettering on the other hand
Source and drain regions 115, 1 used for the sink
16 has a higher Ni concentration than the channel formation region.
(FIG. 3C) By this process, the source area and the
Activation effect in the drain and drain regions,
To recover the crystal structure of the active layer damaged by the polishing process
be able to.

Finally, an interlayer insulating film 120 is formed, a contact hole for exposing the source region and the drain region is formed, a metal film is formed, and the metal film is patterned to make contact with the source region and the drain region. Metal wiring 12
1, 122 are formed. (FIG. 3D) Thus, the fabrication of the TFT according to the embodiment of the present invention is completed.

FIG. 4 is a sectional view of FIG. 3C. FIG. 3C is the same as FIG.
FIG. 4A is a cross-sectional structural view taken along the ZZ ′ plane in FIG.
Is equivalent to Note that the planar shape shown in FIG.
Simplified as a rectangular shape. Further, X in FIG.
FIG. 4B is a cross-sectional structural view taken along the −X ′ plane.
FIG. 4C is a cross-sectional structural view taken along the line YY ′ in FIG.
Is equivalent to

[0054]

Embodiments of the present invention will be described below, but it is needless to say that the present invention is not limited to these embodiments.

[Embodiment 1] An example of the structure of a semiconductor device provided with a semiconductor circuit comprising a semiconductor element using the present invention will be described with reference to FIG. Note that a semiconductor device according to the present invention includes a peripheral driver circuit portion and a pixel matrix circuit portion on the same substrate. In this embodiment, for the sake of simplicity of illustration, a CMOS circuit forming part of a peripheral driving circuit portion and a pixel TFT (N-channel TFT) forming part of a pixel matrix circuit portion are shown on the same substrate. Have been.

FIG. 9 is a diagram corresponding to the top view of FIG. 8. In FIG. 9, the portion cut along the dotted line AA '
8 corresponds to the sectional structure of the pixel matrix circuit shown in FIG.
The portion cut at -B 'corresponds to the cross-sectional structure of the CMOS circuit in FIG. FIG. 10 is a schematic perspective view of an active matrix substrate including a peripheral driver circuit portion and a pixel matrix circuit portion on the same substrate. The active matrix substrate includes a pixel matrix circuit 601, a scan line driver circuit 602, and a signal line driver circuit 6 formed on the substrate 300.
The scanning line driving circuit 602 and the signal line driving circuit 603 are connected to the pixel matrix circuit 601 by the scanning line 520 and the signal line 530, respectively. Scan line,
In the vicinity of the intersection of the signal lines, the pixels TF connected to each wiring
T500 is formed, and a pixel electrode 550,
The additional capacity 560 is connected.

In FIG. 8, all TFTs (thin film transistors) are formed on a base film 301 provided on a substrate 300. P-channel type TFT for CMOS circuit
In this case, the P-type high-concentration impurity regions (source region or drain region) 801 and 802 as the active layer, the channel formation region 803, and the low-concentration impurity region between the high-concentration impurity region and the channel formation region. 804 and 805 are formed. And on the channel forming region,
First gate insulating film 405 and second gate insulating film 408
The gate wiring 407 is formed via the laminated film of FIG.
The gate wiring is protected by a barrier type anodic oxide 409. A contact hole is formed in the first interlayer insulating film 310 covering it, and a wiring 432 is formed in the high-concentration impurity region.
433 is connected thereto, and the second interlayer insulating film 3 is further formed thereon.
20 is formed, a lead-out wiring 442 is connected to the wiring 432, and a third interlayer insulating film 330 is formed so as to cover the lead-out wiring 442.

On the other hand, the N-channel type TFT includes N-type high-concentration impurity regions (source or drain regions) 806 and 807 as active layers, a channel formation region 809,
Low concentration impurity regions 810 and 811 are formed between the high concentration impurity region and the channel formation region. Wirings 431 and 433 are connected to the high-concentration impurity region, and a lead-out wiring 441 is connected to the wiring 431. Portions other than the active layer have substantially the same structure as the P-channel TFT.

The N-channel TFT formed in the pixel matrix circuit has the same structure as the N-channel TFT of the CMOS circuit up to the portion where the first interlayer insulating film is formed. Wirings 530 and 532 are connected to the high-concentration impurity regions 811 and 813, and a wiring 532 is connected to the high-concentration impurity regions 813. A second interlayer insulating film 320 is formed thereon, and a black mask is formed. 541 are formed. This black mask covers the pixel TFT and forms an auxiliary capacitance with the wiring 532. Further, a third interlayer insulating film 330 is formed thereon, and a pixel electrode 550 made of a transparent conductive film such as ITO is connected. In this embodiment, the gate electrode of the pixel TFT of the pixel matrix circuit has a double gate structure. However, a multi-gate structure such as a triple gate structure may be used in order to reduce variation in off current. Further, a single gate structure may be used to improve the aperture ratio.

In the structure of the present invention, (carbon, nitrogen, and the like) at the interface between the channel formation region and the first gate insulating film.
It is characterized in that the impurity concentration is lower than the impurity concentration at the interface between the first gate insulating film and the second gate insulating film (oxygen, Na, Fe, Cr, Al, Ta, etc.). In particular, channel forming regions 413 and 42 of each TFT
3, 514, 515 and first gate insulating films 405, 50
The concentration of impurities such as carbon, nitrogen, and oxygen at the interface with C.5 is 1 × 10 ¹⁹ atoms / cm ³ or less, preferably 1 × 10 ¹⁶ at
The impurity concentration could be controlled to be oms / cm ³ . The concentrations of the alkali metal impurities (such as Na) and metal impurities (such as Fe and Cr) could be controlled to 1 × 10 ¹⁵ atoms / cm ³ or less. The catalyst element (Ni) used for crystallization could be reduced to 5 × 10 ¹⁷ atoms / cm ³ or less. Here, the impurity concentration is defined by the lowest value of the SIMS data.

Hereinafter, an example of a method for manufacturing a semiconductor device of the present invention will be described in detail with reference to FIGS.

First, a substrate 300 having an insulating surface is prepared. In this embodiment, a glass substrate (Corning 1737; strain point 667 ° C.) was used as the substrate 300. A silicon oxide film having a thickness of 200 nm
It formed with the film thickness of. Next, a Ni acetic acid solution was applied using a spinner and further dried to form a Ni layer 31.
(FIG. 6A) However, the Ni layer does not form a complete layer. The Ni concentration of the Ni acetic acid solution is 1 in terms of weight.
To 1000 ppm. In this embodiment, it is set to 100 ppm. In this state, Ni is held on the surface of the base film. In this embodiment, the coating method using a solution is used, but Ni can be held on the surface of the base film by using ion implantation or sputtering.

Next, an initial semiconductor film 302 and a first gate insulating film 303a were formed continuously. (FIG. 6B) In this embodiment, a chamber dedicated to forming an amorphous silicon film is provided.
A chamber dedicated to forming the first gate insulating film was prepared, and the chambers were continuously formed by moving each chamber while maintaining a high vacuum. In this embodiment, the reduced pressure thermal CVD
An initial semiconductor film made of an amorphous silicon film having a thickness of 50 nm is formed using disilane (Si ₂ H ₆ ) as a film forming gas by a deposition method, and a first oxide film made of a 20 nm film is formed by a low pressure thermal CVD method. A gate insulating film was formed. Note that the impurity concentration was controlled such that the concentration of impurities such as carbon, nitrogen, and oxygen in the initial semiconductor film 302 was 5 × 10 ¹⁸ atoms / cm ³ or less.

Subsequently, the amorphous silicon film 302 was crystallized by irradiating ultraviolet light or infrared light with the first gate insulating film 303a on the upper surface to obtain a crystalline silicon film 304. (FIG. 6 (C)) Note that it is preferable that the irradiation of ultraviolet light or infrared light be continuously performed without exposure to the atmosphere. In this embodiment, the XeCl laser light (λ = 308n)
m) was used. In this example, a crystalline semiconductor film was obtained by irradiating a pulsed laser beam under crystallization conditions under which the initial semiconductor film was not melted and growing crystals from a catalytic element.
In this crystallization step, first, nucleation with nickel silicide as a nucleus occurs, the nucleus gradually grows, and the entire film is crystallized.

Next, as shown in FIG. 6D, the crystalline silicon film and the first gate insulating film are patterned by using a dry etching method to form an active layer 305 and a first gate insulating film 303b. did.

Next, after a second gate insulating film 303b having a thickness of 100 nm is formed to cover the entire surface of the substrate, a conductive film containing 2 wt% of scandium and having a thickness of 40 nm is formed.
1 film is formed. Then, a resist mask 308 was formed, the Al film was patterned, and a wiring layer 307 was formed. (FIG. 6 (A))

Next, while the resist mask 308 was left, the probe of the anodizing apparatus was brought into contact with the Ta film to perform first anodizing. Anodizing conditions are 3
% Oxalic acid aqueous solution (temperature: 10 ° C.)
V, a voltage application time of 40 minutes, and a supply current of 20 mA / 1 substrate. Through this step, a porous anodic oxide 309 was formed. Next, after removing the resist mask 308, the probe of the anodic oxidation apparatus was again brought into contact with the Ta film to perform second anodic oxidation. The anodizing conditions were as follows: an ethylene glycol solution containing 3% tartaric acid was used as the electrolytic solution, the electrolytic solution temperature was 10 ° C., the ultimate voltage was 80 V, the voltage application time was 30 minutes, and the supply voltage was 30 mA / 1 substrate. Through this step, barrier anodic oxides 409 and 509 were formed. (FIG. 6 (B))

Next, 303a-c and 306 are selectively removed using the wiring layer and its anodic oxide as a mask,
The first gate insulating films 405 and 505 and the second gate insulating films 408 and 508 are formed, and the surfaces of the active layers serving as source and drain regions are exposed. (FIG. 6
(C))

Next, the porous anodic oxide 309 is removed by etching by a known method, and phosphorus, which is a kind of impurity ions imparting N-type conductivity, is added to the active layer by ion implantation. N-type high concentration impurity region 51
1 to 513, 411, and 412, the phosphorus concentration is 1 × 10
²⁰ to 8 × 10 ²¹ atoms / cm ³ , the N-type low-concentration impurity regions 516 to 519, 414, and 415 have a phosphorus concentration of 1 ×
It is adjusted to be 10 ¹⁵ to 1 × 10 ¹⁷ atoms / cm ³ . Next, the N-channel TFT is covered with a resist (not shown), and boron, which is a kind of impurity ions imparting P-type conductivity, is similarly formed by an ion implantation method in the active layer (421, 422, 424, 425). Area shown)
Was added. (FIG. 7A) The dose of boron is such that the concentration of boron ions in the p-type impurity regions 421 and 422 is N.
The concentration is set to about 1.3 to 2 times the concentration of phosphorus ions added to the impurity regions 511 to 513, 411, and 412 of the mold. Note that the method of adding phosphorus ions or boron ions in this embodiment is a known method, for example, an ion implantation method, a plasma doping method, a method of applying a solution containing phosphorus ions or boron ions, and then heating the film, a film containing phosphorus ions or boron ions. Is performed by using a method of heating after forming.

The regions into which the phosphorus ions and boron ions have not been implanted become intrinsic or substantially intrinsic channel forming regions 413, 423, 423, 423 and 423, which will later become carrier movement paths.
514 and 515.

In this specification, the term “intrinsic” refers to a region that does not contain any impurity that can change the Fermi level of silicon, and a substantially intrinsic region is a region in which electrons and holes are perfectly balanced and conductive. The region where the molds are offset, that is, the concentration range in which the threshold can be controlled (1 × 10 ¹⁵ to 1 × 10 ¹⁷ atoms)
/ Cm ³ ) indicates a region containing an impurity imparting N-type or P-type, or a region in which the conductivity type is offset by intentionally adding an impurity of the opposite conductivity type.

Thereafter, heat treatment was performed at 450 ° C. or more for 0.5 to 12 hours, in this example, 550 ° C. for 2 hours in an inert atmosphere or a dry oxygen atmosphere. (FIG. 7
(B))

In the above heating step, Ni intentionally added for crystallization of the amorphous silicon film is removed from the channel forming region to each source region as schematically shown by arrows in FIG. 7B. And to the drain region. This is because these regions contain a high concentration of phosphorus element, and Ni that reaches these source and drain regions is captured (gettered) there. 400-600 ° C, 0.5
The heat treatment for up to 4 hours can sufficiently getter Ni.

As a result, the Ni concentration in the channel formation region can be reduced while activating the impurity ions. Channel forming regions 803, 809, 814,
The Ni concentration in 815 is 5 × 1, which is the lower limit of SIMS detection.
0 ¹⁷ atoms / cm ³ or less. On the other hand, the Ni concentration in the source region and the drain region used for the gettering sink is higher than that in the channel formation region. (FIG. 8)

After that, a metal film for silicidation is provided, and a heat treatment is performed, so that 801, 802, 806, 80
After silicidation of the regions indicated by 7, 811 to 813, it is preferable to remove only the metal film. By adding this step, the resistance of the source region and the drain region can be reduced, and an operation frequency on the order of several GHz can be realized. As the metal film for silicidation, a film made of a material containing cobalt, titanium, tantalum, tungsten, molybdenum, or the like as a main component can be used.

Then, a first interlayer insulating film is formed on the entire surface of the substrate with a silicon oxide film. Here, a first interlayer insulating film 310 having a thickness of 1 μm is formed by a CVP method. Further, as a material of another interlayer insulating film, a silicon nitride film, a silicon oxynitride film, a transparent organic resin film, for example, an acrylic resin,
Polyimide and BCB (benzocyclobutene) can be used.

Then, a contact hole is formed,
A metal film (not shown) for forming a contact electrode is formed. Here, a three-layer film of a titanium film, an aluminum film, and a titanium film is formed as the metal film by a sputtering method. Then, wirings 530, 532, 431 to 433 are formed by patterning the metal film.

Next, an organic resin film is formed as a second interlayer insulating film 320 to a thickness of 1 μm by spin coating. Then, in order to form an additional capacitance, only a predetermined portion 540 is etched and thinned. Then, a 300 nm thick metal film made of Ti was formed. The metal film was patterned to form a black mask 541 and lead wires 441 and 442.

Then, a third interlayer insulating film 330 is formed of an acrylic resin. Here, a 1 μm-thick third interlayer insulating film 330 is formed by spin coating. When a resin film is used, its surface can be flattened as shown.

Next, a contact hole is formed, and a pixel electrode 550 is formed. Here, first, the ITO film is
A film having a thickness of 0 nm is formed by a sputtering method and is patterned to form a pixel electrode 550.

Finally, in a hydrogen atmosphere at 350 ° C.,
Heat treatment for one hour is performed to reduce defects in the semiconductor layer. Thus, the state shown in FIG. 8 is obtained.

The TFT structure shown in this embodiment is an example of a top gate type, and is not particularly limited to the structure of this embodiment. It is easy to apply to a bottom gate type. Further, in this embodiment, an example in which a transmission type LCD is manufactured is shown, but this is merely an example of a semiconductor device. It is to be noted that the reflection type LCD can be easily manufactured by forming the pixel electrode with a highly reflective metal film instead of ITO and changing the patterning of the pixel electrode appropriately by an operator. When a reflective LCD is manufactured, when a structure in which an insulating film is stacked over a heat-resistant metal film or a structure in which an insulating film is stacked over aluminum nitride is used as a base film, the metal film below the insulating film serves as a heat dissipation layer. Working and effective.
In addition, it is possible for a practitioner to change the above process order as appropriate.

[Embodiment 2] This embodiment is an example of obtaining a crystalline silicon film by a method different from that of Embodiment 1. In this embodiment, in the step of continuously forming the initial semiconductor film and the first gate insulating film, the first gate insulating film is formed at a forming temperature of 400 to 500 ° C., and then the crystalline silicon is formed by laser crystallization. It relates to a method for obtaining a membrane. The basic configuration is almost the same as that of the first embodiment. Therefore, only the differences will be described.

In this embodiment, an initial semiconductor film, here, a semiconductor film having an amorphous structure (film thickness 50 using RF @ PCVD) is used.
nm amorphous silicon film) and a first gate insulating film. At this time, the formation temperature of each film is set to 400 to 500.
° C and 450 ° C in this example, all the forming temperatures were controlled to be the same. With such a formation temperature, the heat treatment of the base film and the treatment for reducing the hydrogen concentration (dehydrogenation) in the amorphous semiconductor film were performed at the same time as the formation. Further, simultaneously with the formation of the first gate insulating film, a nucleus was grown in a semiconductor film having an amorphous structure. Also, by setting the same forming temperature, the stress between the stacked films could be reduced.

After that, when a laser beam was irradiated through the first gate insulating film, the entire film was rapidly crystallized, and a crystalline silicon film was obtained. Further, instead of laser light irradiation, strong light irradiation, for example, RTA or RTP may be used. In this example, a crystalline silicon film was obtained using an excimer laser beam having a wavelength of 308 nm. In Example 1, a crystalline semiconductor film was obtained by irradiating a pulsed laser beam under the condition that the amorphous semiconductor film was not melted to grow a crystal.

The subsequent steps are the same and will not be described.
By doing so, a TFT having good TFT characteristics could be manufactured.

[Embodiment 3] This embodiment is an example in which a crystalline silicon film is obtained by a method different from that of the embodiment 1. The present embodiment relates to a method of forming a laser beam shape into a rectangle or a square, and obtaining a crystalline silicon film by uniform laser crystallization in a region of several cm ² to several hundred cm ² by one irradiation. The basic configuration is almost the same as that of the first embodiment. Therefore, only the differences will be described.

In this embodiment, after the formation of the base film, the amorphous silicon film and the first gate insulating film are successively formed. afterwards,
The crystalline silicon film was obtained by irradiating an excimer laser beam (wavelength: 248 to 308 nm) in an inert or oxidizing atmosphere. Note that the heat treatment may be performed at the same time. Further, instead of laser light irradiation, strong light irradiation, for example, RTA or RTP may be used.

In this embodiment, a laser beam having a wavelength of 248 nm is shaped into a rectangle or a square, and a single irradiation is performed using a uniform laser device (SAELC manufactured by Sopra) in an area of several cm ² to several hundred cm ^2. Thus, a crystalline silicon film was obtained. This laser device is capable of annealing a large area with a single shot and has a large output energy, so that nucleus growth and crystallization of the entire film can be performed.

The subsequent steps are the same and will not be described.
By doing so, a TFT having good TFT characteristics could be manufactured.

This embodiment can be combined with the second embodiment.

[Embodiment 4] This embodiment is an example in which a crystalline silicon film and a first gate insulating film are obtained by a method different from that of the first embodiment. In this embodiment, after the catalytic element is added to the base film, the microcrystalline semiconductor film and the first gate insulating film (plasma oxidation using oxygen gas to which He is added) are continuously performed.
To form In this step, the forming temperature is set to 400 to 5
The present invention relates to a method for obtaining a crystalline silicon film by laser crystallization after forming a first gate insulating film at 00 ° C. The basic configuration is almost the same as that of the first embodiment. Therefore, only the differences will be described.

In this embodiment, after a catalytic element (Ni) is added to a base film, an amorphous silicon film having microcrystals and a first gate insulating film (He and O ₂ are used for plasma oxidation). Silicon oxide film) was continuously formed. Note that a silicon oxynitride film formed using plasma nitriding may be used.

Thereafter, when a laser beam is irradiated through the first gate insulating film, microcrystals and a catalyst element (N
From i), the entire film was rapidly crystallized, and a crystalline silicon film was obtained. Further, instead of laser light irradiation, strong light irradiation, for example, RTA or RTP may be used.
In this example, a crystalline silicon film was obtained using an excimer laser beam having a wavelength of 308 nm. In Example 1, a crystalline semiconductor film was obtained by irradiating a pulsed laser beam under the condition that the amorphous semiconductor film was not melted to grow a crystal.

The subsequent steps are the same and will not be described. By doing so, a TFT having good TFT characteristics could be manufactured.

This embodiment can be combined with the second or third embodiment.

[Embodiment 5] In this embodiment, a first gate insulating film and a second gate insulating film are obtained by a method different from that of the first embodiment. The basic configuration is almost the same as that of the first embodiment. Therefore, only the differences will be described.

In this embodiment, after the catalytic element is added to the base film, an amorphous semiconductor film and a first gate insulating film (silicon nitride film) are continuously formed. Then, after a crystalline silicon film is obtained by laser crystallization, a second gate insulating film (silicon oxide film) is formed. In the present embodiment, a first gate insulating film made of a silicon nitride film (SiNx) formed by using PCVD as a reaction gas with SiH ₄ , NH ₃ , and N ₂ is formed, and TEO is formed using PCVD.
A second gate insulating film was formed using S and oxygen as reaction gases. It is also possible to form a silicon oxynitride film (SiOxN _y). Note that a gate insulating film including a stack of three or more layers may be used.

After the formation of the second gate insulating film, in the region of the circuit where high-speed driving is prioritized, the second gate insulating film was selectively removed to leave only the first gate insulating film. At this time, since the etching ratios of the first gate insulating film and the second gate insulating film are different, the first gate insulating film can be easily and selectively removed as an etching stopper. Note that a first gate insulating film and a second gate insulating film are stacked in a region of a circuit in which high breakdown voltage is prioritized.

By forming a gate insulating film composed of a stack of different film qualities as described above, the interface characteristics between the crystalline silicon film and the first gate insulating film can be improved, and the gate of the TFT can be selectively formed. The electric breakdown voltage of the insulating film can be improved.

The subsequent steps are substantially the same and will not be described. In this manner, TFTs having different gate insulating films can be manufactured on the same substrate.

This embodiment can be combined with Embodiments 2 to 4.

Embodiment 6 An AMLCD manufactured by bonding the active matrix substrate shown in Embodiments 1 to 5 to a counter substrate via a liquid crystal by a known technique is used as a display of various electronic devices. You. In addition,
The electronic device described in this embodiment is defined as a semiconductor device equipped with a semiconductor circuit.

Examples of such electronic devices include a video camera, a still camera, a projector, a projection TV, a head mounted display, a car navigation, a personal computer (including a notebook type), a portable information terminal (a mobile computer, a mobile phone, etc.), and the like. Is mentioned. Examples of those are shown in FIG.

FIG. 11A shows a mobile computer (mobile computer), which comprises a main body 2001, a camera section 2002, an image receiving section 2003, operation switches 2004, and a display device 2005. The present invention is applied to an image receiving unit 200.
3. Applicable to the display device 2005 and the like.

FIG. 11B shows a head mounted display, which comprises a main body 2101, a display device 2102, and a band section 2103. The present invention can be applied to the display device 2102.

FIG. 11C shows a portable telephone, and the main body 22 is provided.
01, audio output unit 2202, audio input unit 2203, display device 2204, operation switch 2205, antenna 220
6. The present invention can be applied to the audio output unit 2202, the audio input unit 2203, the display device 2204, and the like.

FIG. 11D shows a video camera, which includes a main body 2301, a display device 2302, an audio input unit 2303, an operation switch 2304, a battery 2305, and an image receiving unit 23.
06. The present invention can be applied to the display device 2302, the sound input unit 2303, and the image receiving unit 2306.

FIG. 11E shows a rear type projector, which includes a main body 2401, a light source 2402, a display device 2403,
Mirrors (polarizing beam splitters and the like) 2404, 240
5, a screen 2406. The invention can be applied to the display device 2403.

FIG. 11F shows a portable book, and the main body 25 is shown.
01, display devices 2502, 2503, storage medium 250
4. It is composed of an operation switch 2505 and an antenna 2506. The data stored in the storage medium (MD, DVD, or the like) or the data obtained from an antenna (for example, a satellite antenna or the like) is displayed. The present invention relates to display devices 2502, 25
03 can be applied.

As described above, the applicable range of the present invention is extremely wide, and can be applied to electronic devices in all fields. In addition, the present invention can be used for an electronic bulletin board, a display for advertising, and the like.

[Embodiment 7] The TFTs shown in the above embodiments 1 to 5 are examples applied to AMLCD.
The present invention can be applied to various other electro-optical devices and semiconductor circuits other than the CD.

As electro-optical devices other than AMLCD,
An EL (electroluminescence) display device, an image sensor, and the like can be given.

Further, as the semiconductor circuit, an arithmetic processing circuit such as a microprocessor composed of an IC chip,
High-frequency module (MMI) that handles input / output signals of mobile devices
C etc.).

As described above, the present invention provides an insulated gate type TFT.
The present invention can be applied to all semiconductor devices functioning with a circuit including.

[0116]

According to the semiconductor device using the present invention, the interface characteristics between the active layer, in particular, the channel formation region and the first gate insulating film can be improved. Obtainable.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating an example of a manufacturing process of the present invention (Embodiment);

FIG. 2 is a cross-sectional view illustrating an example of a manufacturing process of the present invention (Embodiment);

FIG. 3 is a cross-sectional view illustrating an example of a manufacturing process of the present invention (Embodiment);

FIG. 4 is an enlarged cross-sectional view showing one example of a manufacturing process of the present invention (Embodiment);

5A and 5B are a top view and a cross-sectional view illustrating an example of a manufacturing process of the present invention (Example 1).

FIG. 6 is a cross-sectional view illustrating an example of a manufacturing process of the present invention (Example 1).

FIG. 7 is a cross-sectional view illustrating an example of a manufacturing process of the present invention (Example 1).

FIG. 8 is a cross-sectional view illustrating an example of a manufacturing process of the present invention (Example 1).

FIG. 9 is a top view of a pixel matrix circuit and a CMOS circuit.

FIG. 10 is an external view of an active matrix substrate.

FIG. 11 Electrical equipment

[Explanation of symbols]

REFERENCE SIGNS LIST 100 substrate 101 initial semiconductor film 102 a first gate insulating film 102 b first gate insulating film (after patterning) 102 c second gate insulating film 103 crystalline semiconductor film 104 active layer 105 conductive film 106 resist 107 a to c wiring layer 108 Porous anodic oxide 109 Barrier anodic oxide 110 First gate insulating film (after patterning) 111 Second gate insulating film (after patterning) 115, 116 High concentration impurity region 117, 118 Low concentration impurity region 119 Channel formation area

Claims (18)

[Claims] An active layer made of a crystalline semiconductor film on an insulating surface; a first insulating film in contact with an upper surface of the active layer; a second insulating film on the first insulating film; , The second
A semiconductor device comprising a semiconductor circuit comprising a semiconductor element, the semiconductor device comprising: 2. An active layer comprising a crystalline semiconductor film on an insulating surface, a first insulating film in contact with an upper surface of the active layer, and a first insulating film on the first insulating film. A semiconductor device comprising a semiconductor circuit including a semiconductor element, comprising: a second insulating film having a relatively large thickness; and a gate wiring on the second insulating film. 3. An active layer made of a crystalline semiconductor film on an insulating surface, a first insulating film in contact with an upper surface of the active layer, and a second insulating film having the same pattern shape as the first insulating film. And a gate wiring on the second insulating film. A semiconductor device comprising a semiconductor circuit comprising a semiconductor element. 4. The crystalline semiconductor film according to claim 1, wherein the crystalline semiconductor film includes a step of adding a catalytic element for promoting crystallization to the initial semiconductor film; And crystallizing the initial semiconductor film by irradiating external light or ultraviolet light without melting the initial semiconductor film. Semiconductor device. 5. The method according to claim 4, wherein the catalyst element is N
A semiconductor device including a semiconductor circuit including a semiconductor element, which is at least one element selected from i, Fe, Co, Pt, Cu, Au, and Ge. 6. The semiconductor circuit according to claim 4, wherein the initial semiconductor film is an amorphous semiconductor film or a microcrystalline semiconductor film. Semiconductor device. 7. The semiconductor device according to claim 1, wherein an impurity concentration at an interface between the first insulating film and the active layer is an impurity concentration at an interface between the first insulating film and the second insulating film. A semiconductor device comprising a semiconductor circuit including a semiconductor element, wherein the semiconductor circuit is lower than the concentration. 8. The gate wiring according to claim 1, wherein the gate wiring is a single layer made of a material layer mainly composed of one element selected from aluminum, tantalum, molybdenum, titanium, chromium, and silicon. Alternatively, a semiconductor device including a semiconductor circuit including a semiconductor element, which has a stacked structure. 9. The semiconductor device according to claim 1, wherein the first insulating film has a thickness of 1 to 50 nm. 10. The method according to claim 1, wherein
A semiconductor device comprising a semiconductor circuit comprising a semiconductor element, wherein the thickness of the second insulating film is 100 to 200 nm. 11. The active layer according to claim 1, wherein the active layer has a source region, a drain region, and a channel forming region formed between the source region and the drain region. A semiconductor device comprising a semiconductor circuit comprising a semiconductor element. 12. The semiconductor device according to claim 11, wherein at least a part of the source region and the drain region is a silicide. 13. The device according to claim 11, wherein the source region and the drain region include:
A semiconductor device including a semiconductor circuit including a semiconductor element, to which an impurity imparting N-type conductivity is added. 14. The semiconductor device according to claim 11, wherein an impurity imparting an N-type conductivity and an impurity imparting a P-type conductivity are added to the source region and the drain region. A semiconductor device provided with a semiconductor circuit comprising a semiconductor element. 15. The channel formation region according to claim 11, wherein the channel formation region contains a catalyst element that promotes crystallization of silicon, and the concentration of the catalyst element is smaller than that of the channel formation region. A semiconductor device comprising a semiconductor circuit including a semiconductor element, wherein a drain region is higher. 16. A step of contacting at least a part of a base film having an insulating surface with a catalytic element for promoting crystallization, and a step of continuously forming an initial semiconductor film and a first insulating film on the base film. Irradiating infrared light or ultraviolet light through the first insulating film to crystallize the initial semiconductor film to obtain a crystalline semiconductor film; and forming the crystalline semiconductor film and the first insulating film. Patterning a film to make an end face of the initial semiconductor film coincide with an end face of the first insulating film; and forming a second insulating film covering the active layer and the first insulating film; Forming a gate wiring on the insulating film; and forming the first insulating film and the second insulating film in the same pattern shape. Production method. 17. A step of contacting at least a part of a base film having an insulating surface with a catalytic element for promoting crystallization, and a step of continuously forming an initial semiconductor film and a first insulating film on the base film. Irradiating infrared light or ultraviolet light through the first insulating film to crystallize the initial semiconductor film to obtain a crystalline semiconductor film; and forming the crystalline semiconductor film and the first insulating film. Patterning a film to make an end face of the initial semiconductor film coincide with an end face of the first insulating film; and forming a second insulating film covering the active layer and the first insulating film; Forming a gate wiring on the insulating film; selectively removing the first insulating film and the second insulating film to expose a region to be a source region or a drain region; Will be the source or drain region And performing doping of phosphorus element to come region, subjected to heat treatment, a method for manufacturing a semiconductor device having a semiconductor circuit comprising a semiconductor element and a step for gettering the catalyst element. 18. The method according to claim 16, wherein
The step of obtaining a crystalline semiconductor film includes crystallizing the initial semiconductor film without melting the initial semiconductor film, the method for manufacturing a semiconductor device including a semiconductor circuit including a semiconductor element.