JP4437511B2 - Method for manufacturing electro-optical device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing an electro-optical device having an element or a circuit formed of a thin film transistor (hereinafter referred to as TFT) on a substrate having an insulating surface. The present invention also relates to an electronic device including an electro-optical device manufactured using the present invention.
[0002]
[Prior art]
Development of an electro-optical device having an integrated circuit formed of TFTs on a substrate is in progress. Liquid crystal display devices, EL display devices, or contact image sensors are known as representative examples. In particular, a TFT using a polysilicon film (polycrystalline silicon film) as an active layer (hereinafter referred to as poly-Si TFT) has a field effect transfer compared to a TFT using a conventional amorphous silicon film (hereinafter referred to as a-Si TFT). It is attracting attention because of its high degree.
[0003]
As electro-optical devices using poly-Si TFTs, liquid crystal display devices are currently attracting much attention and are already appearing on the market. However, although poly-Si TFTs have high performance, they are more expensive to manufacture than a-Si TFTs. Therefore, reducing the manufacturing cost of poly-Si TFTs has become an important issue in securing the market for liquid crystal display devices using poly-Si TFTs.
[0004]
[Problems to be solved by the invention]
It is an object of the present invention to provide a technique for reducing the manufacturing cost of an electro-optical device using a TFT by reducing the manufacturing cost of the TFT. An object of the present invention is to provide a technique for reducing the manufacturing cost of an electro-optical device, thereby reducing the manufacturing cost of an electronic device including the electro-optical device.
[0005]
[Means for Solving the Problems]
In the present invention, the manufacturing cost is reduced by minimizing the number of patterning steps (photolithography steps) used in the TFT manufacturing process. In order to reduce the patterning process, after forming the gate electrode, a technique for thinning the gate electrode without performing a new patterning process is used.
[0006]
DETAILED DESCRIPTION OF THE INVENTION
The embodiment of the present invention will be described in detail with reference to the following examples.
[0007]
[Example 1]
An embodiment of the present invention will be described with reference to FIGS. Here, a method for simultaneously manufacturing a pixel portion and a driver circuit provided around the pixel portion will be described. However, in order to simplify the description, regarding the drive circuit, a CMOS circuit which is a basic circuit such as a shift register circuit and a buffer circuit, and an n-channel TFT forming a sampling circuit are illustrated.
[0008]
In FIG. 1A, a glass substrate or a quartz substrate is preferably used for the substrate 101. In addition, a substrate in which an insulating film is formed on the surface of a silicon substrate, a metal substrate, or a stainless steel substrate may be used. If heat resistance permits, a plastic substrate can be used.
[0009]
A base film made of an insulating film containing silicon (referred to as a generic name of a silicon oxide film, a silicon nitride film, or a silicon nitride oxide film in this specification) is formed on the surface of the substrate 101 where the TFT is formed. 102 is formed to a thickness of 100 to 400 nm by plasma CVD or sputtering.
[0010]
Note that in this specification, a silicon nitride oxide film is an insulating film expressed by SiOxNy and indicates an insulating film containing silicon, oxygen, and nitrogen at a predetermined ratio. In this embodiment, as the base film 102, a 100-nm-thick silicon nitride oxide film containing nitrogen at 20 to 50 atomic% (typically 20 to 30 atomic%) and nitrogen at 1 to 20 atomic% (typically 5 to 5) are used. A laminated film with a silicon nitride oxide film having a thickness of 200 nm including 10 atomic%) is used. The thickness need not be limited to this value. The content ratio (atomic% ratio) of nitrogen and oxygen contained in the silicon nitride oxide film may be 3: 1 to 1: 3 (typically 1: 1). The silicon nitride oxide film is made of SiH. _Four And N ₂ O and NH _Three May be produced as a source gas.
[0011]
The base film 101 is provided to prevent impurity contamination from the substrate, and is not necessarily provided when a quartz substrate is used.
[0012]
Next, an amorphous silicon film (not shown) having a thickness of 30 to 120 nm (preferably 50 to 70 nm) is formed on the base film 102 by a known film formation method. Note that the semiconductor film is not limited to an amorphous silicon film, and may be a semiconductor film including an amorphous structure. The semiconductor film including an amorphous structure includes an amorphous semiconductor film and a microcrystalline semiconductor film, and further includes a compound semiconductor film including an amorphous structure such as a silicon germanium film having an amorphous structure. Moreover, if it forms with the said film thickness, the film thickness of the active layer when TFT is finally completed will be 10-100 nm (preferably 30-50 nm).
[0013]
Then, a polysilicon film 103 is formed according to the technique described in Japanese Patent Laid-Open No. 7-130552 (corresponding to USP 5,643,826). The technology described in this publication is a catalyst element (one or more kinds of elements selected from nickel, cobalt, germanium, tin, lead, palladium, iron, and copper, representative of the catalyst element that promotes crystallization when the amorphous silicon film is crystallized. Specifically, it is a crystallization means using nickel).
[0014]
Specifically, heat treatment is performed with the catalytic element held on the surface of the amorphous silicon film to change the amorphous silicon film into a polysilicon film. In this embodiment, the technique described in the first embodiment of the publication is used, but the technique described in the second embodiment may be used. In this embodiment, a polysilicon film is used as an example. However, the present invention is not limited to the polysilicon film, and any semiconductor film including a crystalline structure (including a single crystal silicon film) may be used. (Fig. 1 (A))
[0015]
Although depending on the amount of hydrogen contained in the amorphous silicon film, it is preferable that the dehydrogenation treatment is performed by heating at 400 to 550 ° C. for several hours, and the crystallization step is performed with the content of hydrogen being 5 atom% or less. Further, the amorphous silicon film may be formed by other manufacturing methods such as a sputtering method or a vapor deposition method, but it is desirable to sufficiently reduce impurity elements such as oxygen and nitrogen contained in the film.
[0016]
Here, since the base film and the amorphous silicon film can be formed by the same film formation method, they may be formed continuously. After the formation of the base film, it is possible to prevent the surface from being contaminated by once not being exposed to the air atmosphere, and the characteristic variation of the manufactured TFT can be reduced.
[0017]
Next, the polysilicon film 103 is irradiated with light (laser light) emitted from a laser light source (hereinafter referred to as laser annealing) to form a polysilicon film 104 with improved crystallinity. As the laser beam, a pulse oscillation type or continuous oscillation type excimer laser beam is desirable, but a continuous oscillation type argon laser beam may be used. Further, the beam shape of the laser light may be linear or rectangular. (Fig. 1 (B))
[0018]
Further, instead of laser light, light emitted from a lamp (hereinafter referred to as lamp light) may be irradiated (hereinafter referred to as lamp annealing). As the lamp light, lamp light emitted from a halogen lamp, an infrared lamp, or the like can be used.
[0019]
In addition, the process of performing heat treatment (annealing) with laser light or lamp light in this way is called a light annealing process. Since the light annealing process can be performed at a high temperature in a short time, an effective heat treatment process can be performed with high throughput even when a substrate having low heat resistance such as a glass substrate is used. Of course, since the purpose is annealing, furnace annealing (also referred to as thermal annealing) using an electric furnace can be used instead.
[0020]
In this embodiment, the laser annealing process is performed by processing pulsed excimer laser light into a linear shape. The laser annealing conditions are as follows: XeCl gas is used as the excitation gas, the processing temperature is room temperature, the pulse oscillation frequency is 30 Hz, and the laser energy density is 250 to 500 mJ / cm. ² (Typically 350-400mJ / cm ² ).
[0021]
The laser annealing step performed under the above conditions has the effect of completely crystallizing the amorphous region remaining after thermal crystallization and reducing defects in the already crystallized crystalline region. Therefore, this step can also be called a step of improving the crystallinity of the semiconductor film by light annealing or a step of promoting the crystallization of the semiconductor film. Such an effect can also be obtained by optimizing the lamp annealing conditions. In the present specification, such a condition is referred to as a first annealing condition.
[0022]
Next, the polysilicon film 104 is patterned to form island-like semiconductor films (hereinafter referred to as active layers) 105 to 108. Here, the first patterning step is performed. At the same time, an alignment marker used for alignment in future patterning is formed using a polysilicon film. In the case of the present embodiment, since the alignment marker can be formed simultaneously with the formation of the active layer, the trouble of separately forming the alignment marker (an increase in the patterning process) can be prevented.
[0023]
Next, a protective film 109 is formed on the active layers 105 to 108 for later impurity addition. As the protective film 109, a silicon nitride oxide film or a silicon oxide film with a thickness of 100 to 200 nm (preferably 130 to 170 nm) is used. This protective film 109 has a meaning for preventing the polysilicon film from being directly exposed to plasma when impurities are added and for enabling fine concentration control. (Figure 1 (C))
[0024]
Then, an impurity element imparting p-type conductivity (hereinafter referred to as a p-type impurity element) is added through the protective film 109. As the p-type impurity element, typically, an element belonging to Group 13, typically boron or gallium can be used. This step (referred to as channel doping step) is a step for controlling the threshold voltage of the TFT. Here, diborane (B ₂ H ₆ Boron is added by ion doping that is plasma-excited without mass separation. Of course, an ion implantation method for performing mass separation may be used.
[0025]
Thus 1 × 10 ¹⁵ ~ 1x10 ¹⁸ atoms / cm ^Three (Typically 5 × 10 ¹⁶ ~ 5x10 ¹⁷ atoms / cm ^Three ) Active layers 110 to 113 to which a p-type impurity element (boron in this embodiment) is added are formed. However, all the concentrations described in the present specification are measured values by SIMS (mass secondary ion analysis). Note that in this specification, an impurity region containing a p-type impurity element in the above concentration range (however, 1 × 10 10 ¹⁶ atoms / cm ^Three An impurity element that imparts n-type at a concentration of typically, except for a region added with phosphorus or arsenic) is defined as a p-type impurity region (b). (Figure 1 (D))
[0026]
In this step, boron is also added to the active layer 110 of the later p-channel TFT. However, if not necessary, only the active layer 110 may be hidden with a resist mask and the above step may be performed. Then, an element belonging to group 15 (typically phosphorus or arsenic) may be added only to the active layer 110 to further adjust the threshold voltage. However, in any case, the number of patterning increases.
[0027]
Next, resist masks 114a to 114d are formed. Here, the second patterning step is performed. Then, an impurity element imparting n-type (hereinafter referred to as n-type impurity element) is added to form impurity regions 115 to 118 exhibiting n-type. Note that as the n-type impurity element, an element belonging to Group 15 typically, phosphorus or arsenic can be used. (Figure 1 (E))
[0028]
The low-concentration impurity regions 115 to 118 are impurity regions that later become LDD regions or regions that become lower electrodes of storage capacitors in n-channel TFTs of a CMOS circuit or a sampling circuit. Note that the impurity region formed here contains 2 × 10 n-type impurity elements. ¹⁶ ~ 5x10 ¹⁹ atoms / cm ^Three (Typically 5 × 10 ¹⁷ ~ 5x10 ¹⁸ atoms / cm ^Three ) Concentration. In this specification, an impurity region containing an n-type impurity element in the above concentration range is defined as an n-type impurity region (b).
[0029]
Here, phosphine (PH _Three ) By mass-separated plasma-excited ion doping method with 1 × 10 phosphorus ¹⁸ atoms / cm ^Three Add at a concentration of Of course, an ion implantation method for performing mass separation may be used. In this step, phosphorus is added to the polysilicon film through the protective film 109.
[0030]
Next, the resist masks 114a to 114d and the protective film 109 are removed, and a laser light irradiation process is performed again. Again, the laser beam is preferably a pulse oscillation type or continuous oscillation type excimer laser beam, but may be a continuous oscillation type argon laser beam. Further, the beam shape of the laser light may be linear or rectangular. However, since the purpose is to activate the added impurity element, it is preferable to irradiate with energy that does not melt the polysilicon film. It is also possible to perform the laser annealing process with the protective film 109 attached. (Fig. 1 (F))
[0031]
In this embodiment, the laser annealing process is performed by processing pulsed excimer laser light into a linear shape. The laser annealing conditions are as follows: KrF gas is used as the excitation gas, the processing temperature is room temperature, the pulse oscillation frequency is 30 Hz, and the laser energy density is 100 to 300 mJ / cm. ² (Typically 150-250mJ / cm ² ).
[0032]
The optical annealing step performed under the above conditions has an effect of activating the added n-type or p-type impurity element and recrystallizing the amorphous semiconductor film when the impurity element is added. . Note that it is preferable that the above conditions ensure atomic arrangement consistency without melting the semiconductor film and activate the impurity element. This step can also be called a step of activating an impurity element imparting n-type or p-type by light annealing, a step of recrystallizing a semiconductor film, or a step of simultaneously performing them. Such an effect can also be obtained by optimizing the lamp annealing conditions. In the present specification, such a condition is referred to as a second annealing condition.
[0033]
By this step, an intrinsic region existing at the boundary between the n-type impurity regions (b) 115 to 118, that is, around the n-type impurity region (b) (the p-type impurity region (b) is also regarded as substantially intrinsic). And the joint part becomes clear. This means that when the TFT is later completed, the LDD region and the channel formation region can form a very good junction.
[0034]
In addition, when activating the impurity element by the laser beam, activation by heat treatment using an electric furnace may be used in combination. When activation by heat treatment is performed, heat treatment at 450 to 650 ° C. (preferably 500 to 550 ° C.) may be performed in consideration of heat resistance of the substrate.
[0035]
Next, a gate insulating film 119 is formed so as to cover the active layers 110 to 113. The gate insulating film 119 may be formed to a thickness of 10 to 200 nm, preferably 50 to 150 nm. In this embodiment, plasma CVD is used for N. ₂ O and SiH _Four A silicon nitride oxide film is formed to a thickness of 80 nm using as a raw material. (Fig. 2 (A))
[0036]
Next, a conductive film 120 to be a gate wiring (including a gate electrode) is formed. Note that although the gate wiring may be formed using a single-layer conductive film, it is preferable to form a stacked film such as two layers or three layers as necessary.
[0037]
Here, the conductive film 120 is a metal containing an element selected from tantalum (Ta), titanium (Ti), molybdenum (Mo), tungsten (W), chromium (Cr), niobium (Nb), and silicon (Si). Film, or a metal compound film containing the above element as a main component (typically a tantalum nitride film, a tungsten nitride film, a titanium nitride film), or an alloy film (typically, a Mo—W alloy film, A Mo—Ta alloy film, a tungsten silicide film), or a stacked film in which these thin films are stacked can be used.
[0038]
In this embodiment, as the conductive film 120, a stacked film including a tantalum nitride (TaN) film having a thickness of 50 nm and a tantalum (Ta) film having a thickness of 350 nm is used.
[0039]
In addition, a laminated film of a tungsten nitride film and a tungsten film, a single-layer film including only a tantalum nitride film, and a tungsten silicide film are also suitable. Further, when a structure (polycide structure) in which a silicon film is formed with a thickness of about 2 to 20 nm in the lowermost layer of the gate wiring, the adhesion of the conductive film formed on the silicon film is improved and at the same time, Oxidation can be suppressed.
[0040]
Further, when a metal film is used as the conductive film 120 as in this embodiment, it is also effective to nitride the surface by exposing it to a plasma atmosphere using ammonia gas or nitrogen gas. By doing so, it is possible to suppress oxidation of the metal film surface.
[0041]
Next, resist masks 121a to 121f are formed, and the conductive film 120 is etched to form gate wirings 122 to 124, 125a, and 125b having a thickness of 400 nm and a capacitor wiring 126 serving as an upper electrode of a storage capacitor. Here, a third patterning step is performed. At this time, the gate wirings 123 and 124 formed in the driver circuit are formed so as to overlap a part of the n-type impurity regions (b) 115 to 117 with a gate insulating film interposed therebetween. Although the gate wirings 125a and 125b appear to be two in the cross section, they are actually formed from a single continuous pattern. (Fig. 2 (B))
[0042]
Next, an n-type impurity element (phosphorus in this embodiment) is added in a self-aligning manner using the gate wirings 122 to 124, 125a, 125b and the capacitor wiring 126 as a mask. Thus, impurity regions 127 to 136 containing phosphorus at a high concentration are formed. Here, phosphine (PH _Three ) Using an ion doping method (of course, an ion implantation method may be used), and the phosphorus concentration in this region is 1 × 10 ²⁰ ~ 1x10 ^{twenty one} atoms / cm ^Three (Typically 2 × 10 ²⁰ ~ 5x10 ^{twenty one} atoms / cm ^Three ). In this specification, an impurity region containing an n-type impurity element in the above concentration range is defined as an n-type impurity region (a). (Fig. 2 (C))
[0043]
The region where the impurity regions 129, 131 and 132 are formed already contains phosphorus added in the previous step. However, since phosphorus is added at a sufficiently high concentration, it was added in the previous step. You don't have to think about the effects of phosphorus.
[0044]
Next, an isotropic dry etching process is performed using the resist masks 121a to 121f as masks. CF as etching gas _Four And O ₂ And a mixed gas may be used. Of course, other gas may be used. By this process, gate wirings 137 to 139, 140a, 140b and capacitor wiring 141 which are thinned by etching from the lateral direction are formed. (Fig. 2 (D))
[0045]
Next, the resist masks 121a to 121f are removed, and an n-type impurity element addition step is performed again. Impurity regions 142 to 148 thus formed have a concentration of 1/2 to 1/10 (typically 1/3 to 1/4) of the n-type impurity region (b) (however, in the channel doping step described above). Concentration 5-10 times higher than the added boron concentration, typically 1 × 10 ¹⁶ ~ 5x10 ¹⁸ atoms / cm ^Three , Typically 3x10 ¹⁷ ~ 3x10 ¹⁸ atoms / cm ^Three )) So that phosphorus is added. In this specification, an impurity region containing an n-type impurity element in the above concentration range is defined as an n-type impurity region (c). (Fig. 3 (A))
[0046]
Note that the n-type impurity regions (c) 142 to 148 have already been 1 × 10 4 in the channel doping process. ¹⁵ ~ 1x10 ¹⁸ atoms / cm ^Three In this step, since phosphorus is added at a concentration 5 to 10 times that of boron contained in the p-type impurity region (b), the influence of boron may be ignored.
[0047]
However, strictly speaking, the phosphorus concentration of the portion of the n-type impurity region (b) 115 to 117 that overlaps the gate wiring is 2 × 10. ¹⁶ ~ 5x10 ¹⁹ atoms / cm ^Three Whereas the portion that does not overlap the gate wiring is 1 × 10 ¹⁶ ~ 5x10 ¹⁸ atoms / cm ^Three The concentration of phosphorus is added, and phosphorus is contained at a slightly higher concentration.
[0048]
The n-type impurity regions (c) 145 to 148 formed here serve as LDD regions of TFTs (hereinafter referred to as pixel TFTs) to be disposed in the pixel portion later. The lengths (widths) of the n-type impurity regions (c) 145 to 148 are determined by the etching amount of the gate wiring in FIG. Therefore, it is necessary to set the line width of the first gate wirings 122 to 124, 125a, and 125b and the etching amount from the lateral direction of the gate wiring based on this.
[0049]
Next, a resist mask 149 is formed. Here, a fourth patterning step is performed. Then, a p-type impurity element (boron in this embodiment) is added to form impurity regions 150 and 151 containing boron at a high concentration. Here, diborane (B ₂ H ₆ 3 × 10 by an ion doping method (which may of course be an ion implantation method). ²⁰ ~ 3x10 ^{twenty one} atoms / cm ^Three (Typically 5 × 10 ²⁰ ~ 1x10 ^{twenty one} atoms / cm ^Three ) Add boron at a concentration. In this specification, an impurity region containing a p-type impurity element in the above concentration range is defined as a p-type impurity region (a). (Fig. 3 (B))
[0050]
Note that a part of the impurity regions 150 and 151 (the above-described n-type impurity regions (a) 127 and 128) is already 1 × 10 6. ²⁰ ~ 1x10 ^{twenty one} atoms / cm ^Three However, the boron added here is added at a concentration at least three times that of phosphorus. Therefore, the n-type impurity region formed in advance is completely inverted to the P-type and functions as a P-type impurity region.
[0051]
Next, after removing the resist mask 149, a first interlayer insulating film 152 is formed. The first interlayer insulating film 152 may be formed using an insulating film containing silicon, specifically, a silicon nitride film, a silicon oxide film, a silicon nitride oxide film, or a stacked film including a combination thereof. The film thickness may be 50 to 400 nm (preferably 100 to 200 nm).
[0052]
In this example, SiH is used by plasma CVD. _Four , N ₂ O, NH _Three As a source gas, a 200 nm thick silicon nitride oxide film (however, the nitrogen concentration is 25 to 50 atomic%) is used. The first interlayer insulating film 152 has an effect of preventing an increase in resistance value due to oxidation of the gate wirings 137 to 139, 140 a and 140 b and the capacitor wiring 141 in a heat treatment process (activation process) to be performed next.
[0053]
Thereafter, a heat treatment step (activation step) is performed in order to activate the n-type or p-type impurity element added at each concentration. This step can be performed by a furnace annealing method, a laser annealing method, or a rapid thermal annealing method (RTA method). Here, the activation process is performed by furnace annealing. This heat treatment step is performed in a nitrogen atmosphere at 300 to 650 ° C., preferably 400 to 550 ° C., here 550 ° C. for 4 hours. (Figure 3 (C))
[0054]
At this time, the catalytic element (nickel in this example) used for crystallization of the amorphous silicon film in this example moves in the direction indicated by the arrow, and is formed in the above-described step of FIG. Captured (gettered) in a region containing phosphorus in the concentration. This is a phenomenon caused by the gettering effect of the metal element by phosphorus. As a result, the concentration of the catalyst element in the subsequent channel formation regions 153 to 157 is 1 × 10 5. ¹⁷ atoms / cm ^Three It becomes as follows. However, in the case of nickel, 1 × 10 ¹⁷ atoms / cm ^Three The following are the lower limits of SIMS measurement, and cannot be measured with the current technology.
[0055]
On the contrary, in the region that becomes the gettering site of the catalytic element (the region in which the impurity regions 127 to 136 are formed in the process of FIG. 2C), the catalytic element is segregated at a high concentration to 5 × 10. ¹⁸ atoms / cm ^Three Above (typically 1 × 10 ¹⁹ ~ 5x10 ²⁰ atoms / cm ^Three ) Become present in concentration. However, since the region serving as the gettering site only needs to function as a source region or a drain region, the presence or absence of nickel is not considered to be a problem.
[0056]
Next, a process of hydrogenating the active layer is performed by performing a heat treatment at 300 to 450 ° C. for 1 to 12 hours in an atmosphere containing 3 to 100% hydrogen. This step is a step of terminating dangling bonds in the semiconductor layer with thermally excited hydrogen. As another means of hydrogenation, plasma hydrogenation (using hydrogen excited by plasma) may be performed.
[0057]
When the activation process is completed, a second interlayer insulating film 158 having a thickness of 500 nm to 1.5 μm is formed on the first interlayer insulating film 152. In this embodiment, a silicon oxide film having a thickness of 800 nm is formed as the second interlayer insulating film 158 by a plasma CVD method. Thus, an interlayer insulating film having a thickness of 1 μm formed of a laminated film of the first interlayer insulating film (silicon nitride oxide film) 152 and the second interlayer insulating film (silicon oxide film) 158 is formed. (Fig. 3 (D))
[0058]
As the second interlayer insulating film 158, an organic resin insulating film such as polyimide, acrylic, polyamide, polyimide amide, or BCB (benzocyclobutene) can be used.
[0059]
Thereafter, contact holes reaching the source region or drain region of each TFT are formed. Here, the fifth patterning step is performed. Then, source wirings 159 to 162 and drain wirings 163 to 166 are formed. Here, the sixth patterning step is performed.
[0060]
Although not shown, the drain wirings 163 and 164 are electrically connected to form a CMOS circuit. In this embodiment, the electrode is a laminated film having a three-layer structure in which a Ti film is formed with a thickness of 100 nm, an aluminum film containing Ti with a thickness of 300 nm, and a Ti film with a thickness of 150 nm.
[0061]
Next, the passivation film 167 is formed using a silicon nitride film, a silicon oxide film, or a silicon nitride oxide film with a thickness of 50 to 500 nm (typically 200 to 300 nm).
[0062]
At this time, prior to film formation, H ₂ , NH _Three It is effective to perform plasma treatment using a gas containing isohydrogen and to perform heat treatment after film formation. Hydrogen excited by this pretreatment is supplied into the first and second interlayer insulating films. By performing heat treatment in this state, the film quality of the passivation film 167 is improved and hydrogen added to the first and second interlayer insulating films diffuses to the lower layer side, so that the active layer is effectively hydrogenated. can do.
[0063]
Further, a hydrogenation step may be further performed after the passivation film 167 is formed. For example, heat treatment may be performed at 300 to 450 ° C. for 1 to 12 hours in an atmosphere containing 3 to 100% hydrogen, or the same effect can be obtained by using a plasma hydrogenation method.
[0064]
Note that an opening may be formed in the passivation film 167 at a position where a contact hole for connecting the pixel electrode and the drain wiring is formed later. However, in that case, the number of times of patterning increases.
[0065]
Thereafter, a third interlayer insulating film 168 made of an insulating film made of a resin material (or an organic material) (hereinafter referred to as a resin insulating film) is formed to a thickness of about 1 μm. As the resin material, polyimide, acrylic, polyamide, polyimide amide, BCB (benzocyclobutene), or the like can be used. Advantages of using a resin insulating film are that the film forming method is simple, the relative dielectric constant is low, the parasitic capacitance can be reduced, and the flatness is excellent. A resin insulating film or an organic SiO compound other than those described above can also be used.
[0066]
Here, an acrylic film that is polymerized by heat after being applied to the substrate is used, but a type that is polymerized by light irradiation may be used. Moreover, a negative type resin insulation film is mentioned as a photopolymerization type. In such a type, a portion irradiated with light is polymerized to form a cross-linked structure, so that the resistance to the solution is increased.
[0067]
Further, as a part of the third interlayer insulating film 168, a resin insulating film colored with a pigment or the like may be provided and used as a color filter.
[0068]
Next, a contact hole reaching the drain wiring 166 is formed in the third interlayer insulating film 168 and the passivation film 167. Here, the seventh patterning step is performed. Then, pixel electrodes 169 and 170 are formed. Here, the eighth patterning step is performed.
[0069]
Note that the pixel electrode 170 is a pixel electrode of another adjacent pixel. In this embodiment, transparent conductive films are used as the pixel electrodes 169 and 170. Specifically, an indium tin oxide (ITO) film is formed to a thickness of 110 nm by sputtering.
[0070]
In the case of a reflective liquid crystal display device, a metal film may be used as a material for the pixel electrode. In particular, a metal film having a high reflectance is preferable, and an aluminum alloy is preferably used.
[0071]
Thus, a substrate (hereinafter referred to as an active matrix substrate) having a driving circuit and a pixel portion on the same substrate is completed. The number of times of patterning required to complete the process so far is eight, and it can be said that this is a very small number of times as a method for manufacturing an active matrix substrate using poly-Si TFTs.
[0072]
Further, as shown in FIG. 4, when the active matrix substrate is completed, a spacer 171 made of resin is formed on the pixel electrode 170 by patterning. Further thereon, an alignment film 172 is formed by screen printing.
[0073]
Further, a light-shielding film 174a, 174b, a color filter 175a, 175b, a planarization film (overcoat agent) 176, a counter electrode 177 made of a transparent conductive film, and an alignment film 178 are formed on the light-transmitting substrate 173 to form the counter substrate. Make it.
[0074]
Then, the active matrix substrate and the counter substrate are bonded with a sealant 179, and the liquid crystal 180 is sealed with the sealant 179. Thus, a liquid crystal display device having a structure as shown in FIG. 4 is completed.
[0075]
In FIG. 4, a p-channel TFT 301 and n-channel TFTs 302 and 303 are formed in the driver circuit, and a pixel TFT 304 and a storage capacitor 305 that are n-channel TFTs are formed in the pixel portion.
[0076]
In the p-channel TFT 301 of the driving circuit, a channel formation region 201, a source region 202, and a drain region 203 are each formed with a p-type impurity region (a). However, in actuality, a portion of the source region or the drain region (the portion where the n-type impurity regions 127 and 128 in FIG. 2C are formed) is 1 × 10 ²⁰ ~ 1x10 ^{twenty one} atoms / cm ^Three There is a region containing phosphorus at a concentration of. Further, 5 × 10 5 of the catalytic element gettered in the process of FIG. ¹⁸ atoms / cm ^Three Above (typically 1 × 10 ¹⁹ ~ 5x10 ²⁰ atoms / cm ^Three ) Present in concentration.
[0077]
The n-channel TFT 302 includes a channel formation region 204, a source region 205, a drain region 206, and an LDD region 207 that overlaps with a gate wiring through a gate insulating film on one side (drain region side) of the channel formation region. It is formed. At this time, the LDD region 207 has a size of 2 × 10. ¹⁶ ~ 5x10 ¹⁹ atoms / cm ^Three It is formed so as to contain phosphorus at a concentration of and to partially overlap the gate wiring. An LDD region 208 made of an n-type impurity region (c) is formed on the source region side.
[0078]
In the n-channel TFT 303, a channel formation region 209, a source region 210, a drain region 211, and LDD regions 212 and 213 are formed on both sides of the channel formation region. In this structure, part of the LDD regions 212 and 213 are arranged so as to overlap with the gate wiring, so that the LDD region overlapping with the gate wiring through the gate insulating film does not overlap with the gate wiring through the gate insulating film. An LDD region is formed. This structure is the same structure as the LDD region 207 of the n-channel TFT 302.
[0079]
Here, the cross-sectional view shown in FIG. 5 is an enlarged view showing a state in which the n-channel TFT 303 shown in FIG. 4 is manufactured up to the step of FIG. As shown here, the LDD region 212 can be further classified into a region 212a that overlaps with the gate wiring and a region 212b that does not overlap with the gate wiring, and the LDD region 213 can be further distinguished into a region 213a that overlaps with the gate wiring and a region 213b that does not overlap with the gate wiring. In addition, the above-described regions 212a and 213a have 2 × 10. ¹⁶ ~ 5x10 ¹⁹ atoms / cm ^Three The regions 212b and 213b contain phosphorus at a concentration of 1 to 2 times (typically 1.2 to 1.5 times).
[0080]
In the pixel TFT 304, n-type impurity regions (a) 222 in contact with the channel formation regions 214 and 215, the source region 216, the drain region 217, the LDD regions 218 to 221 and the LDD regions 219 and 220 are formed. At this time, the source region 216 and the drain region 217 are each formed of an n-type impurity region (a), and the LDD regions 218 to 221 are formed of an n-type impurity region (c).
[0081]
Further, the drain region 217 is extended and connected to the n-type impurity region 223. The capacitor wiring 141 overlaps with the gate insulating film 119 interposed therebetween. At this time, a storage capacitor 305 including the n-type impurity region 223, the gate insulating film 119, and the capacitor wiring 141 is formed.
[0082]
According to the manufacturing process of this embodiment, the structure of a TFT for forming a circuit or an element can be optimized according to the performance required by the pixel portion and the driver circuit, and the operation performance and reliability of the semiconductor device can be improved. Specifically, n-channel TFTs have a low LDD region arrangement according to circuit specifications and use different Lov regions or Loff regions. A TFT structure with an emphasis on off-current operation can be realized.
[0083]
For example, in the case of an active matrix liquid crystal display device, the n-channel TFT 302 is suitable for a drive circuit such as a shift register or a signal dividing circuit that places importance on high-speed operation. That is, by disposing the LDD region overlapping with the gate wiring only on one side (drain region side) of the channel formation region, it is possible to achieve an operation that is resistant to deterioration due to hot carrier injection while suppressing formation of parasitic capacitance as much as possible.
[0084]
The n-channel TFT 303 is suitable for a sampling circuit (sample and hold circuit) that places importance on both hot carrier countermeasures and low off-current operation. That is, hot carrier injection is reduced in the LDD region overlapping with the gate wiring, and the low off-state current is reduced in the LDD region not overlapping with the gate wiring. In addition, the sampling circuit has a structure in which the functions of the source region and the drain region are reversed and the carrier moving direction is changed by 180 °, so that the sampling circuit is line-symmetric with respect to the gate wiring.
[0085]
Further, the n-channel TFT 304 is suitable for a pixel portion and a sampling circuit (sample hold circuit) that place importance on low off-current operation. That is, the low off-current operation can be achieved by disposing the LDD region so as not to overlap with the gate wiring without disposing the LDD region overlapping with the gate wiring which may increase the off-current value. Further, by using an LDD region having a lower concentration than the LDD region of the driver circuit, the off-current value can be further reduced.
[0086]
Further, in this embodiment, a double gate structure is used. However, disposing a high-concentration impurity region (in this case, n-type impurity region (a) 222) between two gate wirings (gate electrodes) is an off-current value. It is very effective in reducing. Note that other multi-gate structures such as a triple gate structure may be used.
[0087]
Of the LDD region 207 of the n-channel TFT 302 and the LDD regions 212 and 213 of the n-channel TFT 303, the length (width) of the region overlapping with the gate wiring is 0.1 to 3.0 μm (typically 0. 2 to 1.5 μm), and the length (width) of the region that does not overlap with the gate wiring may be 1.0 to 3.5 μm (typically 1.5 to 2.0 μm). The length (width) of the LDD regions 218 to 221 provided in the pixel TFT 304 may be set to 0.5 to 3.5 μm (typically 2.0 to 2.5 μm).
[0088]
[Example 2]
In this example, the appearance of the liquid crystal display device manufactured in Example 1 will be described. The perspective view of FIG. 6 is used for the description. The active matrix substrate includes a pixel portion 602, a gate signal side driver circuit 603, and a source signal side driver circuit 604 formed on the substrate 601. A pixel electrode 606 and a storage capacitor 607 are connected to the pixel TFT 605 in the pixel portion. The storage capacitor 305 shown in Embodiment 1 is used for this storage capacitor 607.
[0089]
Further, the drive circuit provided in the periphery is configured based on a CMOS circuit. The gate signal side driver circuit 603 and the source signal side driver circuit 604 are connected to the pixel portion 602 through a gate wiring 608 and a source wiring 609, respectively. The FPC 610 is provided with input / output wirings (connection wirings) 611 and 612 for transmitting signals to the driving circuit. Reference numeral 613 denotes a counter substrate.
[0090]
In this specification, the electro-optical device shown in FIG. 6 is called a liquid crystal display device, but the state in which the FPC is attached as shown in FIG. 6 is generally called a liquid crystal module. Therefore, the liquid crystal display device in this embodiment may be called a liquid crystal module.
[0091]
[Example 3]
In this example, a case where a liquid crystal display device is manufactured through a manufacturing process different from that of Example 1 is described. FIG. 7 is used for the description.
[0092]
First, the steps up to the step of FIG. However, in this embodiment, a material that can be anodized is used for the gate wiring. A particularly preferable material is a material mainly composed of aluminum. In this embodiment, an aluminum film containing 0.2 wt% scandium is used.
[0093]
This state is shown in FIG. When the state of FIG. 7A is obtained, porous anodic oxides 701 to 706 are formed by anodizing using a 3% oxalic acid aqueous solution as an electrolytic solution. These anodic oxides are formed laterally with respect to the gate wiring as shown in FIG. The thickness of these anodic oxides 701 to 706 is controlled by time, and in this embodiment, the thickness is 1 μm.
[0094]
Next, the resist masks 121a to 121f are removed, and an anodic oxidation treatment is performed using an electrolytic solution in which a 15% ammonium tartrate aqueous solution and ethylene glycol are mixed at a ratio of 2: 8 to obtain a dense (nonporous) anodic oxide 707. 713 are formed. The thickness of the anodic oxides 707 to 713 is controlled by the applied voltage at the time of anodic oxidation, and in this embodiment, the thickness is 150 nm. The anodic oxides 707 to 713 are provided for the purpose of protecting the gate wiring in a later doping process or activation process. (Fig. 7 (C))
[0095]
Next, the porous anodic oxides 701 to 706 are removed. As an etching solution for removal, a solution obtained by mixing phosphoric acid, nitric acid, acetic acid, and water in this order at 85: 5: 5: 5 (volume ratio) may be used.
[0096]
Then, an n-type impurity element is added using the final gate wirings 707 to 709, 710a, 710b and the capacitor wiring 711 as a mask. The addition conditions at this time are the same as those in the process of FIG. Thereby, n-type impurity regions (c) 142 to 148 are formed. In this way, the state of FIG.
[0097]
In the case of this embodiment, a length corresponding to the thickness of the above-described anodic oxides 707 to 713 is formed between the channel formation regions 714 to 718 and the n-type impurity regions (c) 142 to 148 in contact therewith. An offset region (not shown) is formed.
[0098]
The subsequent steps may follow the steps after FIG. 3B of the first embodiment. Note that the activation step in FIG. 3C is preferably performed in a temperature range of 450 to 500 ° C. in consideration of heat resistance of the gate wiring.
[0099]
In the case of this embodiment, all the gate wirings must be electrically connected until at least the process shown in FIG. That is, a portion for electrically connecting adjacent gate wirings must be divided.
[0100]
Therefore, in this embodiment, when forming the source wiring and the drain wiring shown in FIG. 3D, a part of the gate wiring is exposed in advance, and when the source wiring and the drain wiring are formed, a part of the gate wiring ( Etching is also performed to remove the cut portion. As a result, the individual gate lines are separated.
[0101]
In addition, the manufacturing process of a present Example changes a part of Example 1, and can apply Example 1 mutatis mutandis except the part. In addition, when the liquid crystal display device shown in Embodiment 2 is manufactured, this embodiment can be carried out.
[0102]
[Example 4]
In this example, a case where a liquid crystal display device is manufactured through a manufacturing process different from that of Example 1 is described. FIG. 8 is used for the description.
[0103]
First, the steps up to FIG. However, in this embodiment, as the gate wiring 120, a stacked film including the first conductive film 120a and the second conductive film 120b is used. At this time, there is a feature in that a combination of conductive films satisfying a condition that “the first conductive film 120a is not etched under the condition that the second conductive film 120b can be etched” is selected.
[0104]
In this embodiment, a molybdenum film with a thickness of 100 nm is used as the first conductive film 120a, and a tantalum film with a thickness of 300 nm is used as the second conductive film 120b. Note that although a tantalum film is used as a single layer here, a laminated film with a tantalum nitride film may be used. The tantalum film is easily etched with a fluorine-based etching gas, but the molybdenum film is hardly etched with a fluorine-based gas.
[0105]
As a combination in the case of using a fluorine-based gas as an etching gas, a titanium film, a molybdenum film, or an aluminum alloy film is selected as the first conductive film 120a, and a silicon film or a tantalum film (tantalum nitride film) is selected as the second conductive film 120b. The same may be used. In addition, as a combination in the case of using a chlorine-based gas, either a silicon film or a tantalum film (the same applies to a tantalum nitride film) is selected as the first conductive film 120a, and an aluminum alloy film or a titanium film is used as the second conductive film 120b. Use it.
[0106]
Although the case where dry etching is performed is described here, the same applies to the case where wet etching is used. A solution to be etched and a solution not to be etched for various metal films are well known, and their relationship may be investigated and applied.
[0107]
This state is shown in FIG. When the state of FIG. 8A is obtained, resist masks 121a to 121f are formed and etched to form gate wirings 122 to 124, 125a and 125b and a capacitor wiring 126.
[0108]
Then, an n-type impurity element is added in the same manner as in the step of FIG. 2C of Embodiment 1 to form n-type impurity regions (A) 127 to 136. (Fig. 8 (B))
[0109]
Next, using the resist masks 121a to 121f as a mask, fluorine-based gas (CF in this embodiment) _Four And O ₂ Isotropic etching using a mixed gas). As a result, only the portion made of the second conductive film 120b in the gate wiring is selectively etched, and the convex gate wiring and capacitance formed of the conductive film shown by 801a to 806a and the conductive film shown by 801b to 806b. A wiring is formed.
[0110]
Then, an n-type impurity element is added using the convex gate wiring and the capacitor wiring as a mask. The addition conditions at this time are the same as those in the process of FIG. However, here, the n-type impurity element is adjusted so as to penetrate through the conductive films indicated by reference numerals 801b to 806b and also to the active layer therebelow. Thereby, n-type impurity regions (c) 142 to 148 are formed. In this way, the state of FIG.
[0111]
In this embodiment, since the n-type impurity region (c) is also formed under the conductive films indicated by 801b to 806b, the gate wiring completely overlaps the LDD region.
[0112]
The subsequent steps may follow the steps after FIG. 3B of the first embodiment. In addition, the manufacturing process of a present Example changes a part of Example 1, and can apply Example 1 mutatis mutandis except the part. In addition, when the liquid crystal display device shown in Embodiment 2 is manufactured, this embodiment can be carried out.
[0113]
[Example 5]
In the manufacturing process of Example 1, an example in which a catalytic element that promotes crystallization is used as a method for forming a semiconductor film including a crystal structure. However, in this example, thermal crystallization is performed without using such a catalytic element. A case where a semiconductor film including a crystal structure is formed by crystallization or laser crystallization is shown.
[0114]
In the case of thermal crystallization, a heat treatment step for 15 to 24 hours may be performed at a temperature of 600 to 650 ° C. after forming a semiconductor film including an amorphous structure. That is, by performing heat treatment at a temperature exceeding 600 ° C., natural nuclei are generated and crystallization proceeds.
[0115]
In the case of laser crystallization, a laser annealing process may be performed under the first annealing conditions described in Embodiment 1 after forming a semiconductor film including an amorphous structure. Thus, a semiconductor film including a crystal structure can be formed in a short time. Of course, lamp annealing may be performed instead of laser annealing.
[0116]
Moreover, you may use the technique described in Example 1 of Japanese Patent Application No. 11-76967 application specification. According to the manufacturing process of Example 1 of the same application specification, a polysilicon film having a unique crystal structure can be obtained. For details of this polysilicon film, refer to the applications of Japanese Patent Application No. 10-044659, Japanese Patent Application No. 10-152316, Japanese Patent Application No. 10-152308 or Japanese Patent Application No. 10-152305 filed by the present applicant. It ’s fine.
[0117]
As described above, a semiconductor film including a crystal structure used for a TFT can be formed using any known means. In addition, a present Example can be freely combined with any structure of Examples 1-4.
[0118]
[Example 6]
Before any n-type impurity element or p-type impurity element is added in any or all of the steps of FIG. 2C, the step of FIG. 3A, or the step of FIG. Alternatively, the gate insulating film may be etched and removed using the gate wiring as a mask.
[0119]
When the gate insulating film is an insulating film containing silicon, CHF is used as an etching gas. _Three It is preferable to use a dry etching method using By doing so, the impurity element is directly added to the active layer, so that the acceleration voltage during doping can be suppressed and the throughput can be improved.
[0120]
In addition, the structure of a present Example can be implemented in combination freely with any structure of Examples 1-5.
[0121]
[Example 7]
The present invention can also be used when an interlayer insulating film is formed on a conventional MOSFET using a semiconductor substrate and a TFT is formed thereon. That is, it is possible to realize a three-dimensional semiconductor device.
[0122]
Further, only when a reflective liquid crystal display device is manufactured, an SOI substrate such as SIMOX, Smart-Cut (registered trademark of SOITEC), ELTRAN (registered trademark of Canon Inc.), or the like can be used as a substrate. Of course, if a technique for forming a single crystal semiconductor thin film on a transparent substrate using these SOI techniques is established, it can be used for a transmissive display device.
[0123]
In addition, the structure of a present Example can be freely combined with any structure of Examples 1-6.
[0124]
[Example 8]
The manufacturing process of the TFT shown in Embodiments 1 to 7 can be applied to the case of manufacturing an active matrix EL (electroluminescence) display device.
[0125]
In an ordinary EL display device, a switching TFT and a current control TFT are formed in a pixel. The n-channel TFT 304 shown in FIG. 4 is suitable as a switching TFT, and an n-channel TFT is used. The TFT 302 is suitable as a current control TFT.
[0126]
Therefore, an active matrix substrate for an EL display device may be manufactured with reference to the manufacturing steps of Examples 1 to 7, and the EL display device may be completed using a known EL formation technique.
[0127]
[Example 9]
An inexpensive electro-optical device obtained by implementing the present invention can be incorporated as a part in any electronic device (electronic product) incorporating a display such as a personal computer.
[0128]
Such electronic devices include video cameras, digital still cameras, projectors (rear type or front type), goggle type displays (head mounted display), car navigation, personal computers, personal digital assistants (mobile computers, mobile phones or electronic devices). A display capable of playing back a recording medium such as a book, etc., and a recording medium (specifically, a compact disc (CD), laser disc (LD), digital video disc (DVD), etc.) And the like). Examples of these semiconductor devices are shown in FIGS.
[0129]
FIG. 9A illustrates a personal computer, which includes a main body 2001, an image receiving portion 2002, a display device 2003, a keyboard 2004, and the like. The present invention can be used for the display device 2004.
[0130]
FIG. 9B illustrates a video camera, which includes a main body 2101, a display device 2102, an audio input portion 2103, operation switches 2104, a battery 2105, an image receiving portion 2106, and the like. The present invention can be used for the display device 2102.
[0131]
FIG. 9C illustrates a goggle type display which includes a main body 2201, a display device 2202, an arm portion 2203, and the like. The present invention can be used for the display device 2202.
[0132]
FIG. 9D shows an image reproducing device (specifically, a DVD reproducing device) provided with a recording medium, which includes a main body 2301, a recording medium (CD, LD, DVD, etc.) 2302, an operation switch 2303, and a display device (a). 2304, a display device (b) 2305, and the like. Although the display device (a) mainly displays image information and the display device (b) mainly displays character information, the present invention can be used for these display devices (a) and (b). Note that the present invention can be used for a CD playback device, a game machine, or the like as an image playback device provided with a recording medium.
[0133]
FIG. 9E illustrates a front type projector, which includes a main body 2401, a light source, an optical system lens including a display system, an optical engine 2402, and the like, and can display an image on a screen 2403. The present invention can be used for a display device (not shown) built in the optical engine 2402. Note that the display device may be a method using three or a single device, and may be a transmissive display device or a reflective display device.
[0134]
FIG. 9F shows a rear projector, which includes a main body 2501, an optical engine 2402 including a light source, an optical system lens, and a display device, a light source 2502, reflectors 2503 and 2504, a screen 2505, and the like. The present invention can be used for a display device (not shown) built in the optical engine 2502. Note that the display device may be a method using three or a single device, and may be a transmissive display device or a reflective display device.
[0135]
Note that the electro-optical device according to the present embodiment may be manufactured using a configuration including any combination of the first to eighth embodiments.
[0136]
【The invention's effect】
By implementing the present invention, the manufacturing process of an electro-optical device such as a liquid crystal display device or an EL display device can be simplified, and the manufacturing cost can be reduced. In addition, a highly reliable electro-optical device can be manufactured at such a low cost.
[0137]
Furthermore, the manufacturing cost of the electronic device can be reduced by mounting an inexpensive electro-optical device obtained by implementing the present invention. Thus, the present invention is a very useful technology in the industry.
[Brief description of the drawings]
FIGS. 1A and 1B illustrate a manufacturing process of a pixel portion and a driver circuit. FIGS.
FIGS. 2A and 2B illustrate a manufacturing process of a pixel portion and a driver circuit. FIGS.
FIGS. 3A and 3B are diagrams illustrating a manufacturing process of a pixel portion and a driver circuit. FIGS.
FIGS. 4A and 4B illustrate a manufacturing process of a pixel portion and a driver circuit. FIGS.
FIG. 5 is a diagram showing an LDD structure of an n-channel TFT.
FIG. 6 is a perspective view of an active matrix liquid crystal display device.
FIGS. 7A to 7C illustrate a manufacturing process of a pixel portion and a driver circuit. FIGS.
FIGS. 8A and 8B illustrate a manufacturing process of a pixel portion and a driver circuit. FIGS.
FIG 9 illustrates an example of an electronic device.
[Explanation of symbols]
101 substrate
102 Base film
103 crystalline semiconductor film
104 crystalline semiconductor film
105-108 active layer
109 Protective film
110-113 Active layer in which p-type impurity region (b) is formed
115-118 n-type impurity region (b)
119 Gate insulation film
120 conductive film
121a to 121f, 149 resist mask
122-124, 125a, 125, 126 Gate wiring
127-136 n-type impurity region (a)
137-141 Gate wiring
142-148 n-type impurity region (c)
150, 151 p-type impurity region (a)
152 First interlayer insulating film
153 to 157 channel formation region
158 Second interlayer insulating film
159-162 Source wiring
163 to 166 Drain wiring
167 Passivation film
168 Third interlayer insulating film
169, 170 Pixel electrode

Claims (6)

Forming an amorphous semiconductor film on the substrate;
Heat-treating the amorphous semiconductor film to change it to a semiconductor film containing a crystalline structure,
Forming a plurality of active layers from a semiconductor film including the crystalline structure;
Wherein among the plurality of active layers, the n-type impurity element is selectively added to the active layer included in the n-channel type TFT after some later forms a region serving as the LDD region,
Forming a gate insulating film on the plurality of active layers;
Forming a conductive film provided on the gate insulating film;
A resist mask is formed on the conductive film, patterning is performed to form a first shape gate wiring,
Using the first shape gate wiring as a mask, an n-type impurity element is added to an active layer later included in the n-channel TFT among the plurality of active layers,
Using the resist mask, a part of the first shape gate wiring except at least a lowermost conductive film is etched to form a second shape gate wiring. Forming,
Of the plurality of active layers, the conductive film of the lowermost layer among the conductive films that are stacked on the active layer later included in the n-channel TFT among the plurality of active layers using the gate wiring of the second shape as a mask. An n-type impurity element is added through the second shape gate wiring to form the LDD region, the source region, and the drain region that overlap with a part of the second shape gate wiring;
A method for manufacturing an electro-optical device, wherein a source region and a drain region are formed by adding a p-type impurity element to an active layer later included in a p-channel TFT among the plurality of active layers. Forming an amorphous semiconductor film on the substrate;
Heat treatment is performed in a state in which a catalytic element that promotes crystallization is retained, and the amorphous semiconductor film is changed to a semiconductor film including a crystalline structure,
Forming a plurality of active layers from a semiconductor film including the crystalline structure;
Wherein among the plurality of active layers, the n-type impurity element is selectively added to the active layer included in the n-channel type TFT after some later forms a region serving as the LDD region,
Forming a gate insulating film on the plurality of active layers;
Forming a conductive film provided on the gate insulating film;
A resist mask is formed on the conductive film, patterning is performed to form a first shape gate wiring,
Using the first shape gate wiring as a mask, an n-type impurity element is added to an active layer later included in the n-channel TFT among the plurality of active layers,
Using the resist mask, a part of the first shape gate wiring except at least a lowermost conductive film is etched to form a second shape gate wiring. Forming,
Of the plurality of active layers, the conductive film of the lowermost layer among the conductive films that are stacked on the active layer later included in the n-channel TFT among the plurality of active layers using the gate wiring of the second shape as a mask. An n-type impurity element is added through the second shape gate wiring to form the LDD region, the source region, and the drain region that overlap with a part of the second shape gate wiring;
A method for manufacturing an electro-optical device, wherein a source region and a drain region are formed by adding a p-type impurity element to an active layer later included in a p-channel TFT among the plurality of active layers. According to claim 1 or claim 2, a method for manufacturing an electro-optical device, characterized in that the step of etching the part of the gate line of the first shape is isotropic dry etching. In any one of claims 1 to 3, conductive film formed by the laminated electro-optical characterized by comprising a two-layer structure which is formed in the order of the first conductive film, the second conductive film Device fabrication method. 5. The method for manufacturing an electro-optical device according to claim 4 , wherein the step of etching part of the first shape gate wiring includes etching only the second conductive film. In any one of claims 1 to 5, tantalum conductive film formed by the stacked, titanium, molybdenum, tungsten, chromium, a metal film containing an element selected from niobium, or the element A method for manufacturing an electro-optical device, wherein a metal compound film containing a main component or an alloy film containing the element as a main component is stacked and used.

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