JP4245739B2 - Method for manufacturing electro-optical device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing an electro-optical device having an element or a circuit formed of a thin film transistor (hereinafter referred to as TFT) on a substrate having an insulating surface. The present invention also relates to an electronic device including an electro-optical device manufactured using the present invention.
[0002]
[Prior art]
Development of an electro-optical device having an integrated circuit formed of TFTs on a substrate is in progress. Liquid crystal display devices, EL display devices, or contact image sensors are known as representative examples. In particular, a TFT using a polysilicon film (polycrystalline silicon film) as an active layer (hereinafter referred to as poly-Si TFT) has a field effect transfer compared to a TFT using a conventional amorphous silicon film (hereinafter referred to as a-Si TFT). It is attracting attention because of its high degree.
[0003]
As electro-optical devices using poly-Si TFTs, liquid crystal display devices are currently attracting much attention and are already appearing on the market. However, although poly-Si TFTs have high performance, they are more expensive to manufacture than a-Si TFTs. Therefore, reducing the manufacturing cost of poly-Si TFTs has become an important issue in securing the market for liquid crystal display devices using poly-Si TFTs.
[0004]
[Problems to be solved by the invention]
It is an object of the present invention to improve the manufacturing yield of TFTs by reducing the number of masks required for patterning, and to reduce the manufacturing cost of electro-optical devices using TFTs. An object of the present invention is to provide a technique for reducing the manufacturing cost of an electro-optical device, thereby reducing the manufacturing cost of an electronic device including the electro-optical device.
[0005]
[Means for Solving the Problems]
In the present invention, by suppressing the number of patterning steps (photolithography steps) used in the TFT manufacturing process as much as possible, a manufacturing process with a high yield that is not affected by the patterning accuracy is realized, and the manufacturing cost of the electro-optical device is reduced. In order to reduce the number of masks, each impurity region (source region, drain region or LDD region) of the gate wiring and the active layer is formed in a self-aligned manner by backside exposure using a light shielding film provided under the active layer. To do.
[0006]
DETAILED DESCRIPTION OF THE INVENTION
The embodiment of the present invention will be described in detail with reference to the following examples.
[0007]
[Example 1]
An embodiment of the present invention will be described with reference to FIGS. Here, a method for simultaneously manufacturing a pixel portion and a driver circuit provided around the pixel portion will be described. However, in order to simplify the description, regarding the drive circuit, a CMOS circuit which is a basic circuit such as a shift register circuit and a buffer circuit, and an n-channel TFT forming a sampling circuit are illustrated.
[0008]
In FIG. 1A, a glass substrate or a quartz substrate is preferably used as the substrate 101, but any substrate may be used as long as it is light-transmitting. If heat resistance permits, a plastic substrate can be used.
[0009]
Next, light shielding films 102a to 102f made of a light-shielding thin film are formed on the surface of the substrate 101 on the side where the TFT is formed. As the light-shielding thin film, an aluminum film, a tantalum film, a tungsten film, a titanium film, a conductive film such as an alloy film or a silicide film thereof, an insulating film in which a pigment or a carbon-based material is dispersed, or the like can be used. .
[0010]
The light shielding films 102a to 102f should be as thin as possible, and preferably 100 to 200 nm. Further, the edge portion of the light shielding film is preferably tapered. By doing so, the flatness of the thin film formed on the light shielding film is increased as much as possible.
[0011]
Here, the first patterning step is performed. At the same time, an alignment marker used for alignment in future patterning is formed using the conductive film. In this embodiment, since the alignment marker can be formed simultaneously with the formation of the light shielding film, it is possible to prevent the trouble of separately forming the alignment marker (an increase in the patterning process).
[0012]
Next, the base film 103 made of an insulating film containing silicon (silicon) (referred to generically as a silicon oxide film, a silicon nitride film, or a silicon nitride oxide film in this specification) is formed over the light shielding films 102a to 102f by plasma. It is formed to a thickness of 100 to 400 nm by CVD or sputtering.
[0013]
Note that in this specification, a silicon nitride oxide film is an insulating film expressed by SiOxNy and indicates an insulating film containing silicon, oxygen, and nitrogen at a predetermined ratio. In this embodiment, as the base film 102, a 100-nm-thick silicon nitride oxide film containing nitrogen at 20 to 50 atomic% (typically 20 to 30 atomic%) and nitrogen at 1 to 20 atomic% (typically 5 to 5) are used. A laminated film with a silicon nitride oxide film having a thickness of 200 nm including 10 atomic%) is used. The thickness need not be limited to this value. In addition, the content ratio (atomic% ratio) of nitrogen and oxygen contained in the silicon nitride oxide film may be 3: 1 to 1: 3 (typically 1: 1). The silicon nitride oxide film is made of SiH. _Four And N ₂ O and NH _Three May be produced as a source gas.
[0014]
Next, an amorphous silicon film (not shown) having a thickness of 30 to 120 nm (preferably 50 to 70 nm) is formed on the base film 103 by a known film formation method. Note that the semiconductor film is not limited to an amorphous silicon film, and may be a semiconductor film including an amorphous structure. The semiconductor film including an amorphous structure includes an amorphous semiconductor film and a microcrystalline semiconductor film, and further includes a compound semiconductor film including an amorphous structure such as a silicon germanium film having an amorphous structure. Moreover, if it forms with the said film thickness, the film thickness of the active layer when TFT is finally completed will be 10-100 nm (preferably 30-50 nm).
[0015]
Then, the polysilicon film 104 is formed according to the technique described in Japanese Patent Laid-Open No. 7-130552 (corresponding to USP 5,643,826). The technology described in this publication is a catalyst element (one or more kinds of elements selected from nickel, cobalt, germanium, tin, lead, palladium, iron, and copper, which is representative of a catalyst element that promotes crystallization when an amorphous silicon film is crystallized. Specifically, it is a crystallization means using nickel).
[0016]
Specifically, heat treatment is performed with the catalytic element held on the surface of the amorphous silicon film to change the amorphous silicon film into a polysilicon film. In this embodiment, the technique described in the first embodiment of the publication is used, but the technique described in the second embodiment may be used. In this embodiment, a polysilicon film is used as an example. However, the present invention is not limited to the polysilicon film, and any semiconductor film including a crystalline structure (including a single crystal silicon film) may be used. (Fig. 1 (A))
[0017]
Although depending on the amount of hydrogen contained in the amorphous silicon film, it is preferable that the dehydrogenation treatment is performed by heating at 400 to 550 ° C. for several hours, and the crystallization step is performed with the amount of hydrogen contained being 5 atom% or less. Further, the amorphous silicon film may be formed by other manufacturing methods such as a sputtering method or a vapor deposition method, but it is desirable to sufficiently reduce impurity elements such as oxygen and nitrogen contained in the film.
[0018]
Here, since the base film and the amorphous silicon film can be formed by the same film formation method, they may be formed continuously. After the formation of the base film, it is possible to prevent surface contamination by preventing exposure to the air atmosphere and to reduce variation in characteristics of the manufactured TFT.
[0019]
Next, the polysilicon film 104 is irradiated with light (laser light) emitted from a laser light source (hereinafter referred to as laser annealing) to form a polysilicon film 105 with improved crystallinity. As the laser beam, a pulse oscillation type or continuous oscillation type excimer laser beam is desirable, but a continuous oscillation type argon laser beam may be used. Further, the beam shape of the laser light may be linear or rectangular. (Fig. 1 (B))
[0020]
Further, instead of laser light, light emitted from a lamp (hereinafter referred to as lamp light) may be irradiated (hereinafter referred to as lamp annealing). As the lamp light, lamp light emitted from a halogen lamp, an infrared lamp, or the like can be used. In addition, furnace annealing using an electric furnace can be used together or substituted.
[0021]
In this embodiment, the laser annealing process is performed by processing pulsed excimer laser light into a linear shape. The laser annealing conditions are as follows: XeCl gas is used as the excitation gas, the processing temperature is room temperature, the pulse oscillation frequency is 30 Hz, and the laser energy density is 250 to 500 mJ / cm. ² (Typically 350-400mJ / cm ² ).
[0022]
The laser annealing step performed under the above conditions has the effect of completely crystallizing the amorphous region remaining after thermal crystallization and reducing defects in the already crystallized crystalline region. Such an effect can also be obtained by optimizing the lamp annealing conditions.
[0023]
Next, resists 106a to 106f are formed by a backside exposure method using the light shielding films 102a to 102f. At this time, the conditions are such that the pattern shapes of the light shielding film and the resist are substantially the same.
[0024]
Then, an impurity element imparting n-type (hereinafter referred to as n-type impurity element) is added using resists 106a to 106f as masks to form impurity regions 107a to 107f exhibiting n-type. Note that as the n-type impurity element, an element belonging to Group 15 typically, phosphorus or arsenic can be used.
[0025]
In this embodiment, phosphine (PH _Three N-type impurity regions 107a to 107f are formed by an ion doping method using the above. The concentration of phosphorus in this region is 1 × 10 ²⁰ ~ 1x10 ^{twenty one} atoms / cm ^Three (Typically 2 × 10 ²⁰ ~ 5x10 ^{twenty one} atoms / cm ^Three ). In this specification, an impurity region containing an n-type impurity element in the above concentration range is defined as an n-type impurity region (a). (Figure 1 (C))
[0026]
In addition, all the density | concentrations described in this specification are the measured values when measuring in the minimum density | concentration area | region by SIMS (mass secondary ion analysis).
[0027]
Next, after removing the resists 106a to 106f, a protective film 108 made of an insulating film containing silicon is formed. This protective film 108 has a meaning for preventing the polysilicon film from being directly exposed to plasma when impurities are added and for enabling fine concentration control. Further, the thickness of the protective film 108 plays a role of controlling the amount of light sneak when performing the subsequent back surface exposure process.
[0028]
The amount of light sneaking determines the width (length) of the LDD region of the n-channel TFT. In this embodiment, since the amount of light sneaking is set to 0.3 to 1.0 μm, the thickness of the protective film 108 is set to 0.2 to 1.0 μm. However, since the amount of wraparound can be controlled by the exposure conditions, it is not necessary to limit to this film thickness.
[0029]
Next, an impurity element imparting p-type conductivity (hereinafter referred to as a p-type impurity element) is added through the protective film 108. As the p-type impurity element, typically, an element belonging to Group 13, typically boron or gallium can be used. This step (referred to as channel doping step) is a step for controlling the threshold voltage of the TFT. Here, diborane (B ₂ H ₆ Boron is added by an ion doping method using
[0030]
Thus 1 × 10 ¹⁵ ~ 1x10 ¹⁸ atoms / cm ^Three (Typically 5 × 10 ¹⁶ ~ 5x10 ¹⁷ atoms / cm ^Three ) Regions 109a to 109f to which a p-type impurity element (boron in this embodiment) is added are formed. Note that in this specification, an impurity region containing a p-type impurity element in the above concentration range (however, 1 × 10 10 ¹⁶ atoms / cm ^Three An impurity element that imparts n-type at a concentration of typically, except for a region to which phosphorus or arsenic is added) is defined as a p-type impurity region (b). (Figure 1 (D))
[0031]
Further, in this step, boron is also added to a region (region indicated by 109a) which will be a channel formation region of the p-channel TFT later. However, if not necessary, the above step may be performed while being hidden with a resist or the like. . Alternatively, after adding boron to the entire surface, an element belonging to Group 15 (typically phosphorus or arsenic) may be added only to the region indicated by 109a to further adjust the threshold voltage.
[0032]
Next, resists 110a to 110f are formed by a backside exposure method using the light shielding films 102a to 102f. At this time, the resists 110a to 110f are formed in a pattern that is reduced to the inside of the light shielding film by the light traveling inside the light shielding film. In this embodiment, the thickness of the protective film 108 is set to 0.3 μm, and the amount of light wraparound is adjusted to 0.3 μm. That is, on each light shielding film, a resist having a pattern in which each light shielding film is reduced inward by 0.3 μm is formed. (Figure 1 (E))
[0033]
Next, the protective film 108 is patterned using the resists 110a to 110f as masks to form patterned protective films 111a to 111f. Then, an n-type impurity element is added by an ion doping method as it is to form n-type impurity regions 112a to 112k. At this time, an impurity element may be added after removing the resists 110a to 110f. (Fig. 2 (A))
[0034]
These low-concentration impurity regions 112a to 112k are impurity regions that will later become LDD regions of n-channel TFTs or regions that become part of the lower electrode of the storage capacitor. Note that the impurity region formed here contains 2 × 10 n-type impurity elements. ¹⁶ ~ 5x10 ¹⁹ atoms / cm ^Three (Typically 5 × 10 ¹⁷ ~ 5x10 ¹⁸ atoms / cm ^Three ) Concentration. In this specification, an impurity region containing an n-type impurity element in the above concentration range is defined as an n-type impurity region (b).
[0035]
Next, the polysilicon film is patterned to form island-shaped semiconductor films (hereinafter referred to as active layers) 114 to 118. Here, the second patterning step is performed. Note that 114 is an active layer of a p-channel TFT, 115 to 117 are active layers of an n-channel TFT, and 118 is a lower electrode of a storage capacitor. (Fig. 2 (B))
[0036]
Note that it is also effective to add the added n-type impurity element or p-type impurity element by performing laser annealing, furnace annealing, or a combination of both before performing the patterning step of FIG. When such an activation step is introduced, an intrinsic region (p-type impurity region (b) also exists at the boundary between the n-type impurity regions (b) 112a to 112k, that is, around the n-type impurity region (b). The joint portion becomes clear. This means that when the TFT is later completed, the LDD region and the channel formation region can form a very good junction.
[0037]
Next, as shown in FIG. 2C, a gate insulating film 119 is formed so as to cover the active layers 114 to 118. The gate insulating film 119 may be formed to a thickness of 10 to 200 nm, preferably 50 to 150 nm. In this embodiment, plasma CVD is used for N. ₂ O and SiH _Four A silicon nitride oxide film is formed to a thickness of 80 nm using as a raw material.
[0038]
Next, a conductive film (not shown) to be a gate wiring (including a gate electrode) is formed. This conductive film is formed of a material that transmits the exposure light irradiated from the exposure apparatus. Specifically, it is desirable to transmit one of the lights included in the wavelength range from 0.71 nm (X-ray) to 436 nm (g-line).
[0039]
In this embodiment, since a silicon film to which an n-type impurity element is added is used as the conductive film, light having a wavelength of 350 nm or more, typically i-line (365 nm), g-line (436 nm), or h-line (405 nm) is used. Backside exposure is possible. In addition, when an ITO (indium tin oxide) film, a tin oxide film, an ITO film added with zinc, or a tin oxide film added with zinc is used as the conductive film, light having a wavelength of 400 nm or more (g-line or h-line) is used. By using it, back surface exposure becomes possible.
[0040]
Note that in the case of using an ITO film, a tin oxide film, an ITO film to which zinc is added, or a tin oxide film to which zinc is added, the resistivity can be lowered by adding fluorine at the time of film formation.
[0041]
Next, the conductive film is patterned by a backside exposure method to form a conductive film pattern 120 having a thickness of 400 nm, gate wirings 120 to 124, and a capacitor wiring 125 serving as an upper electrode of a storage capacitor. At this time, the gate wirings 121 to 124 are formed so as to overlap a part of the n-type impurity regions (b) 112b to 112i via the gate insulating film. This structure may be adjusted according to exposure conditions, or may be adjusted by the film thickness of the gate insulating film 119 or the conductive film to be a gate wiring. (Fig. 2 (C))
[0042]
Next, resists 126a and 126b are formed. Here, a third patterning step is performed. Next, the conductive film pattern 120 is etched using the resists 126a and 126b as a mask to form a gate wiring 127 of a p-channel TFT.
[0043]
Further, in this state, a p-type impurity element (boron in this embodiment) is added to form impurity regions 128a and 128b containing boron at a high concentration. Here, diborane (B ₂ H ₆ 3 × 10 by ion doping method using ²⁰ ~ 3x10 ^{twenty one} atoms / cm ^Three (Typically 5 × 10 ²⁰ ~ 1x10 ^{twenty one} atoms / cm ^Three ) Add boron at a concentration. In this specification, an impurity region containing a p-type impurity element in the above concentration range is defined as a p-type impurity region (a). (Fig. 2 (D))
[0044]
Note that phosphorus is already added to part of the impurity region 128b (the above-described n-type impurity region (b) 112a), but boron added here is added at a concentration at least three times that of the impurity region 128b. Therefore, the n-type impurity region formed in advance is completely inverted to the P-type and functions as a P-type impurity region.
[0045]
Next, after removing the resist masks 126a and 126b, a first interlayer insulating film 129 is formed. The first interlayer insulating film 129 may be formed using an insulating film containing silicon, specifically, a silicon nitride film, a silicon oxide film, a silicon nitride oxide film, or a stacked film including a combination thereof. The film thickness may be 50 to 400 nm (preferably 100 to 200 nm).
[0046]
In this example, SiH is used by plasma CVD. _Four , N ₂ O, NH _Three As a source gas, a 200 nm thick silicon nitride oxide film (however, the nitrogen concentration is 25 to 50 atomic%) is used. The first interlayer insulating film 129 has an effect of preventing the gate wirings 121 to 124 and 127 and the capacitor wiring 125 made of a silicon film from being oxidized in a heat treatment process (activation process) to be performed next.
[0047]
Thereafter, a heat treatment step (activation step) is performed to activate the n-type or p-type impurity element added at each concentration. This step can be performed by a furnace annealing method, a laser annealing method, or a rapid thermal annealing method (RTA method). Here, the activation process is performed by furnace annealing. In this heat treatment step, heat treatment is performed in a nitrogen atmosphere at 300 to 650 ° C., preferably 400 to 550 ° C., here 550 ° C. for 4 hours.
[0048]
At this time, the catalyst element (nickel in this embodiment) used for crystallization of the amorphous silicon film in this embodiment moves and is captured (gettered) in a region containing phosphorus. This is a phenomenon caused by the gettering effect of the metal element by phosphorus. As a result, in all TFTs, the concentration of the catalyst element in the channel formation region is 1 × 10. ¹⁷ atoms / cm ^Three It becomes as follows. However, in the case of nickel, 1 × 10 ¹⁷ atoms / cm ^Three The following are the lower limits of SIMS measurement, and cannot be measured with the current technology.
[0049]
Conversely, in the region where the catalytic element is gettered, the catalytic element is segregated at a high concentration, resulting in 5 × 10 5. ¹⁸ atoms / cm ^Three Above (typically 1 × 10 ¹⁹ ~ 5x10 ²⁰ atoms / cm ^Three ) Become present in concentration. However, since the region serving as the gettering site only needs to function as a source region or a drain region, the presence or absence of nickel is not considered to be a problem.
[0050]
Next, a process of hydrogenating the active layer is performed by performing a heat treatment at 300 to 450 ° C. for 1 to 12 hours in an atmosphere containing 3 to 100% hydrogen. This step is a step of terminating dangling bonds in the semiconductor layer with thermally excited hydrogen. As another means of hydrogenation, plasma hydrogenation (using hydrogen excited by plasma) may be performed.
[0051]
When the activation process is completed, a second interlayer insulating film 130 having a thickness of 500 nm to 2.0 μm is formed on the first interlayer insulating film 129. In this embodiment, an insulating film (hereinafter referred to as a resin insulating film) made of a resin material (or an organic material) is used as the second interlayer insulating film 130. As the resin material, polyimide, acrylic, polyamide, polyimide amide, BCB (benzocyclobutene), or the like can be used.
[0052]
The advantages of using a resin insulating film are that the film formation method (typically spin coating) is simple, the relative dielectric constant is low, parasitic capacitance can be reduced, and flatness is excellent. Raised. A resin insulating film or an organic SiO compound other than those described above can also be used. In addition, the second interlayer insulating film 130 may be a laminated structure, and some layers may be colored with a pigment or the like to be used as a color filter.
[0053]
Next, a transparent conductive film (ITO film in this embodiment) is formed on the second interlayer insulating film 130, and a pixel electrode 131 is formed by performing a fourth patterning step. Although the film thickness is 110 nm, the film thickness can be reduced by adding fluorine.
[0054]
Thereafter, contact holes reaching the source region or drain region of each TFT are formed. Here, the fifth patterning step is performed. Then, source wirings 132 to 135 and drain wirings 136 to 138 are formed. Here, the sixth patterning step is performed. In this embodiment, these wirings are laminated films having a three-layer structure in which a Ti film is formed with a thickness of 100 nm, an aluminum film containing Ti with a thickness of 300 nm, and a Ti film with a thickness of 150 nm. Of course, it is not necessary to limit to this structure.
[0055]
Although not shown in this embodiment, an insulating film made of a resin material is provided on the source wiring and the drain wiring, and planarization by etching (referred to as an etch-back process) is performed. It is also effective to relieve the step at the pattern edge and the step due to the contact hole.
[0056]
Thus, a substrate (hereinafter referred to as an active matrix substrate) having a driving circuit and a pixel portion on the same substrate is completed. The number of patterning required to complete so far is six, and it can be said that the number of patterning is very small as a method of manufacturing an active matrix substrate having a top gate structure using poly-Si TFTs.
[0057]
Further, as shown in FIG. 3, when the active matrix substrate is completed, an alignment film 139 is formed on the pixel electrode 131 and a rubbing process is performed. Although not shown, the alignment film 139 can be formed after a spacer made of a resin material is formed at a predetermined position of the pixel portion.
[0058]
Next, a light-shielding film 141a, a color filter 142, a planarizing film (overcoat agent) 143, a counter electrode 144 made of a transparent conductive film, and an alignment film 145 are formed on the light-transmitting substrate 140 and subjected to rubbing treatment to face each other. A substrate is produced.
[0059]
Then, after forming a sealant (not shown) on the active matrix substrate, the active matrix substrate and the counter substrate are bonded together, and the liquid crystal 146 is sealed in a region surrounded by the sealant. Thus, a liquid crystal display device having a structure as shown in FIG. 3 is completed.
[0060]
In FIG. 3, a p-channel TFT 301 and n-channel TFTs 302 and 303 are formed in the driver circuit, and a pixel TFT 304 and a storage capacitor 305 that are n-channel TFTs are formed in the pixel portion.
[0061]
In the p-channel TFT 301 forming the CMOS circuit of the driving circuit, a channel formation region 201 and a source region 202 and a drain region 203 made of a p-type impurity region (a) are formed. All these impurity regions are formed in a self-aligned manner.
[0062]
In addition, an n-channel TFT 302 which forms a CMOS circuit of a driver circuit includes a channel formation region 204, a source region 205, a drain region 206, and an LDD region 207 partially overlapping with the gate wiring with the channel formation region interposed therebetween. 208 is formed. At this time, the LDD regions 207 and 208 are 2 × 10. ¹⁶ ~ 5x10 ¹⁹ atoms / cm ^Three It is formed so as to contain phosphorus at a concentration of and to partially overlap the gate wiring. All these impurity regions are formed in a self-aligned manner.
[0063]
When a part of the LDD region overlaps with the gate wiring, the LDD region includes a region overlapping with the gate wiring and a region not overlapping with the gate wiring. The LDD region overlapping with the gate wiring can reduce deterioration due to hot carrier injection. This is generally known, but has the disadvantage that off current (drain current that flows when the TFT is off) increases. However, when an LDD region that does not overlap with the gate wiring is provided adjacent to the LDD region that overlaps with the gate wiring as in this embodiment, an increase in off-current can be effectively suppressed.
[0064]
In the n-channel TFT 303 forming the sampling circuit, a channel formation region 209, a source region 210, a drain region 211, and LDD regions 212 and 213 are formed on both sides of the channel formation region. Also in this structure, part of the LDD regions 212 and 213 is arranged so as to overlap with the gate wiring. The effect is the same as that of the n-channel TFT 302. These impurity regions are all formed in a self-aligned manner.
[0065]
The pixel TFT 304 disposed in the pixel portion includes n-type impurity regions (a) 222 in contact with the channel formation regions 214 and 215, the source region 216, the drain region 217, the LDD regions 218 to 221, and the LDD regions 219 and 220. Is formed. At this time, the source region 216 and the drain region 217 are each formed of an n-type impurity region (a), and the LDD regions 218 to 221 are formed of an n-type impurity region (b). The LDD regions 218 to 221 partially overlap with the gate wiring. The effect is the same as that of the n-channel TFT 302. These impurity regions are all formed in a self-aligned manner.
[0066]
The drain region 217 is extended and connected to the semiconductor region 223. The capacitor wiring 125 overlaps with the gate insulating film 119 interposed therebetween. At this time, a storage capacitor 305 including the semiconductor region 223, the gate insulating film 119, and the capacitor wiring 125 is formed.
[0067]
Of the LDD regions 207, 208, 212, 123, and 218 to 221 of the n-channel TFTs 302, 303, and 304, the length (width) of the region overlapping with the gate wiring is 0.3 to 1.0 μm, and the gate wiring The length (width) of the region that does not overlap with the substrate may be 0.5 to 1.5 μm.
[0068]
[Example 2]
In this example, the appearance of the liquid crystal display device manufactured in Example 1 will be described. The perspective view of FIG. 4 is used for the description. The active matrix substrate includes a pixel portion 402, a gate signal side driver circuit 403, and a source signal side driver circuit 404 formed on the substrate 401. A pixel electrode 406 and a storage capacitor 407 are connected to the pixel TFT 405 in the pixel portion. The storage capacitor 305 shown in Embodiment 1 is used for this storage capacitor 407.
[0069]
Further, the drive circuit provided in the periphery is configured based on a CMOS circuit. The gate signal side driver circuit 403 and the source signal side driver circuit 404 are connected to the pixel portion 402 by a gate wiring 408 and a source wiring 409, respectively. The FPC 410 is provided with input / output wirings (connection wirings) 411 and 412 for transmitting signals to the drive circuit. Reference numeral 413 denotes a counter substrate.
[0070]
In this specification, the electro-optical device shown in FIG. 4 is called a liquid crystal display device, but a state where an FPC is attached as shown in FIG. 4 is generally called a liquid crystal module. Therefore, the liquid crystal display device in this embodiment may be called a liquid crystal module.
[0071]
[Example 3]
In this example, a case where a liquid crystal display device is manufactured through a manufacturing process different from that of Example 1 is described. FIG. 5 is used for the description.
[0072]
First, the steps up to FIG. However, in this embodiment, a 150 nm silicon oxide film 501 a and a 1 μm thick polyimide film 501 b are formed as the protective film 108. Thereafter, resists 110a to 110f are formed in the same manner as in FIG. (Fig. 5 (A))
[0073]
Note that the important point here is that the protective film 108 has a laminated structure, and the layer above it can be selectively removed leaving a part of the layer. Therefore, if a silicon oxide film is used as the film indicated by 501a, it is possible to use a resin material other than the polyimide film as the film indicated by 501b. In addition, if a silicon nitride film is used as the film indicated by 501a, a silicon oxide film can also be used as the film indicated by 501b. Of course, the same material may be used, and the difference between the etching rates of the two may be used for the configuration of this embodiment.
[0074]
Next, the polyimide film 501b is etched using the resists 110a to 110f as masks to form polyimide patterns 502a to 502f. At this time, the polyimide film 501b is etched by a dry etching method using oxygen gas, but the underlying silicon oxide film 501a remains without being etched.
[0075]
In this state, an n-type impurity element is added. Addition conditions are the same as those in the process of FIG. 2A of Example 1, and n-type impurity regions (b) 112a to 112k are formed. (Fig. 5 (B))
[0076]
In the case of this embodiment, the n-type impurity element addition step is performed with the protective film remaining on the polysilicon film, so that the impurity element concentration can be easily controlled.
[0077]
Thereafter, the polyimide patterns 502a to 502f and the silicon oxide film 501a are removed and the polysilicon film is patterned to form active layers 114 to 118. (Fig. 5 (C))
[0078]
The subsequent steps may follow the steps after FIG. 2B of the first embodiment. Needless to say, the configuration of this example is obtained by improving some of the steps in Example 1, and may be implemented in manufacturing the liquid crystal display device of Example 2.
[0079]
[Example 4]
In this example, a case where a liquid crystal display device is manufactured through a manufacturing process different from that of Example 1 is described. FIG. 6 is used for the description.
[0080]
This embodiment is characterized in that the step shown in FIG. 6 is added after the step shown in FIG. That is, after the step shown in FIG. 2D, the resists 126a and 126b are removed, and new resists 601a and 601b are formed.
[0081]
In that state, an n-type impurity element addition step is performed under the same conditions as in the step shown in FIG. At this time, the n-type impurity element is added in a self-aligning manner using the gate wiring 121 as a mask, and n-type impurity regions (a) 602 and 603 are formed. At the same time, n-type impurity regions (b) 604 and 605 are defined.
[0082]
At this time, the n-type impurity regions (b) 604 and 605 are LDD regions completely overlapping the gate wiring 121. That is, in the active matrix substrate shown in FIG. 4, the LDD region of the n-channel TFT 302 is formed by the n-type impurity regions (b) 604 and 605 of this embodiment.
[0083]
The LDD region that completely overlaps with the gate wiring is suitable for a TFT that needs to operate at a high speed because the carrier component moves faster and has a smaller resistance component. Therefore, it is suitable for a TFT for forming a circuit that needs to operate at several MHz to several tens of MHz, such as a shift register.
[0084]
Note that the steps after FIG. 6 may follow the steps after FIG. Needless to say, the configuration of this example is obtained by improving some of the steps in Example 1, and may be implemented in manufacturing the liquid crystal display device of Example 2. Moreover, the combination with Example 3 is also easy.
[0085]
[Example 5]
In this example, a case where a liquid crystal display device is manufactured through a manufacturing process different from that of Example 1 is described. FIG. 7 is used for the description. In addition, the code | symbol used in Example 1 is quoted as needed.
[0086]
First, the process up to the step of FIG. However, the gate wiring (hereinafter referred to as the first gate wiring) provided in the pixel portion is characterized in that it is formed as an independent pattern for each pixel as indicated by reference numerals 701 and 702 in FIG. 7A. . That is, the first gate wiring is formed in each pixel, but is electrically isolated between the pixels.
[0087]
After the step shown in FIG. 2D, next, the resists 126a and 126b are removed, and an activation step is performed at a temperature of 450 to 550 ° C. in that state. In the case of Example 1, since the silicon film is used as the material of the first gate wiring, oxide or nitride is formed on the surface.
[0088]
Next, the oxide or nitride is removed with a hydrofluoric acid-based etching solution. In this case, the gate insulating film is also etched, but it is not a problem as much as the oxide or nitride film is thin.
[0089]
After the oxide or nitride formed on the surfaces of the first gate wirings 701 and 702 is removed in this way, an alloy film containing aluminum or copper as a main component or a laminated film of these and another metal film is formed. Any material may be used as long as it is a conductive film, but a conductive film having a low resistivity is preferable.
[0090]
Then, the conductive film is patterned to form the second gate wiring 703. The second gate wiring 703 is used as a bus line for connecting in series a first gate wiring provided electrically isolated for each pixel.
[0091]
This state is shown in FIG. FIG. 7B shows a cross-sectional view taken along line AA ′ of the top view of FIG. In this way, the first gate lines are electrically connected to each other by the second gate line 703 provided in contact with the first gate lines 701 and 702.
[0092]
A known transparent conductive film typified by an ITO film can be used as the first gate wiring. In this case, the surface treatment of the first gate wiring can be omitted as long as an ohmic contact with the second gate wiring can be ensured.
[0093]
When the second gate wiring 703 is thus formed, a first interlayer insulating film 129 is formed, and hydrogenation is performed according to the first embodiment. Of course, hydrogenation treatment may be performed before the first interlayer insulating film 129 is formed. Further, the subsequent steps may be performed according to the first embodiment. Furthermore, the configuration of this embodiment is a partial improvement of the first embodiment, and may be implemented when the liquid crystal display device of the second embodiment is manufactured.
[0094]
A feature of this embodiment is that a conductive film having a higher resistivity than other metal films such as a silicon film and an ITO film is used as a TFT gate wiring, and aluminum is mainly used as a bus line for electrically connecting the gate wiring. A metal film having a relatively low resistivity, such as an alloy film as a component, is used.
[0095]
In the present invention, since it is necessary to use a material capable of transmitting light in the vicinity of 350 to 450 nm as the electrode (or wiring) functioning as the gate of the TFT, it is difficult to use a metal material having a low resistivity. In that case, only the gate portion of the TFT may be formed of such a material, and each gate may be connected later with a low resistance material.
[0096]
Note that the configuration of this embodiment is obtained by improving a part of the steps in Embodiment 1, and it goes without saying that the liquid crystal display device of Embodiment 2 may be manufactured. Moreover, the combination with Example 3 or Example 4 is also easy.
[0097]
[Example 6]
In this example, a case where a liquid crystal display device is manufactured through a manufacturing process different from that of Example 1 is described. FIG. 8 is used for the description. In addition, the code | symbol used in Example 1 is quoted as needed.
[0098]
First, according to the process of Example 1, the process up to the process of FIG. At this time, resists 801a to 801f are formed on the protective film 108 by backside exposure. (Fig. 8 (A))
[0099]
Next, the protective film 108 is etched using the resists 801a to 801f as masks to form patterned protective films 802a to 802f. (Fig. 8 (B))
[0100]
Next, the patterned protective films 802a to 802f are isotropically etched using the resists 801a to 801f as a mask. In this step, the protective films 802a to 802f are etched from the lateral direction to form patterned protective films 803a to 803f narrower in width than the resists 801a to 801f. (Fig. 8 (C))
[0101]
The subsequent steps may follow the steps from FIG. 2A of the first embodiment, and finally the active matrix substrate as shown in FIG. 3 and the liquid crystal display device as shown in FIG. 4 are completed. To do.
[0102]
In the first embodiment, the widths (lengths) of the n-type impurity regions (b) 112a to 112k are determined by the amount of wraparound light in the backside exposure, whereas in this embodiment, the protective films 802a to 802f are etched from the lateral direction. It is characterized in that the width (length) of the n-type impurity regions (b) 112a to 112k is determined depending on the amount.
[0103]
Note that the configuration of this embodiment is obtained by improving a part of the steps in Embodiment 1, and it goes without saying that the liquid crystal display device of Embodiment 2 may be manufactured. Moreover, the combination with any structure of Examples 3-5 is also easy.
[0104]
[Example 7]
The present embodiment is an embodiment in which the structure of the pixel portion is improved in the active matrix substrate shown in FIG. 3 of the first embodiment. Since the pixel structure is almost the same as that of the first embodiment, only the changed points will be described with reference numerals.
[0105]
In this embodiment, as shown in FIG. 9, after forming the source wiring 901 and the drain wiring 902, the pixel electrode 903 made of a transparent conductive film is formed.
[0106]
Note that the configuration of this embodiment is obtained by improving a part of the steps in Embodiment 1, and it goes without saying that the liquid crystal display device of Embodiment 2 may be manufactured. Moreover, the combination with any structure of Examples 3-6 is also easy.
[0107]
[Example 8]
The present embodiment is an embodiment in which the structure of the pixel portion is improved in the active matrix substrate shown in FIG. 3 of the first embodiment. Since the pixel structure is almost the same as that of the first embodiment, only the changed points will be described with reference numerals.
[0108]
In this embodiment, as shown in FIG. 10, when forming the source wiring 135 in the step of FIG. 2E, the drain wiring 138 is not formed and the contact hole is left open. Thereafter, a pixel electrode 1001 made of a transparent conductive film is formed so as to be connected to the drain region 217.
[0109]
Note that the configuration of this embodiment is obtained by improving a part of the steps in Embodiment 1, and it goes without saying that the liquid crystal display device of Embodiment 2 may be manufactured. Moreover, the combination with any structure of Examples 3-6 is also easy.
[0110]
[Example 9]
In this embodiment, a case where a reflective liquid crystal display device is manufactured by implementing the present invention will be described. In this embodiment, the drain wiring indicated by 138 in FIG. 2E may be formed widely in the pixel and used as a reflective electrode (functioning as a pixel electrode). However, since the pixel electrode is formed in the same layer as the source wiring, attention must be paid to a short circuit between the source wiring and the pixel electrode.
[0111]
Specifically, as illustrated in FIG. 11A, the source wiring 1101 and the drain wiring 1102 are formed in the same layer, and the drain wiring 1102 also serves as a pixel electrode. FIG. 11 shows an example in combination with the structure of the fifth embodiment. Reference numeral 1103 denotes a second gate wiring formed of a low resistance material used as a bus line of the first gate wiring (the first gate wiring in FIG. 7A). Corresponds to a two-gate wiring 703).
[0112]
A cross-sectional view taken along line AA ′ of FIG. 11A is shown in FIG. As shown in FIG. 11B, the drain wiring (pixel electrode) 1102 is formed in a pixel surrounded by a source wiring 1101 and a gate wiring (here, corresponding to the second gate wiring 1103), and the pixel is exclusively used. It is formed so as to occupy most of the area. Although it is necessary to design with a margin so as not to contact the source wiring 1101, the drain wiring 1102 occupies 70 to 95% (typically 80 to 90%) of the area occupied by the pixel. Therefore, the image displayable area is greatly increased as compared with the transmissive liquid crystal display device.
[0113]
Further, according to the present embodiment, since the pixel electrode 131 film forming process and the patterning process in the first embodiment can be omitted, the number of processes is greatly simplified and the number of masks necessary for patterning is up to five. Reduced.
[0114]
Note that the external appearance of the liquid crystal module is the same as that shown in FIG. 4 as a reflective liquid crystal display device. Moreover, you may implement combining the structure of Examples 3-8 with respect to a present Example.
[0115]
[Example 10]
In the manufacturing process of Example 1, an example in which a catalytic element that promotes crystallization is used as a method for forming a semiconductor film including a crystal structure, but in this example, thermal crystallization is performed without using such a catalytic element. A case where a semiconductor film including a crystal structure is formed by crystallization or laser crystallization is shown.
[0116]
In the case of thermal crystallization, a heat treatment step for 15 to 24 hours may be performed at a temperature of 600 to 650 ° C. after forming a semiconductor film including an amorphous structure. That is, by performing heat treatment at a temperature exceeding 600 ° C., natural nuclei are generated and crystallization proceeds.
[0117]
In the case of laser crystallization, a laser annealing process may be performed under the first annealing conditions described in Embodiment 1 after forming a semiconductor film including an amorphous structure. Thus, a semiconductor film including a crystal structure can be formed in a short time. Of course, lamp annealing may be performed instead of laser annealing.
[0118]
Moreover, you may use the technique described in Example 1 of Japanese Patent Application No. 11-76967 application specification. According to the manufacturing process of Example 1 of the same application specification, a polysilicon film having a unique crystal structure can be obtained. For details of this polysilicon film, refer to the applications of Japanese Patent Application No. 10-044659, Japanese Patent Application No. 10-152316, Japanese Patent Application No. 10-152308 or Japanese Patent Application No. 10-152305 filed by the present applicant. It ’s fine.
[0119]
As described above, a semiconductor film including a crystal structure used for a TFT can be formed using any known means. In addition, a present Example can be freely combined with any structure of Examples 1-9.
[0120]
[Example 11]
The configurations shown in Examples 1 to 10 can be applied to the case where an active matrix EL (electroluminescence) display device is manufactured.
[0121]
In an ordinary EL display device, a switching TFT and a current control TFT are formed in a pixel. The n-channel TFT 304 shown in FIG. 3 is suitable for a switching TFT, and an n-channel TFT is used. The TFT 302 is suitable as a current control TFT.
[0122]
Therefore, an active matrix substrate for an EL display device may be manufactured with reference to the configurations of Embodiments 1 to 10, and an active matrix EL display device may be completed using a known EL formation technique.
[0123]
[Example 12]
An inexpensive electro-optical device obtained by carrying out the present invention can be incorporated as a part in any electronic device (electronic product) incorporating a display such as a personal computer.
[0124]
Such electronic devices include video cameras, digital still cameras, projectors (rear type or front type), goggle type displays (head mounted displays), car navigation systems, personal computers, personal digital assistants (mobile computers, mobile phones or electronic devices). A display capable of playing back a recording medium such as a book, etc., and a recording medium (specifically, a compact disc (CD), laser disc (LD), digital video disc (DVD), etc.) And the like). Examples of these semiconductor devices are shown in FIGS.
[0125]
FIG. 8A illustrates a personal computer, which includes a main body 2001, an image receiving portion 2002, a display device 2003, a keyboard 2004, and the like. The present invention can be used for the display device 2004.
[0126]
FIG. 8B illustrates a video camera, which includes a main body 2101, a display device 2102, an audio input portion 2103, operation switches 2104, a battery 2105, an image receiving portion 2106, and the like. The present invention can be used for the display device 2102.
[0127]
FIG. 8C illustrates a goggle-type display which includes a main body 2201, a display device 2202, an arm portion 2203, and the like. The present invention can be used for the display device 2202. However, in practice, the display device 2202 is incorporated with an optical system so as not to obstruct the field of view.
[0128]
FIG. 8D shows an image reproducing device (specifically, a DVD reproducing device) provided with a recording medium, which includes a main body 2301, a recording medium (CD, LD, DVD, etc.) 2302, an operation switch 2303, a display device (a). 2304, a display device (b) 2305, and the like. Although the display device (a) mainly displays image information and the display device (b) mainly displays character information, the present invention can be used for these display devices (a) and (b). Note that the present invention can be used for a CD playback device, a game machine, or the like as an image playback device provided with a recording medium.
[0129]
FIG. 8E illustrates a front type projector, which includes a main body 2401, a light source, an optical system lens including a display system, an optical engine 2402, and the like, and can display an image on a screen 2403. The present invention can be used for a display device (not shown) built in the optical engine 2402. Note that the display device may be a method using three or a single device, and may be a transmissive display device or a reflective display device.
[0130]
FIG. 8F illustrates a rear projector, which includes a main body 2501, an optical engine 2402 including a light source, an optical system lens, and a display device, a light source 2502, reflectors 2503 and 2504, a screen 2505, and the like. The present invention can be used for a display device (not shown) built in the optical engine 2502. Note that the display device may be a method using three or a single device, and may be a transmissive display device or a reflective display device.
[0131]
Note that the electro-optical device according to the present embodiment may be manufactured using a configuration including any combination of the first to twelfth embodiments.
[0132]
【The invention's effect】
By implementing the present invention, the manufacturing process of an electro-optical device such as a liquid crystal display device or an EL display device becomes high, and the manufacturing cost can be reduced. In addition, a highly reliable electro-optical device can be manufactured at such a low manufacturing cost.
[0133]
Furthermore, the manufacturing cost of the electronic device can be reduced by mounting an inexpensive electro-optical device obtained by implementing the present invention. Thus, the present invention is a very useful technology in industry.
[Brief description of the drawings]
FIGS. 1A and 1B illustrate a manufacturing process of a pixel portion and a driver circuit. FIGS.
FIGS. 2A and 2B illustrate a manufacturing process of a pixel portion and a driver circuit. FIGS.
FIGS. 3A and 3B are diagrams illustrating a manufacturing process of an active matrix substrate. FIGS.
FIG. 4 is a perspective view of an active matrix liquid crystal display device.
FIGS. 5A and 5B illustrate a manufacturing process of a pixel portion and a driver circuit. FIGS.
6A and 6B illustrate a manufacturing process of a pixel portion and a driver circuit.
FIG. 7 is a diagram showing a top structure of a pixel portion.
FIGS. 8A and 8B illustrate a manufacturing process of a pixel portion and a driver circuit. FIGS.
FIG. 9 illustrates a cross-sectional structure of a pixel portion.
FIG. 10 is a diagram showing a cross-sectional structure of a pixel portion.
FIGS. 11A and 11B illustrate a cross-sectional structure and a top surface structure of a pixel portion. FIGS.
FIG. 12 illustrates an example of an electronic device.
[Explanation of symbols]
101 substrate
102a to 102f light shielding film
103 Underlayer
104 Polysilicon film
105 Polysilicon film
106a-106e resist
107a to 107f n-type impurity region (a)
108 Protective film
109a to 109f p-type impurity region (b)
110a-110f resist
111a to 111f patterned protective film
112a to 112k n-type impurity region (b)
115-118 active layer
119 Gate insulation film
120 conductive film pattern
121-124, 127 Gate wiring
125 capacity wiring
126a, 126b resist
128a, 128b p-type impurity region (a)
129 First interlayer insulating film
130 Second interlayer insulating film
131 Pixel electrode
132-135 Source wiring
136-138 drain wiring
139, 145 Alignment film
140 substrates
141 Light-shielding film on opposite side
142 Color filter
143 Planarization film (overcoat agent)
144 Counter electrode
146 liquid crystal

Claims (6)

The light shielding film is formed on a base plate,
Forming an insulating film containing silicon on the light shielding film,
Forming a semiconductor film on the insulating film containing silicon;
Forming a first resist having the same size as the light-shielding film on the semiconductor film by backside exposure using the light-shielding film as a mask;
As a mask the first resist, it added not pure element content in a region to be a source region and a drain region of the n-channel type TFT of the semiconductor film,
Forming a protective film on the front Symbol semi conductor film,
Forming a second resist smaller than the first resist on the protective film by backside exposure using the light shielding film as a mask;
In order to form a channel formation region and a low-concentration impurity region of the n-channel TFT , etching is performed so that a part of the protective film remains using the second resist as a mask,
As the second resist and the mask protective film formed by the remaining added non pure element content in a region to be a low concentration impurity region before Symbol n-channel type TFT of the semiconductor film,
Removing the protective film formed by pre-chopped exist,
Patterning the previous SL semi conductor film to form a plurality of active layers,
Forming a gate insulating film in contact with the active layer,
Forming a conductive film which transmits light of a predetermined wavelength on said gate insulating film,
Forming a third resist larger than the second resist on the conductive film by backside exposure using the light shielding film as a mask;
By etching the conductive film using the third resist as a mask to form a gate wiring of the n-channel TFT, and
The region other than the region to be a source region and a drain region of the p-channel type TFT is covered with a fourth resist, and etching the conductive film to form a gate wiring of the p-channel type TFT,
Method for manufacturing an electro-optical device according to the fourth resist, wherein the p-channel type source region and the non-pure element content to the accompanying pressure to Rukoto the drain region and a region of a TFT of the plurality of active layers as a mask. The light shielding film is formed on a base plate,
Forming an insulating film containing silicon on the light shielding film,
Forming a semiconductor film on the insulating film containing silicon;
Forming a first resist having the same size as the light-shielding film on the semiconductor film by backside exposure using the light-shielding film as a mask;
As a mask the first resist, it added not pure element content in a region to be a source region and a drain region of the n-channel type TFT of the semiconductor film,
Forming a protective film on the front Symbol semi conductor film,
Forming a second resist smaller than the first resist on the protective film by backside exposure using the light shielding film as a mask;
In order to form a channel formation region and a low-concentration impurity region of the n-channel TFT , etching is performed so that a part of the protective film remains using the second resist as a mask,
As the second resist and the mask protective film formed by the remaining added non pure element content in a region to be a low concentration impurity region before Symbol n-channel type TFT of the semiconductor film,
Removing the protective film formed by pre-chopped exist,
Patterning the previous SL semi conductor film to form a plurality of active layers,
Forming a gate insulating film in contact with the active layer,
Forming a conductive film which transmits light of a predetermined wavelength on said gate insulating film,
Forming a third resist larger than the second resist on the conductive film by backside exposure using the light shielding film as a mask;
By etching the conductive film using the third resist as a mask to form a gate wiring of the n-channel TFT, and
The region other than the region to be a source region and a drain region of the p-channel type TFT is covered with a fourth resist, and etching the conductive film to form a gate wiring of the p-channel type TFT,
Non pure element content in the source and drain regions and a region of the p-channel type TFT of the plurality of active layers said fourth resist as a mask added pressure,
An insulating film made of a resin material is formed above the gate wiring of the n-channel type TFT and p-channel TFT, and
Forming a pixel electrode made of a transparent conductive film on the insulating film made of the resin material;
Forming a contact hole in the insulating film made of the resin material;
A method for manufacturing an electro-optical device, comprising forming a source wiring and a drain wiring so as to partially overlap with a pixel electrode in a pixel portion . The light shielding film is formed on a base plate,
Forming an insulating film containing silicon on the light shielding film,
Forming a semiconductor film on the insulating film containing silicon;
Forming a first resist having the same size as the light-shielding film on the semiconductor film by backside exposure using the light-shielding film as a mask;
As a mask the first resist, it added not pure element content in a region to be a source region and a drain region of the n-channel type TFT of the semiconductor film,
Forming a protective film on the front Symbol semi conductor film,
Forming a second resist smaller than the first resist on the protective film by backside exposure using the light shielding film as a mask;
In order to form a channel formation region and a low-concentration impurity region of the n-channel TFT , etching is performed so that a part of the protective film remains using the second resist as a mask,
As the second resist and the mask protective film formed by the remaining added non pure element content in a region to be a low concentration impurity region before Symbol n-channel type TFT of the semiconductor film,
Removing the protective film formed by pre-chopped exist,
Patterning the previous SL semi conductor film to form a plurality of active layers,
Forming a gate insulating film in contact with the active layer,
Forming a conductive film which transmits light of a predetermined wavelength on said gate insulating film,
Forming a third resist larger than the second resist on the conductive film by backside exposure using the light shielding film as a mask;
By etching the conductive film using the third resist as a mask to form a gate wiring of the n-channel TFT, and
The region other than the region to be a source region and a drain region of the p-channel type TFT is covered with a fourth resist, and etching the conductive film to form a gate wiring of the p-channel type TFT,
Non pure element content in the source and drain regions and a region of the p-channel type TFT of the plurality of active layers said fourth resist as a mask added pressure,
An insulating film made of a resin material is formed above the gate wiring of the n-channel type TFT and p-channel TFT, and
Forming a contact hole in the insulating film made of the resin material;
Forming a source wiring and the drain wiring,
Method for manufacturing an electro-optical device comprising a Turkey for forming a pixel electrode made of a transparent conductive film so as to partially overlap the drain wiring. The light shielding film is formed on a base plate,
Forming an insulating film containing silicon on the light shielding film,
Forming a semiconductor film on the insulating film containing silicon;
Forming a first resist having the same size as the light-shielding film on the semiconductor film by backside exposure using the light-shielding film as a mask;
As a mask the first resist, it added not pure element content in a region to be a source region and a drain region of the n-channel type TFT of the semiconductor film,
Forming a protective film on the front Symbol semi conductor film,
Forming a second resist smaller than the first resist on the protective film by backside exposure using the light shielding film as a mask;
In order to form a channel formation region and a low-concentration impurity region of the n-channel TFT , etching is performed so that a part of the protective film remains using the second resist as a mask,
As the second resist and the mask protective film formed by the remaining added non pure element content in a region to be a low concentration impurity region before Symbol n-channel type TFT of the semiconductor film,
Removing the protective film formed by pre-chopped exist,
Patterning the previous SL semi conductor film to form a plurality of active layers,
Forming a gate insulating film in contact with the active layer,
Forming a conductive film which transmits light of a predetermined wavelength on said gate insulating film,
Forming a third resist larger than the second resist on the conductive film by backside exposure using the light shielding film as a mask;
By etching the conductive film using the third resist as a mask to form a gate wiring of the n-channel TFT, and
The region other than the region to be a source region and a drain region of the p-channel type TFT is covered with a fourth resist, and etching the conductive film to form a gate wiring of the p-channel type TFT,
Non pure element content in the source and drain regions and a region of the p-channel type TFT of the plurality of active layers said fourth resist as a mask added pressure,
An insulating film made of a resin material is formed above the gate wiring of the n-channel type TFT and p-channel TFT, and
A method for manufacturing an electro-optical device in which a contact hole is formed in an insulating film made of the resin material, and a source wiring and a drain wiring are formed.
Drain wirings formed on image Motobu is formed in a pixel surrounded by the source wiring and the gate wiring, and the feature and Turkey accounting for 70% to 95% of the area in which the pixel is chromatic A method for manufacturing an electro-optical device. In claims 1 to 4, before Kiho Mamorumaku the method of preparing of an electro-optical device which is a laminate film having an insulating film containing silicon, an insulating film made of a resin material. In claims 1 to 4, the wavelength of the plant constant to an electro-optical device which is a wavelength of light used by the pre Kiura surface exposed when forming a gate wiring of the n-channel type TFT Manufacturing method.

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