JP2000124131A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve a semiconductor device in electrolytic effect mobility. SOLUTION: A silicon film 150 is formed on a base film 110 through a PECVD(plasma-enhanced chemical vapor deposition) method. The CVD silicon film 150 is a semiconductor thin film, where an amorphous component and a crystalline component are mixedly present, and the CVD silicon film 150 is of crystalline structure in which an amorphous part is present between crystal grains, and the crystal grain is columnar in structure and has a base, that belongs to the surface of the substrate. The CVD silicon film 150 is annealed by an excimer laser beam and formed into a crystalline silicon film 151. The silicon film 151 is patterned into island shape and forms active layers.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a semiconductor device having a semiconductor circuit including a semiconductor element such as an insulated gate transistor and a method of manufacturing the same, and a method of forming a crystalline semiconductor film on an insulating surface. About technology. The semiconductor device of the present invention includes a thin film transistor (TF
The present invention relates not only to semiconductor elements such as T) and MOS transistors, but also to a semiconductor device having a semiconductor circuit composed of these semiconductor elements. The present invention relates to an active matrix display device and an image sensor, as well as an active matrix display device and an image sensor. An electronic device equipped with is included in the category.

[0002]

2. Description of the Related Art As a monitor for a personal computer or an HDTV, an active matrix type liquid crystal panel using a thin film transistor (TFT) as a switching element has been developed.
By using the FT, a high-definition display can be achieved, and a driver circuit as well as a pixel matrix circuit can be manufactured on the same substrate.

In order to form a polycrystalline silicon film, PEC is used.
There are known a method of polycrystallizing a silicon film deposited by a VD (Plasma Enhanced Chemical Vapor Deposition) method, and a method of forming an amorphous silicon film by crystallizing it. A polycrystalline silicon film requires a deposition temperature of 600 ° C., while an amorphous silicon film has a temperature of 300 ° C.
Since a film can be formed over a large area at a film formation temperature of about 100 ° C., a polycrystalline silicon film formed by the latter method is generally used as a TFT.
Of the active layer.

[0004] As a method of crystallizing an amorphous silicon film, a method of irradiating a laser beam such as an excimer laser or an Ar laser,
A method of heating at 600 to 1000 ° C. in an electric furnace is employed. In particular, a substrate having a low heat resistance such as a Corning 1737 glass substrate is used as the substrate, and the process temperature is 6
Polycrystalline silicon that has undergone a crystallization step at a temperature of 00 ° C. or lower is called low-temperature polysilicon or low-temperature polycrystalline silicon.

[0005]

However, the field-effect mobility of a conventional TFT using a low-temperature polycrystalline silicon film is at most about 100 cm ² / Vs in the case of an N-channel type. This is because, in polycrystalline silicon, the crystal grain boundaries are a major obstacle to the movement of carriers (electrons or holes). At the crystal grain boundaries, the bonds of silicon atoms are broken and many unpaired bonds are present. This is because this dangling bond is at the trap level.

An object of the present invention is to provide a technique for solving the drawbacks of the conventional polycrystalline silicon and improving the electrical characteristics of a semiconductor device using a semiconductor thin film as an active layer.

[0007]

In order to solve the above-mentioned problems, according to the present invention, a semiconductor film in which an amorphous component and a crystalline component are mixed is formed by a PECVD method and annealed. The annealed semiconductor thin film is used for the active layer.

By crystallizing a semiconductor film in which an amorphous component and a crystal component are mixed, dangling bonds at crystal grain boundaries are reduced, so that electrical characteristics of a semiconductor element can be improved.

[0009] Note that the term "semiconductor film" as used herein, silicon (Si) film, a germanium (Ge) film, a silicon - germanium compound _{(Si x Ge 1-x (} 0 <X
<1)).

[0010]

Embodiments of the present invention will be described below in detail with reference to FIG.

A substrate 100 is prepared. For the substrate 100, an insulating substrate such as a glass substrate, a quartz substrate, and a ceramic substrate,
Single crystal silicon substrate, further stainless steel substrate, Cu substrate,
A conductive substrate such as a substrate made of a high melting point metal material such as Ta, W, Mo, Ti, Cr, or an alloy thereof (for example, a nitrogen-based alloy) can be used.

On the surface of the substrate 100, a base film 110 having an insulating surface is formed. When a substrate 100 having an insulating surface, such as a glass or quartz substrate, is used,
Need not be formed, but the base film 100 has a function of preventing impurities from diffusing from the substrate into the semiconductor element, and a function of the substrate 1.
Increase the adhesion of the semiconductor film or metal film formed on
Has the function of preventing peeling.

As the base film 110, an inorganic insulating film such as a silicon oxide film, a silicon nitride film, or a silicon nitride oxide film formed by a CVD method, a sputtering method, or the like can be used.

For example, when a silicon substrate is used, its surface can be oxidized by thermal oxidation to form a base film. In addition, quartz substrates, stainless steel substrates, etc.
When a heat-resistant substrate is used, an amorphous silicon film can be formed and thermally oxidized to form a silicon oxide film.

Further, as the base film 110, a high-melting-point metal film such as tungsten, chromium, or tantalum, or a film having high conductivity such as an aluminum nitride film is formed as a lower layer, and the inorganic insulating film is formed as an upper layer. A membrane may be used. In this case, the heat generated in the semiconductor device is
Since the radiation is radiated from the lower coating film 10, the operation of the semiconductor circuit can be stabilized.

A semiconductor film 150 is formed on the base film 110 by PECVD. Here, the semiconductor film 150 serving as a starting film of the annealing process is referred to as a CVD semiconductor film 150. (Fig. 1 (A))

The CVD semiconductor film 150 is a semiconductor thin film in which an amorphous component and a crystalline component are mixed, and has a crystal structure in which an amorphous portion exists between crystal grains.

Semiconductor film 15 having such a crystal structure
For example, to form a silicon film, a film of SiH ₄ (monosilane) diluted with H ₂ in a source gas is formed.
Or, use Si ₂ H ₆ (disilane) and adjust the gas flow ratio to Si.
H ₄ : H ₂ = 1: 30 to 100 (or Si ₂ H ₆ : H ₂
= 1: 30 to 100), pressure 5 to 270 Pa, RF power density 10 to 250 mW / cm ² , substrate temperature 80 to 350
° C. Note that SiH ₄ or Si ₂ H ₆ is replaced with He.
(Helium).

The CVD silicon film 150 has a crystal structure in which an amorphous component and a crystal component are mixed, and an amorphous component exists between crystal grains. It was also observed that the crystal grains had a columnar structure with the substrate surface as the bottom surface.

The semiconductor film 150 formed by PECVD is annealed (crystallized). By the annealing, the amorphous component in the semiconductor film is crystallized, and the crystal grains grow, so that the semiconductor film 151 having crystallinity is formed.
(FIG. 2 (B))

The semiconductor film 151 crystallized by using a film deposited by the PECVD method of the present invention as a starting film, unlike a conventional polycrystalline semiconductor film, has a smooth bond of atoms at crystal grain boundaries, and has There are few pairs. This is because, in the starting film, the amorphous portion serves as a buffer portion for stress between crystal grains, and there are few dangling bonds at the junction between the crystal component (crystal grain) and the amorphous portion. By annealing such a starting film, a semiconductor film having few dangling bonds at grain boundaries can be obtained.

The annealing treatment of the present invention is broadly classified into thermal annealing in which heat treatment is performed in an electric furnace and light annealing. Optical annealing is effective because the thermal stress applied to the substrate is smaller than that of thermal annealing and can be processed in a short time. In particular, since shorter wavelengths are not absorbed by the glass substrate,
No thermal stress is applied.

The light annealing is further divided into laser annealing and lamp annealing. For laser annealing, a pulse oscillation type laser such as an excimer laser using XeCl, ArF, KrF or the like as an excitation gas, or a continuous oscillation type laser such as an Ar laser or a ruby laser is used.
On the other hand, a lamp light source that emits infrared light or ultraviolet light such as an infrared lamp or a mercury lamp is used for lamp annealing. Further, in the optical annealing, the throughput of irradiating light after shaping the light to be linear, rectangular or square is improved.

The laser annealing conditions (laser beam shape, laser beam wavelength, overlap ratio, irradiation intensity, pulse width, repetition frequency, irradiation time, etc.) are determined in consideration of the thickness of the semiconductor film, the substrate temperature, and the like. Then, the practitioner may appropriately determine. In addition, depending on the conditions of laser crystallization, when the semiconductor film crystallizes after passing through a molten state, or when the semiconductor film crystallizes in a solid state without melting or in an intermediate state between a solid phase and a liquid phase. There is. However, when laser crystallization is performed in the air, a thin oxide film is formed. Therefore, it is sometimes preferable to remove this oxide film after annealing.
In the same chamber without touching the atmosphere, PE
A configuration in which a semiconductor film is formed by a CVD method and annealing is performed may also be employed.

Thermal crystallization in which a catalyst element (nickel) for promoting crystallization is added is described in detail in JP-A-7-130652 and JP-A-9-312260. Metal elements that promote crystallization include Fe, Co,
Ni, Ru, Rh, Pd, Os, Ir, Pt, Cu, A
One or more elements selected from u are used. Also, the diffusion in the amorphous silicon film is G
e and Pb can also be used.

However, when a catalytic element is used, a high concentration of the catalytic element remains in the semiconductor film. Therefore, a step of reducing the concentration of the catalytic element in the semiconductor film after the crystallization treatment, ie, a so-called gettering treatment Is preferably applied.

The annealed semiconductor film 151 is patterned to form active layers 210, 300, and 310 having desired shapes. Using the active layers 210, 300, 310,
A semiconductor element such as a thin film transistor (TFT), a diode, or a memory element can be formed. A circuit (for example, a matrix circuit) is formed using these semiconductor elements, and a semiconductor device such as an active matrix display device or an image sensor can be manufactured.

The field effect mobility of a TFT using the annealed semiconductor film 151 of the present invention as an active layer is typically 100 to 500 cm ² / Vs for an N-channel type, and 20 to 500 cm ² / Vs for a P-channel type. 300 cm ² / Vs, typically can achieve 50~300cm ² / Vs.

[0029]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. However, it goes without saying that the present invention is not limited to the embodiments.

[Embodiment 1] This embodiment will be described with reference to FIGS. This embodiment is an example in which the present invention is applied to an active matrix type liquid crystal panel.

FIG. 7 is a schematic diagram of the active matrix type liquid crystal panel of this embodiment. In a liquid crystal panel, an active matrix substrate and a counter substrate face each other, and liquid crystal is sandwiched between these substrates. The active matrix substrate includes a pixel matrix circuit 101, a scanning line driving circuit 102, and a signal line driving circuit 1 formed on a glass substrate 100.
03.

The scanning line driving circuit 102 and the signal line driving circuit 1
Numeral 03 is connected to the pixel matrix circuit 101 by a scanning line 230 and a signal line 240, respectively. These drive circuits 102 and 103 are mainly constituted by CMOS circuits.

A scanning line 230 is formed for each row of the pixel matrix circuit 101, and a signal line 240 is formed for each column. The pixel TFT 200 is formed near the intersection of the scanning line 230 and the signal line 240. Pixel TFT2
00 is connected to the scanning line 230, and the source is connected to the signal line 240. Further, the pixel electrode 260 and the storage capacitor 270 are connected to the drain.

The opposing substrate 130 has an IT
A transparent conductive film such as an O film is formed. The transparent conductive film is a counter electrode to the pixel electrode 260 of the pixel matrix circuit 101, and the liquid crystal material is driven by an electric field formed between the pixel electrode and the counter electrode. If necessary, an alignment film and a color filter are formed on the counter substrate 130.

The active matrix substrate has FPC1
IC chips 132 and 13 using the surface on which
3 is attached. These IC chips 132,
A circuit 133 is formed by forming circuits such as a video signal processing circuit, a timing pulse generating circuit, a gamma correction circuit, a memory circuit, and an arithmetic circuit on a silicon substrate.

FIG. 6A is a top view of the pixel matrix circuit 101, and is a top view of substantially one pixel. FIG. 6 (B)
FIG. 3 is a top view of a CMOS circuit forming the driving circuits 102 and 103.

FIG. 5 is a sectional view of the active matrix substrate, and is a sectional view of the pixel matrix circuit 101 and the CMOS circuit. FIG. 6 is a sectional view of the pixel matrix circuit 101.
(A) corresponds to the cross section along the chain line XX ′,
A cross-sectional view of the circuit corresponds to a cross section taken along dashed line YY ′ in FIG.

A base film 110 is formed on the entire surface of the substrate 100. Pixel TFT 200 of pixel matrix circuit 101
Has an active layer 210 formed on a base film 110, a gate insulating film 220, and a gate electrode 230E. Scanning line 23
0 and the gate electrode 230E of the pixel TFT 200 are formed integrally.

The active layer 210 has two channel formation regions.
Regions 211 and 212 and channel forming regions 211 and 212
A pair of N sandwiching⁺Mold region (high concentration impurity region) 213 and
214, 214 and 215, a channel forming region 211,
On each side of 212, a pair of N ^-Type low concentration impurity region 2
16 and 217 and 218 and 219 are formed. Low concentration
N-type impurities (phosphorus, arsenic) in impurity regions 216 to 219
Element) is lower than the high-concentration impurity regions 213 to 215.
N⁺The mold regions 213 and 215 are source regions, respectively.
Corresponds to the drain region.

In the CMOS circuit, the active layers 300 and 310
In addition, a gate insulating film 320 and a gate wiring 330 as a first layer wiring are formed. N-channel TFT and P
Channel type TFT gate insulating film 320 and gate wiring 3
30 is formed integrally.

In the active layer 300 of the N-channel TFT,
One channel formation region 301 and a pair of N ⁺ type source / drain regions (high concentration impurity regions) 302 and 303
Are formed, and N ⁻ -type low-concentration impurity regions 304 and 305 are formed between the channel forming region 301 and the source / drain regions 302 and 303 in contact with these regions. The low-concentration impurity regions 304 and 305 have an N-type impurity (phosphorous or arsenic)
Lower than 303.

In the active layer 310 of the P-channel type TFT,
One channel formation region 311 and a pair of P ⁺ type source / drain regions (high concentration impurity regions) 312 and 313
Are formed, and N ⁻ -type low concentration impurity regions 314 and 315 are formed between the channel formation region 311 and the source / drain regions 312 and 313 in contact with these regions. The low-concentration impurity regions 314 and 315 have a P-type impurity (boron) concentration lower than that of the high-concentration impurity regions 312 and 313.

The scanning line 230 and the gate wiring 330 are formed in the same process, and are formed of a material containing Al as a main component.
These surfaces are covered with an alumina film 23 which is an anodic oxide of the wiring.
1, 331.

Over the active layers 210, 300, 310,
An interlayer insulating film 111 is formed. Interlayer insulating film 111
A signal line 240, a drain electrode 241, source lines 341 and 342, and a drain electrode 343 are formed thereon as second layer wiring and electrodes. The drain electrode 343 is connected to the gate wiring 335 of another CMOS circuit.

A first flattening film 112 is formed so as to cover the second layer wiring / electrode. First planarization film 112
A black mask 25 is formed thereon as a third layer wiring.
0, source wirings 351 and 352 are formed. As shown in FIG. 6A, the black mask 340 is integrated with the pixel matrix circuit 101, and its potential is fixed at a predetermined value.

A second planarizing film 113 is formed to cover the third-layer wiring. A pixel electrode 260 is formed on the second flattening film 113 so as to be connected to the drain electrode 231. The second flattening film 113 is used as a dielectric, with the black mask 240 and the electrode facing the pixel electrode 260 as a dielectric.
A storage capacitor 270 is formed.

Hereinafter, a manufacturing process of the active matrix substrate shown in FIGS. 5 to 7 will be described with reference to FIGS. 1 to 4 correspond to the cross-sectional view of FIG. 5, the right side shows the cross-sectional view of the pixel matrix circuit, and the left side shows the CMO.
1 shows a cross-sectional view of an S circuit.

A glass substrate 100 is prepared. here,
A 1737 substrate (strain point 667 ° C.) manufactured by Corning Incorporated is used. PECVD as a base film 110 on the surface of the substrate 100
Silicon oxide film 200nm in thickness using TEOS as raw material
Form a film. After forming the next base film 110, 200 to 70
Heat treatment at 0 ° C. Of course, the upper limit of the heat treatment temperature is equal to or lower than the strain point of the substrate. Here, heating is performed at 640 ° C. for 4 hours.

The CV is formed on the underlayer 110 by PECVD.
A D silicon film 150 is formed. The deposition conditions were SiH ₄
The flow rate was ₂ sccm, the H ₂ flow rate was 200 sccm, the pressure during film formation was kept at 133 Pa, the RF (13.56 MHz) power density was 120 mW / cm ² , and the substrate temperature was 300 ° C.
The formed CVD silicon film 150 is a semiconductor thin film in which an amorphous component and a crystalline component are mixed, and has a crystal structure in which an amorphous portion exists between crystal grains. (Fig. 1 (A))

Annealing the CVD silicon film 150
Laser-annealed silicon film (crystalline silicon film) 151
To form In this embodiment, the CVD silicon film 150 is laser-annealed. A XeCl excimer laser was used as a laser light source. In addition, the laser light is shaped linearly by an optical system, the pulse frequency is 30 Hz, the overlap ratio is 96%, and the laser energy density is 359 mJ / cm.
^{Assume 2} .

By irradiating the laser beam, the amorphous component of the CVD silicon film 150 is crystallized,
Crystal grains grow and a laser-annealed silicon film (crystalline silicon film) 151 having improved crystallinity is formed. In addition, since the surface was exposed to the air to perform laser crystallization, a thin oxide film was formed on the surface of the crystalline silicon film 151, but is not shown in the present embodiment for simplicity. (Figure 1
(B))

The laser-annealed silicon film 151 is patterned to form an active layer 2 having a desired shape (see FIG. 6).
10, 300 and 310 are formed. After the crystallization step, a step of adding an impurity to a region to be a channel formation region may be added in order to control a threshold value. (Figure 1
(C))

A 150-nm-thick silicon oxide film is formed as an insulating film 153 on the entire surface of the substrate 100 covering the active layers 210, 300, and 310 by PECVD. Insulation coating 1
53 is a film for forming a gate insulating film. Insulation coating 15
3 is formed to a film thickness. As the insulating film 153, a single-layer film or a stacked film of silicon oxide, nitride, or nitride oxide may be formed.

On the insulating film 153, a conductive film to be a first-layer wiring is formed. In this embodiment, an aluminum film is formed to a thickness of 400 nm as a conductive film. Using the photoresist masks 154 and 155, the aluminum film is patterned to form aluminum patterns 156 and 157 as wiring prototypes. (Fig. 2 (A))

As the conductive film constituting the wiring, a conductive material or a semiconductor material, for example, aluminum (Al),
Tantalum (Ta), copper (Cu), niobium (Nb), hafnium (Hf), zirconium (Zr), titanium (T
i), a single-layer structure or a laminated structure including a layer mainly containing chromium (Cr), silicon (Si), silicide, or the like can be used. 10 to 500 n as a conductive film
m can be used.

Before forming this conductive film, the laser-annealed silicon film may be further subjected to light annealing or thermal annealing to reduce defects in crystal grains. Of course, annealing can be performed after the silicon film 151 is patterned into an island shape.

The aluminum patterns 156 and 157 are anodized. Oxalic acid (temperature: 30 ° C.) is used as the electrolytic solution, and the ultimate pressure is 8 V and the current is 15 mV / sheet. In this anodic oxidation step, since the photoresists 156 and 157 are present, only the side surfaces of the patterns 156 and 157 are anodized, and alumina films 158 and 159 are formed. The alumina films 158 and 159 have a porous crystal structure, and are easily etched by hydrofluoric acid. (FIG. 2 (B))

After removing the photoresist masks 156 and 157, anodic oxidation is performed again. Using tartaric acid (temperature 10 ° C) as the electrolytic solution, ultimate pressure 80V, current 15mV
/ Sheet. In this anodic oxidation, the alumina films 158, 1
Since the electrolytic solution also permeates into 59, the surfaces of aluminum patterns 156 and 157 are anodized, and alumina films 231 and 331 are formed. Alumina films 231 and 33
Reference numeral 1 denotes a barrier type film having a dense crystal structure, which has etching resistance to hydrofluoric acid. The aluminum patterns 156 and 157 remaining after the two anodic oxidation processes become the scanning lines 230 and the gate lines 330, respectively. (Fig. 2 (C))

Alumina films 158, 159, 221 and 22
3 as a mask, an insulating film 153 made of silicon oxide.
Is patterned to form gate insulating films 220 and 320. (FIG. 3 (A))

In FIG. 3A, an impurity may be first added to the active layer without patterning the silicon oxide film 153, and then the insulating film 153 may be patterned.

An active layer 210 serving as an N-channel type TFT;
300 is covered with a photoresist mask 160, and an impurity imparting P-type conductivity is added to the active layer 310 by a plasma doping method. In this embodiment, boron is added. Since the gate wiring 330 and the gate insulating film 320 function as masks, the intrinsic channel formation region 311, P
⁺ Type source region 312, P ⁺ type drain region 31
3. P ^- type low concentration impurity regions 314 and 315 are formed in a self-aligned manner. The addition of the impurity may be performed by a known method such as an ion implantation method, a laser doping method, or a diffusion method, in addition to a plasma doping method. (FIG. 3 (C))

After removing the photoresist mask 160, a photoresist mask 161 covering the active layer 310 of the P-channel TFT is formed, and an impurity imparting N-type conductivity is added to the active layers 210 and 3 by plasma doping.
Add to 00. In this embodiment, phosphorus is added. Arsenic (As) may be used instead of phosphorus. Gate insulating film 220,
The scanning line 230 functions as a mask, and the channel formation region 211 and the N ⁺ -type high-concentration impurity region 2 are formed in the active layer 210.
12, 213, 214, N ^- low concentration impurity region 215-
219 are formed in a self-aligned manner. At the same time, the gate insulating film 320 and the gate wiring 330 function as a mask,
In the active layer 300, an intrinsic channel formation region 301, N ⁺
Source region 302, N ⁻ type drain region 303,
Low concentration impurity regions 304 and 305 are formed in a self-aligned manner. (FIG. 4 (A))

In this specification, the term “intrinsic” refers to a region which does not contain phosphorus, arsenic, boron (impurities added to source / drain regions) which can change the Fermi level of silicon, or a threshold value control. In this region, phosphorus, arsenic, and boron are intentionally added. The concentration of phosphorus, arsenic, and boron in this region was 1 × by SIMS analysis.
It is in the range of 10 ¹⁵ to 1 × 10 ¹⁷ atoms / cm ³ .

Impurities (boron, phosphorus) added to the active layer
To activate the laser beam, the active layers 210, 300,
Irradiation is performed on the substrate 310, and heat treatment is further performed. Laser irradiation conditions are: pulse frequency 50 Hz, laser energy density 1
79 mJ / cm ² . The heat treatment conditions are a nitrogen atmosphere, temperature: 450 ° C., and time: 2 hours.

Next, as the interlayer insulating film 111, PEC
20 nm thick silicon nitride film by VD method, 900 n thick
m silicon oxide film is formed. A contact hole exposing the source region and the drain region is formed in the interlayer insulating film 111. Titanium (150n) is formed on the interlayer insulating film 111.
m) / aluminum (500 nm) / titanium (100 n
m) is formed by sputtering and patterned to form a signal line 240, a drain electrode 241, a source line 3
41, 342 and a drain electrode 343 are formed. Perform hydrogenation treatment (hydrogen atmosphere, 350 ° C, 2 hours), CM
The OS circuit and the pixel TFT 200 are completed. (FIG. 4
(B))

A first planarizing film 112 is formed on the entire surface of the substrate. As the first planarization film 112, a stacked film of silicon nitride and an acrylic film is formed. First, the thickness 2 by PECVD method
A 0-nm-thick silicon nitride film is formed, and an acrylic film is formed to a thickness of 1 μm by spin coating.

The source wiring 34 is formed on the first planarizing film 112.
1, 342, and a contact hole reaching the drain electrode 343 is formed. Titanium film 300n thick by sputtering method
m, and patterning to form a black mask 250,
Source wirings 351 and 352 are formed.

As the second flattening film 113, an acrylic film is formed to a thickness of 1 μm by spin coating. A contact hole reaching the drain electrode 241 is formed in the planarization films 112 and 113. An ITO film is formed as a conductive film transparent to visible light to a thickness of 100 nm by a sputtering method,
The pixel electrode 260 is formed by patterning. In the portion where the pixel electrode 260 overlaps the black mask 260, the storage capacitor 270 using the second planarizing film 113 as a dielectric and the black mask 250 and the pixel electrode 260 as electrodes.
Is formed. Through the above steps, an active matrix substrate is manufactured. (Fig. 5)

Here, a transmissive liquid crystal panel is manufactured. However, a pixel electrode is formed of a material having a high reflectance (80% or more) with respect to visible light such as aluminum to obtain a reflective liquid crystal panel. Can also. In particular, when a reflective liquid crystal panel is manufactured, when a structure in which an insulating film is stacked over a heat-resistant metal film or a structure in which an insulating film is stacked over aluminum nitride is used as a base film, the metal film below the insulating film serves as a heat dissipation layer. Working and effective. In addition, it is possible for a practitioner to change the above process order as appropriate.

In this embodiment, the pixel TFT 200 has a double gate structure. However, the present invention can be applied to a multi-gate structure such as a single gate structure or a triple gate structure.

In this embodiment, a liquid crystal display device is described as an example, but an active matrix type display device such as an EL (electroluminescence) display device or an EC
It goes without saying that the present invention can be applied to an (electrochromic) display device.

Further, it is easy to form a CMOS image sensor by providing a photoelectric conversion layer instead of a pixel electrode.

[Embodiment 2] This embodiment is an example in which a crystalline semiconductor film is obtained by a method different from that in Embodiment 1, and a step of selectively holding a catalytic element for promoting crystallization on the entire surface of the semiconductor film or selectively. Add. Since the basic configuration is the same as that of the first embodiment, only the differences will be described with reference to FIG.

The CVD silicon film 15 is formed by the PECVD method.
The steps up to the step of forming 0 are the same as in the first embodiment.

In this embodiment, a catalytic element for promoting crystallization of silicon is introduced into the surface of the CVD silicon film 150. Catalyst elements that promote silicon crystallization include N
One or a plurality of elements selected from i, Fe, Co, Pt, Cu, Au, and Ge are used. In this embodiment, Ni is used. Ni has a high diffusion rate in the silicon film among the above catalyst elements, and can obtain the best crystallinity.

The location where the catalyst element is introduced is not particularly limited, but the catalyst element is selectively introduced over the entire surface of the silicon film 150 or by appropriately forming a mask. Further, a step of introducing a catalyst element to the back surface of the amorphous silicon film or to both the front and back surfaces may be adopted.

The method for introducing the catalytic element into the silicon film may be such that the catalytic element and the silicon react to form a compound of the silicon and the catalytic element. The catalytic element is contained on the surface of the amorphous silicon film. And a method that can be added to the silicon film 150.

For example, a sputtering method, a CVD method, a plasma treatment method, an adsorption method, an ion implantation method, or a method of applying a solution containing a catalytic element can be used. The method of applying the solution is simple and has an advantage that the concentration of the catalyst element can be easily adjusted. Various salts can be used as the metal salt, and water, alcohols,
Aldehydes, ethers, other organic solvents, or a mixed solvent of water and an organic solvent can be used. In this embodiment, a solution containing nickel in the range of 1 to 100 ppm (in terms of weight) is applied using an application method. However, it is necessary to appropriately adjust the addition amount in consideration of the thickness of the amorphous silicon film. In the amorphous silicon film thus obtained, the nickel concentration in the film is 1 × 10 ^19-
It becomes 1 × 10 ²¹ atoms / cm ³ .

As described above, the catalyst element is
After being introduced into 51, crystallization is performed by irradiation with laser light to form a crystalline silicon film 153. Further, instead of laser annealing, thermal annealing in which heating is performed at a temperature of 550 ° C. or more may be used. In addition, since the catalytic element impairs the semiconductor characteristics of the active layer, it is preferable to add a step of performing gettering for reducing the catalytic element in the film after annealing.

In the subsequent steps, an active matrix substrate can be manufactured according to the manufacturing steps of the first embodiment.

[Embodiment 3] This embodiment is an example in which a crystalline semiconductor film is obtained by a method different from that of Embodiment 1. In the first embodiment, the silicon film 151 is formed by the PECVD method after the heat treatment of the base film. In the present embodiment, the base film 110 and the CVD silicon film 150 are continuously formed without touching the atmosphere. Show. This embodiment will be described with reference to FIG.

First, a stainless steel substrate is prepared as the substrate 100. A base film 110 made of a silicon nitride film and a CVD silicon film 150 are continuously formed thereon by a PECVD method without touching the atmosphere. By doing so, the interface between the base film 110 and the semiconductor film 150 can be cleaned.

In the subsequent steps, an active matrix substrate can be manufactured according to the manufacturing steps of the first embodiment.

Fourth Embodiment In the first embodiment, a top gate type TFT has been described as an example. However, the configuration of the present invention can be applied to a bottom gate type TFT (typically, an inverted stagger type TFT). In this embodiment, a manufacturing process of an inverted staggered TFT will be described with reference to FIGS.

A laminated film in which a tantalum film having a thickness of 250 nm is sandwiched between tantalum nitride films having a thickness of 50 nm is formed on a glass substrate 500 by a sputtering method, and is patterned to form a gate wiring 501. An anodic oxidation process is performed to form an anodic oxide film 502 on the surface of the gate wiring 501.
Instead of the anodic oxide film 502, a metal oxide may be formed by a sputtering method or the like. A gate insulating film 504 is formed to cover the gate wiring 501. In this embodiment, the PECV
A 100-nm-thick silicon oxynitride film by a D method;
A silicon nitride film having a thickness of 250 nm is continuously formed. Further, the PEC is continuously formed with the gate insulating film 504.
A CVD silicon film 505 in which an amorphous component and a crystalline component are mixed is formed by a VD method. (FIG. 8A)

The CVD silicon film 505 is laser-annealed. A laser beam is shaped into a linear shape by an optical system and irradiated onto the CVD silicon film 505 to form a laser-annealed silicon film (crystalline silicon film) 506 with improved crystallinity. Laser irradiation conditions were as follows: pulse frequency 30 Hz, overlap rate 96%, laser energy density 35
9 mJ / cm ² . CVD by laser annealing
Crystal grains grow at the same time as the amorphous portion of the silicon film 505 is crystallized, and a laser-annealed silicon film 506 with improved crystallinity is formed. (FIG. 8 (B))

A silicon oxide film having a thickness of 120 n is formed on the entire surface of the substrate.
m, and patterned using a photoresist mask 507 to form a spacer 508. (FIG. 8
(C))

After removing the photoresist mask 507, an N-type or P-type impurity is added to the silicon film 506 using the spacer 508 as a doping mask. Here, an N-type region 509 is formed in a self-aligned manner with the silicon film 506 by adding phosphorus. (FIG. 8 (D))

A region to be a channel forming region is covered with a photoresist mask 511. Using the spacer 508 and the photoresist mask 511 as a mask, phosphorus is added by a plasma doping method. The silicon film 506 includes an intrinsic region 521, an N ⁺ -type high-concentration impurity region 522, and N ⁻
A low-concentration impurity region 523 is formed in a self-aligned manner. (FIG. 9A)

The silicon film 506 is divided into islands for each TFT.
Then, an active layer 530 is formed. The active layer 530 is intrinsic
Channel forming region 531, N⁺Mold source region 53
2, N ⁺Type drain region 533, N⁺High concentration impurity of mold
Object regions 534 and 535 are formed. (FIG. 9
(B))

A silicon oxide film having a thickness of 0.9 μm is formed as an interlayer insulating film 540 by PECVD. A contact hole is formed in the interlayer insulating film 540, a titanium film is formed to a thickness of 300 nm by a sputtering method, and is patterned to form a source wiring 542 and a drain wiring 543. (FIG. 9
(C))

In this embodiment, the fabrication process of the inverted stagger type TFT has been described, but the bottom gate type TFT having another structure is described.
It can also be. In addition, the TFT of this embodiment uses the CMO
It is easy to configure the S circuit and the pixel matrix circuit by referring to the manufacturing process of the first embodiment, and the description is omitted.

[Embodiment 5] The present invention can be applied to all conventional IC technologies. That is, the present invention can be applied to all semiconductor circuits currently on the market. For example, RISC processor integrated on one chip, ASIC
The present invention can be applied to a microprocessor such as a processor. Further, the present invention can be applied to a signal processing circuit represented by a liquid crystal driver circuit (D / A converter, gamma correction circuit, signal division circuit, etc.) and a high frequency circuit for portable equipment (cellular phone, PHS, mobile computer).

A semiconductor circuit such as a microprocessor is mounted on various electronic devices and functions as a central circuit. Representative electronic devices include personal computers, portable information terminal devices, and all other home appliances. Further, a computer for controlling a vehicle (an automobile, a train, or the like) is also included. The present invention is applicable to such a semiconductor device.

In manufacturing the semiconductor device shown in this embodiment, any of the structures of Embodiments 1 to 4 may be employed, or the embodiments may be freely combined and used. .

[Embodiment 6] The active matrix display device shown in Embodiment 1 is used as displays of various electronic devices. Such electronic devices include video cameras, digital cameras, projectors,
Examples include a projection TV, a goggle display, a car navigation system, a personal computer, and a portable information terminal (mobile computer, mobile phone, electronic book, and the like). One example of them is shown in FIG.

FIG. 10A shows a mobile phone, and the main body 20 is shown.
01, audio output unit 2002, audio input unit 2003, display device 2004, operation switch 2005, antenna 200
6. The present invention can be applied to the audio output unit 2002, the audio input unit 2003, the display device 2004, and other signal control circuits.

FIG. 10B shows a video camera, which includes a main body 2101, a display device 2102, an audio input unit 2103, an operation switch 2104, a battery 2105, and an image receiving unit 21.
06. The present invention can be applied to the display device 2102, the audio input unit 2103, and other signal control circuits.

FIG. 10C shows a mobile computer (mobile computer), which comprises a main body 2201, a camera section 2202, an image receiving section 2203, operation switches 2204, and a display device 2205. The present invention relates to a display device 220.
5 and other signal control circuits.

FIG. 10D shows a goggle display, which includes a main body 2301, a display device 2302, and an arm 230.
3 The present invention can be applied to the display device 2302 and other signal control circuits.

FIG. 10E shows a rear type projector, in which a main body 2401, a light source 2402, a display device 2403,
Polarizing beam splitter 2404, reflector 240
5, 2406 and a screen 2407. The present invention can be applied to the display device 2403 and other signal control circuits.

FIG. 10F shows a portable book (electronic book), which includes a main body 2501, display devices 2502 and 2503, a storage medium 2504, operation switches 2505, and an antenna 250.
6. The present invention relates to display devices 2502 and 2503.
And other signal control circuits.

As described above, the applicable range of the present invention is extremely wide, and can be applied to electronic devices in various fields.

According to the present invention, it is possible to form a crystalline semiconductor film having few dangling bonds at crystal grain boundaries.
A high-moving semiconductor device can be manufactured. Further, in the present invention, a semiconductor film is formed by the PECVD method.
The production line can be applied, and no extra capital investment is required.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a manufacturing process of an active matrix substrate of Example 1.

FIG. 2 is a cross-sectional view showing a manufacturing process following FIG. 1;

FIG. 3 is a sectional view showing a manufacturing process following FIG. 2;

FIG. 4 is a sectional view showing a manufacturing process following FIG. 3;

FIG. 5 is a cross-sectional view of the active matrix substrate according to the first embodiment.

FIG. 6 is a top view of a pixel matrix circuit and a CMOS circuit according to the first embodiment.

FIG. 7 is a schematic diagram of an active matrix liquid crystal display device according to the first embodiment.

FIG. 8 is a cross-sectional view showing a manufacturing process of the inverted staggered TFT of Example 4.

FIG. 9 is a cross-sectional view showing a manufacturing step following FIG. 8;

FIG. 10 is a schematic view of an electronic device shown in Embodiment 6.

[Explanation of symbols]

REFERENCE SIGNS LIST 100 substrate 110 base film 150 silicon film formed by PECVD method 151 laser-annealed silicon film

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI theme coat ゛ (Reference) H01L 21/205 H01L 29/78 618A 627G F term (Reference) 2H092 JA24 JA26 JA41 JB22 JB31 KA02 KA04 KA05 KA10 MA07 MA09 MA15 MA18 MA24 MA27 MA29 MA30 PA01 PA03 PA06 PA08 RA10 4M104 AA09 BB14 CC01 DD07 DD16 DD17 DD37 FF22 FF30 GG10 5F045 AA08 AB01 AB03 AB05 AB32 AB33 AB34 AC01 AC07 AC17 AD04 AD05 AD06 AD07 AE17 AE19 AE21 AF03 AF07 AF07 DA07 BB07 DA02 DB03 EA15 JA04 5F110 AA01 BB02 BB10 CC02 CC08 DD02 DD07 DD13 EE03 EE34 FF02 FF30 GG02 GG13 GG45 HJ01 HJ18 HJ23 HK03 HK04 HK22 HK33 HL03 HL04 HL12 HL23 NN03 NN04 NN23

Claims (6)

[Claims] 1. A semiconductor circuit comprising a semiconductor element formed on an insulating surface and having an active layer made of a semiconductor thin film, wherein the semiconductor thin film is a film obtained by crystallizing a semiconductor thin film in which an amorphous component and a crystalline component are mixed. A semiconductor device characterized by being formed of: 2. The semiconductor circuit according to claim 1, wherein the semiconductor device is a matrix circuit, and the semiconductor device is an active matrix display device or an image sensor. 3. The semiconductor device according to claim 1, wherein the semiconductor circuit is a microprocessor, a signal processing circuit, or a high-frequency circuit. 4. The semiconductor circuit according to claim 1, wherein the semiconductor device is a matrix circuit, and the semiconductor device is an electronic device including an active matrix display device. 5. The electronic device according to claim 4, wherein the electronic device is a video camera, a digital camera, a projector, a goggle display, a car navigation system, a personal computer, or a portable information terminal. 6. A method of manufacturing a semiconductor device having a semiconductor circuit comprising a semiconductor element formed on an insulating surface, comprising: forming a semiconductor film on which an amorphous component and a crystalline component are mixed by a PECVD method. A method for manufacturing a semiconductor device, comprising: a step of forming; and a step of annealing the semiconductor film.