JP3514891B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

Detailed Description of the Invention

[0001]

The present invention relates to a thin film transistor (T
The present invention relates to a semiconductor circuit having a plurality of FTs) and a manufacturing method thereof. The semiconductor circuit manufactured by the present invention is formed on either an insulating substrate such as glass or a semiconductor substrate such as single crystal silicon. In particular, the present invention relates to a matrix circuit such as a monolithic active matrix circuit (used for a liquid crystal display) which requires a low off current and a small variation in the off current, a high speed operation for driving the same and an on-state operation. The effect is exerted in a semiconductor circuit having a peripheral circuit that requires a small variation in current.

[0002]

2. Description of the Related Art Recently, research has been conducted on an insulating gate type semiconductor device having a thin film active layer (also called an active region) on an insulating substrate. In particular, thin-film insulating gate transistors, so-called thin film transistors (TFTs), have been eagerly studied. These are intended to be used for controlling each pixel in a display device such as a liquid crystal having a matrix structure, which is formed on a transparent insulating substrate, and for a driving circuit, and the semiconductor material to be used. -Amorphous silicon TFTs and crystalline silicon TFTs are distinguished by the crystalline state.

Generally, the electric field mobility of a semiconductor in an amorphous state is small, and therefore TF which requires high speed operation.
Not available for T. Therefore, recently, research and development of crystalline silicon TFTs have been advanced in order to manufacture higher performance circuits. In order to obtain a crystalline silicon film, a method in which amorphous silicon is thermally annealed at a high temperature of around 600 ° C. or higher for a long time, or a method in which intense light such as laser light is irradiated (optical annealing) is known. .

A crystalline semiconductor has a larger electric field mobility than an amorphous semiconductor, and therefore can operate at high speed. With crystalline silicon, not only an NMOS TFT but also a PMOS TFT can be manufactured in the same manner, so that a CMOS circuit can be manufactured. For example, in an active matrix type liquid crystal display device, a circuit having a so-called monolithic structure (monolithic active matrix circuit) in which not only an active matrix portion but also peripheral circuits (drivers and the like) are configured by CMOS crystalline TFTs is used. Are known.

[0005]

FIG. 1 shows a block diagram of a monolithic active matrix circuit used in a liquid crystal display. As the peripheral driver circuit, a source driver (column driver) and a gate driver (row driver) are provided, and many pixel circuits including switching transistors and capacitors are formed in the active matrix circuit (pixel) region to form a matrix. The pixel transistors of the circuit and the peripheral driver circuit are connected by the same number of source lines and gate lines as the number of rows and columns. TFTs used in peripheral circuits, especially peripheral logic circuits such as shift registers, are required to operate at high speed, and therefore a large current (ON current) at the time of selection and a small variation are required.

On the other hand, the TFT used in the pixel circuit is in a non-selected state, that is, when a reverse bias voltage is applied to the gate electrode so that the electric charge accumulated in the capacitor is retained for a long time. Is sufficiently low and variation is required to be small. Specifically, the off current is required to be 1 pA or less, and the variation is required to be within one digit. On the contrary, the ON current does not need to be so large.

Thus, it has been required to simultaneously form TFTs having physically contradictory characteristics on the same substrate. That is, high on-current and low leakage current, and
All TFTs have the characteristic that their variations are small.
Is sought after. However, it is easy to see that this is technically very difficult.

For example, in order to obtain a TFT having a high on-current (that is, a high field effect mobility), a method of crystallizing an amorphous silicon film by an optical annealing method such as a laser annealing method is effective. It is known.
However, it has been empirically revealed that it is impossible to simultaneously achieve high field effect mobility and small variation in off current.

Also known is a method of crystallizing amorphous silicon by a thermal annealing method. This method can reduce the variation in off-current, but high field-effect mobility could not be expected. The present invention is intended to provide an answer to such a difficult task.

[0010]

The present inventor has found that nickel (Ni), platinum (Pt), palladium (Pd), copper (C
u), silver (Ag), iron (Fe), or other element simple substance or a compound thereof is substantially adhered to the surface of the amorphous silicon film in a trace amount, and thereafter, thermal annealing or optical annealing (laser annealing or rapid thermal. It has been found that crystallization can be more easily progressed and crystallinity can be improved by performing annealing (RTA) or the like than conventional thermal annealing or optical annealing. For example, when the thermal annealing method is used, the time required for crystallization can be shortened and the crystallization temperature can be lowered as compared with the conventional method.

This is nickel, platinum, palladium,
It was confirmed that copper, silver and iron function as catalytic elements that promote crystallization of the amorphous silicon film. That is, these catalytic elements form crystalline silicide with amorphous silicon with energy lower than the crystallization energy of amorphous silicon. Next, the catalyst element of the silicide moves to the amorphous silicon ahead of it, and silicon enters the site of the catalyst element of the silicide to form crystalline silicon. That is, the silicon film is crystallized as the catalytic element moves in the amorphous silicon.

It has been confirmed that the crystallization of an amorphous silicon film using this catalytic element has the following two forms. (1) Crystallization that occurs in the region where the catalytic element is introduced, and although it is not possible to specify the crystallization direction in particular, if it is intentionally expressed, a mode in which the crystal growth proceeds in the direction perpendicular to the substrate (2) The catalytic element is As the catalytic element moves from the introduced region to the region where the catalytic element is not introduced,
A mode in which the crystal growth region expands and crystal growth proceeds in a direction parallel to the substrate.

In particular, in the crystal growth mode (2), the form in which columnar crystals grow in the direction parallel to the substrate is confirmed by observation using a TEM (transmission electron microscope). In the following, the crystal growth mode of (1) is referred to as vertical growth, the region crystallized by the mode is referred to as a vertical growth region, the crystal growth mode of (2) is lateral growth, and the region crystallized by the mode is lateral growth. It is called a region.

For example, if a thin film of a catalytic element or a compound having the same is formed on an amorphous silicon film by some means and thermal annealing is performed, the film is initially formed mainly by vertical growth. The crystallized portion of silicon is crystallized, and then the crystallized region is expanded to the peripheral region by lateral growth. Thus, crystallinity can be further enhanced by performing appropriate optical annealing after crystal growth by thermal annealing. The main effect of the photo-annealing in this case is to increase the field effect mobility and decrease the threshold voltage.

A difference is observed in the crystal orientation between the vertical growth and the horizontal growth. Generally, in the vertical growth, the crystal orientation is not so high, and the orientation of the (111) plane is slightly larger than that of the substrate surface. On the other hand, it is observed that the orientation is remarkable in the lateral growth. For example, when the surface of a silicon film is covered with a silicon oxide film or a silicon nitride film and crystallized by a thermal annealing method, the (111) plane is mainly oriented. Specifically, the ratio of the reflection intensity of the (111) plane by the X-ray diffraction method to the sum of the reflection intensities of the (111) plane, the (220) plane, and the (311) plane is 80% or more. This becomes more remarkable by performing the optical annealing after the crystallization by the thermal annealing method as described above, and the ratio to the sum of the reflection intensities of the above surfaces becomes 90% or more.

On the other hand, when the surface of the silicon film is not covered and crystallized by the thermal annealing method, the orientation of the (220) plane also becomes strong and the reflection intensity of the (111) plane and the (220) plane is 9
It becomes 0% or more.

In order to carry out lateral growth, it is necessary to selectively introduce a catalytic element, which usually contains silicon oxide, silicon nitride or silicon oxynitride formed on an amorphous silicon film as a main component. A hole for introduction is formed in a film of a material to be formed by a photolithography method, and a thin film, a cluster or the like of a catalytic element simple substance or its compound is formed by means of a sputtering method, a CVD method, a spin coating method or the like. However, as a result of the study by the present inventor, it has been clarified that with a diameter of 7 μm or less, the probability of defective crystal growth is significantly increased.

This is not advantageous in a highly integrated part such as a peripheral logic circuit. In particular, it cannot be used at all when the design rule is 5 μm or less. On the other hand, in the active matrix circuit, since the distance between the TFTs is sufficient, there is no problem even in the lateral growth.

However, it has become clear that lateral growth need not be adopted for the peripheral logic circuit. As a result of examination by the present inventor, it was revealed that there is no significant difference in field effect mobility between lateral growth and vertical growth. However, by performing optical annealing after thermal annealing, the field effect mobility is doubled. It became clear that it could be improved to a certain degree. A typical field effect mobility is 50 to 80 cm ² / Vs only by thermal annealing, but for example, when laser annealing is added to this, 100 to ²⁰⁰ cm ² / Vs.
It was possible to improve to s. In any case, the value is sufficient for use in the TFT of the peripheral logic circuit.

It is not necessary to change the conditions for the vertical growth region and the lateral growth region during the above-mentioned photo-annealing. Therefore, if the same substrate is used, substantially the same conditions (unintentional It is effective in terms of mass productivity if the optical annealing is carried out under the same conditions (excluding changes in the general conditions). A significant difference between the vertical growth and the lateral growth is recognized in the magnitude and variation of the off current. That is, the off-current is small and the variation is small in the lateral growth, whereas the off-current and the variation are large in the vertical growth.

The present invention utilizes such characteristics of vertical growth and horizontal growth, and is characterized in that the active matrix circuit is crystallized by horizontal growth and the peripheral logic circuit is crystallized by vertical growth to manufacture a TFT. To do. Here, the peripheral logic circuit is a circuit included in a source driver or a gate driver, but a circuit such as an analog switch may be vertically or horizontally grown.

In the present invention, the region crystallized by lateral growth is used for the TFT of the active matrix circuit, but in that case, there are some variations in the arrangement of the TFT. Figure 1 shows one of them.
Shown in. In FIG. 4, 401 is a portion to which a catalytic element is added, that is, a region crystallized by vertical growth. Then, the crystallized region 402 expands laterally around this portion as a center.

In this case, if the catalyst element addition region 401 is rectangular, an elliptical lateral growth region is formed as shown in the figure. In that case, the gate electrode 404 may be made substantially parallel to the region 401 as in the TFT 1, and crystal growth may be performed in the direction from the drain 405 to the source 403 or in the opposite direction. In some cases, like the TFT 2 in the figure, the region 401 and the gate electrode 407 are arranged substantially vertically so that the source 406 and the drain 408 are almost simultaneously crystal-grown. It has been confirmed that there is no great difference in the characteristics of the TFT by either method.

Further, in the active matrix circuit, the catalytic element may be linearly added in parallel with the source line or the gate line. In FIG. 5, gate lines 502, 5
An example in which catalyst element addition regions 501 and 506 are provided in parallel with 07 is shown. FIG. 5A corresponds to the TFT 2 of FIG. 4, and shows a case where the catalytic element is added substantially vertically to the gate electrodes of the TFTs 503 to 505. FIG. 5B shows the TF of FIG.
This corresponds to T1 and is the case where the catalytic element is added substantially parallel to the gate electrodes of the TFTs 508 to 510. The same applies when the catalyst element addition region is provided substantially parallel to the source line.

As mentioned above, the orientation of the (111) plane or the (220) plane is mainly remarkable in the lateral growth region, and the orientation is lowered in the vertical growth region.
Therefore, in the present invention, the crystalline silicon semiconductor (lateral growth region) used for elements such as TFTs, resistors and capacitors of the active matrix circuit is mainly (111).
The crystalline silicon semiconductor used for the peripheral logic circuit has a lower degree of orientation than the crystalline silicon semiconductor used for the active matrix circuit.

Further, if the thermal annealing for crystallization is performed at a temperature equal to or higher than the crystallization temperature of the amorphous silicon thin film, the same crystallinity as when laser annealing is used together can be obtained. Although the crystallization temperature of the amorphous silicon thin film varies depending on the film forming method and the film forming conditions, it is generally 580 ° C. to 620 ° C.
℃. That is, by performing heat treatment at a temperature higher than this temperature (preferably as high as possible), a crystalline silicon film having high crystallinity can be obtained. The upper limit of this heat treatment temperature is preferably about 1100 ° C. Further, when the heat treatment at this high temperature is used, the substrate needs to be a quartz substrate or a glass substrate that can withstand high temperatures.

[0027]

In the present invention, in order to obtain the crystalline silicon semiconductor of the peripheral logic circuit having a high degree of integration, the crystal growth is carried out by the vertical growth utilizing the catalytic element in this portion. As a result,
T with high field-effect mobility, regardless of integration
FT can be obtained. On the other hand, in the active matrix circuit, crystal growth is performed by vertical growth using a catalytic element. As a result, the off current is small, and
It is possible to obtain a TFT with a small variation. In particular, when this heat treatment is performed at a temperature equal to or higher than the crystallization temperature of the amorphous silicon thin film, high crystallinity can be obtained.

[0028]

【Example】

[Embodiment 1] This embodiment relates to a process of simultaneously forming an active matrix circuit (pixel circuit) used in a liquid crystal display device and a peripheral logic circuit on the same glass substrate at the same time. That is, in the crystalline silicon film forming the TFT of the active matrix circuit, a catalytic element that promotes crystallization is added in the vicinity of the region to be crystallized, and heat treatment is performed to parallel the substrate from the region where the element is added. It is obtained by growing crystals in different directions.

Further, in the crystalline silicon film forming the TFT of the peripheral logic circuit, a catalytic element that promotes crystallization is added to a region including a region where the TFT is obtained, and the whole surface of the portion is crystallized by heat treatment. It is obtained by FIG. 2 shows a conceptual cross-sectional view of a manufacturing process of a TFT of a peripheral logic circuit and an active matrix circuit. In the figure, a region (peripheral circuit region) where peripheral logic circuits are formed is shown on the left side, and a region (pixel region) where pixels are formed on the right side.
Indicates. Although the peripheral circuit area and the pixel area are shown as being adjacent to each other in the figure, they are not actually adjacent to each other as shown in the figure.

Further, the TFT in the pixel region is shown in FIG.
As in the case of the TFT 1 in FIG. 4, the catalytic element addition region and the gate electrode are arranged substantially parallel to each other.
As shown in FIG. 2, the catalytic element addition region and the gate electrode may be arranged so as to be substantially vertical. The manufacturing process is shown below.

First, the substrate 201 (Corning 7059)
No. or other borosilicate glass)
A base film 202 of silicon oxide having a thickness of 2000 Å is formed by plasma CVD using EOS (tetra-ethoxy-silane) and oxygen as source gases.

Then, the plasma CVD method or LPCV is used.
According to the D method, a thickness of 300 to 1500Å, for example, 50
An amorphous silicon film 203 containing almost no conductive impurities (phosphorus, boron, etc.) of 0Å is formed. Next, a silicon oxide film 204 having a thickness of 100 to 2000Å, for example, 200Å, is continuously formed by the plasma CVD method. Then, the silicon oxide film 204 is selectively etched,
An exposed region of the amorphous silicon film 203 is formed. In this step, in the peripheral circuit region on the left side of the drawing, the silicon oxide film 204 is entirely removed, and the amorphous silicon film 2 is removed.
The surface of No. 03 was exposed. On the other hand, in the pixel region on the right side of the figure, the silicon oxide film 204 is selectively removed.

Then, an extremely thin oxide film (having a thickness of several tens of liters) is formed on the surface of the amorphous silicon film 203 exposed by the above process. This is to prevent the solution from being repelled on the surface of the amorphous silicon film 203 in the subsequent solution coating step. This oxide film may be formed by thermal oxidation, irradiation with ultraviolet light in an oxygen atmosphere, or treatment with a highly oxidizing solution such as hydrogen peroxide solution.

After that, a nickel acetate solution containing nickel element which is a catalytic element for promoting crystallization is applied, and an extremely thin film of nickel acetate 2 is formed on the surface of the amorphous silicon film 203.
Form 05. This membrane 205 is extremely thin and therefore may not be a perfect membrane. This step was performed using a spin coating method and a spin dry method. The concentration of nickel in the acetic acid solution (in terms of weight) was appropriately 1 to 100 ppm. In this embodiment, it is 10 ppm. (Fig. 2 (A))

After that, 400 to 580 ° C., 55 in this case
A thermal annealing process was performed at 0 ° C. for 4 hours to crystallize the amorphous silicon film 203. As a result, in the peripheral circuit region, almost the entire region grows vertically and changes into the crystalline silicon region 206. In addition, in the pixel region, lateral growth starts from the region to which nickel is added and changes to a crystalline silicon region 208, and the amorphous silicon region 207 remains as it is in the portion far from the region to which nickel is added. (Fig. 2 (B))

Next, the silicon oxide film 204 is removed, and the entire surface is irradiated with KrF excimer laser light (wavelength 248 nm) to improve the crystallinity. Laser light is applied to 2 to 20 shots at one place. Energy density is 250 ~
Although 350 mJ / cm ² was suitable, since the optimum energy density changes depending on the silicon film, the optimum energy density is determined by preconditioning.
The laser irradiation conditions are set similarly on the entire surface of the substrate. Of course, there is a temporal fluctuation (fluctuation) in the energy density during laser irradiation, and in a very microscopic observation, the number of shots irradiated by the laser and the cumulative irradiation energy vary depending on the location. The change was not originally intended. In this embodiment, the fluctuation of the cumulative irradiation energy at an arbitrary 1 cm ² is 10
Laser irradiation was performed under the condition that the ratio was within%.

Other lasers are XeCl excimer laser (wavelength 308 nm), ArF excimer laser (wavelength 193 nm), XeF excimer laser (wavelength 3).
An excimer laser (e.g., 53 nm) or other pulsed laser may be used. Further, this step may be performed by using a rapid thermal annealing (RTA) method.

The nickel concentration in the crystalline silicon film crystallized in this way is determined by secondary ion mass spectrometry (SIMS).
According to the above, typically 1 × 10 ¹⁸ to 1 × 10 ¹⁹ atoms / cm ^{3 in} the vertically grown crystalline region 206 and 1 × 10 ^{17 to} 5 × 10 ¹⁸ atoms / c in the laterally grown crystalline region 208.
It was m ³ .

After the above steps are completed, the silicon film is dry-etched to form island-shaped active layer regions 209, 210, 2
11 is formed. Here, the active layer 210 partially includes the amorphous silicon region 207, and that portion is the TFT.
Since it does not serve as the channel formation region of the above, there is no problem.

In the active layer 211, the region into which nickel is directly introduced (the region not covered with the silicon oxide film 204 at the time of applying nickel acetate) is arranged so as not to overlap the channel forming region of the TFT. This is because it is confirmed that nickel exists in a higher concentration in the region where nickel is directly introduced (vertical growth region) than in the lateral growth region, and in particular, the off-current is low and its variation is small. This is because it is not preferable that a part of the channel formation region of the TFT in the required pixel region includes a vertically grown region. (Fig. 2 (C))

After that, the silicon oxide film 303 functioning as a gate insulating film is deposited to 1500 Å by plasma CVD.
To the thickness of. As a raw material of the plasma CVD method,
Monosilane (SiH ₄ ) and dinitrogen monoxide (N ₂ O) are used. In this example, 10 SCCM of monosilane and 100 SCCM of nitrous oxide were introduced into the reaction chamber, and the substrate temperature was 43.
0 ° C., reaction pressure 0.3 Torr, input power (13.56
MHz) 250 W. These conditions will vary depending on the reactor used. The deposition rate of the silicon oxide film produced under the above conditions is about 1000Å / min, and the mixed solution of hydrofluoric acid 1, acetic acid 50 and ammonium fluoride 50 (20 ° C)
The etching rate is about 1000Å / min.

Subsequently, a low pressure CVD method is used to form a polycrystalline silicon film having a thickness of 2000 to 8000 Å, for example 4000 Å (containing 0.1 to 2% phosphorus for improving conductivity), and etching this. Then the gate electrodes 213 and 21
4, 215 are formed. Next, the active layer 209 is formed by an ion doping method (also referred to as a plasma doping method).
~ 211 using the gate electrodes 213 to 215 as a mask,
Doping with impurities that impart N conductivity type and P conductivity type in a self-aligned manner. Here, the TFT in the pixel region is of a P-channel type. That is, the active layer 21 in the figure
0 and 211 are doped with P-type impurities, and the active layer 209 is doped with N-type impurities. In order to dope the impurities having different conductivity types as described above, known CMOS technology may be used.

In this embodiment, N is used as the doping gas.
Phosphine (PH ₃ ) is used for the p-type doping and diborane (B ₂ H ₆ ) is used for the p-type doping, and the acceleration voltage is 60 to 100 kV in the former case, for example, 90 kV, and 40 to 80 kV in the latter case. , For example, 70 kV. The dose amount is 1 × 10 ¹⁴ to 8 × 10 ¹⁵ atoms / cm ² ,
For example, the N-type impurity is 4 × 10 ¹⁴ atoms / cm ² and the P-type impurity is 1 × 10 ¹⁵ atoms / cm ² . As a result, the N-type impurity region 216 and the P-type impurity regions 217 and 218 are formed.
Can be formed.

Thereafter, thermal annealing is carried out at 400 to 550 ° C. for 1 to 12 hours, typically 450 ° C. for 2 hours to activate the doped impurities. As is common to the present invention, since the active layer contains a catalytic element that promotes crystallization of amorphous silicon, such low temperature and short time thermal annealing is sufficient for activation, The resistance of the region can be reduced to about 1 kΩ / □ or lower. (Fig. 2 (D))

Subsequently, a silicon nitride film having a thickness of 500Å (which has a passivation effect for preventing moisture and mobile ions from entering the TFT from the outside) and a thickness of 4000 are formed.
An insulating film 219 consisting of two layers of a silicon oxide film of Å is formed by a plasma CVD method as a first interlayer insulator, and a contact hole is formed in the insulating film 219, and a metal material such as a multilayer film of titanium and aluminum (main In the example, titanium 5
00 Å and 4000 Å of aluminum) by TF
T electrodes / wirings 220 to 223 are formed. (Fig. 2
(E))

Then, a silicon oxide film 224 having a thickness of 2000Å is further formed by the plasma CVD method, and this is used as a second interlayer insulator. Then, the TF of the pixel area
A contact hole is formed in the impurity region which constitutes the pixel electrode of T, and further an ITO (indium tin oxide) film having a thickness of 800 Å is formed by the sputtering method, and this is etched to form the pixel electrode 225. To do. (Fig. 2
(F) In this way, the pixel region and the peripheral circuit region in the active matrix liquid crystal display device can be simultaneously formed on the same glass substrate.

[Embodiment 2] FIG. 3 shows a cross-sectional view of a manufacturing process of this embodiment. The left side of the figure shows the logic circuit area, and the right side shows the pixel area. In the actual circuit, the logic circuit is an N-channel type T
Although it is a CMOS circuit composed of FT and P-channel type TFTs, the TFT of the logic circuit is shown only for N-channel type for simplification in the figure. N-channel type T for the TFT in the pixel area
FT was used. In this embodiment, the TFT is the source /
A structure having a low-concentration impurity region other than the drain provided adjacent to them was adopted. However, the difference between the N-channel TFT and the P-channel TFT is the type of doping impurity in the source / drain and the low-concentration impurity region. Was the same except that the concentration was different.

First, the substrate (Corning 7059) 301
An underlying film 302 of silicon oxide having a thickness of 2000 Å is formed thereon by a sputtering method. Furthermore, plasma CVD
Depending on the method, the thickness is 300-1000Å, for example 500Å
Intrinsic (I-type) amorphous silicon film 302 is deposited. Further, a silicon oxide film 303 having a thickness of 200Å is formed by a sputtering method, and this is etched in the same manner as in Example 1,
An introduction region of the catalytic element (nickel) is formed, and a thin film of nickel acetate (not shown) is formed by spin coating.

Then, the amorphous silicon film 302 is thermally annealed at 550 ° C. for 4 hours in a nitrogen atmosphere to be crystallized,
A vertical growth region 304 and a horizontal growth region 306 are formed. Region 305 remained amorphous. Then, laser light was irradiated to improve the crystallinity. In this example, a KrF excimer laser was used. Its energy density is 250
˜350 mJ / cm ² was suitable. After laser irradiation, thermal annealing was performed again at 550 ° C. for 1 hour for the purpose of relaxing the distortion caused by laser annealing. (Fig. 3 (A))

The silicon film crystallized in this manner is etched to form island-shaped active layer regions 307 (logic circuit TFTs).
308 (used for pixel TFT) is formed similarly to (used for. In addition, monosilane (SiH ₄ ) and oxygen (O
_The thickness of 1200Å by the thermal CVD method using ₂ ) as a raw material.
A silicon oxide film 309 is deposited. Further, after the film formation, thermal annealing was performed for 1 to 12 hours in an atmosphere of dinitrogen monoxide (N ₂ O) at 400 to 500 ° C.

Subsequently, by the sputtering method,
An aluminum film having a thickness of 2000 to 8000Å, for example 4000Å, is deposited. An extremely thin (50 to 200Å) anodic oxide film (not shown) is formed on this surface in order to improve the adhesion to the photoresist. Then, a photoresist is applied, and photoresist masks 310 and 311 are formed by a known photolithography method,
The aluminum film is etched to form gate electrodes 312 and 3
13 is formed. Aluminum has 0.1 to 0.5 wt% scandium (S) in order to suppress the occurrence of abnormal crystal growth (hillock) in the heating or the subsequent anodic oxidation process.
c) or yttrium (Y) was mixed. Photoresist masks 310 and 311 used as etching masks are left on the gate electrodes 312 and 313 as they are. (Fig. 3 (B))

Further, in the electrolytic solution, the gate electrode 312,
313 is anodized by applying an electric current to form anodic oxides 314 and 315 having a thickness of 1 to 5 μm, for example, 2 μm. As the electrolytic solution, an acidic aqueous solution of 3 to 20% citric acid or oxalic acid, phosphoric acid, chromic acid, sulfuric acid, or the like is used.
A constant current of 0 to 30 V is applied. In this example, pH =
Voltage is 1 in 0.9-1.0 oxalic acid solution (30 ° C)
It is set to 0 V and anodized. The thickness of the anodic oxide is controlled by the anodic oxidation time.

The anodic oxide 31 thus obtained
4,315 were porous. In this anodic oxidation step, the thin anodic oxide film existing between the gate electrodes 312 and 313 and the photoresist masks 310 and 311 can prevent the current from leaking from the photoresist masks 310 and 311. Therefore, the anodic oxidation can be advanced only on the side surfaces of the gate electrodes 312 and 313. (Fig. 3 (C))

Next, photoresist masks 310, 3
11 was peeled off, and the gate electrode 3 was again placed in the electrolytic solution.
A current is applied to 12, 313. This time, pH = 3-10% containing at least one of tartar solution, boric acid, and nitric acid.
An ethylene glycol ammonia solution of 6.9 to 7.1 is used. When the temperature of the solution is lower than room temperature around 10 ° C., a good oxide film can be obtained. Therefore, the gate electrode 312,
Anodic oxides 316 and 317 are formed on the top and side surfaces of 313. The thickness of the anodic oxides 316 and 317 is almost proportional to the applied voltage, and when the applied voltage is 150 V, the anodic oxides 316 and 317 of 2000 Å are formed. Anodic oxide 31
6 and 317 were dense and hard, and were effective in protecting the gate electrodes 312 and 313 in the subsequent heating step. (Fig. 3 (D))

After that, the silicon oxide film 309 is etched by the dry etching method. Since the porous anodic oxides 314 and 315 are not etched in this etching, the underlying silicon oxide film can be left as the gate insulating films 318 and 319 without being etched.
(Fig. 3 (E))

After that, the porous anodic oxides 314 and 315 are etched using a mixed acid of phosphoric acid, acetic acid and nitric acid. In this etching, only the anodic oxides 314 and 315 were etched, and the etching rate was about 600Å / min. The gate insulating films 318 and 319 thereunder remain as they are.

Next, impurities (phosphorus) are implanted into the active layer regions 307 and 308 by ion doping using the gate electrodes 312 and 313 and the gate insulating films 318 and 319 as masks. Phosphine (PH ₃ ) is used as a doping gas, and two-step doping is performed.
The first stage has an acceleration voltage of 80 kV and a dose of 5 × 10 ^12.
Atom / cm ² . In this doping, phosphorus ions pass through the gate insulating films 318 and 319 and are also implanted into the region below. Since the dose amount at this time is small, the low concentration impurity regions 322 and 323 are formed.

The second stage has an acceleration voltage of 30 kV and a dose of 5 × 10 ¹⁴ atoms / cm ² . In this doping, phosphorus ions cannot pass through the gate insulating films 318 and 319, and are mainly implanted into the exposed silicon portion of the active layer. Since the dose amount at this time is large, high-concentration impurity regions (source / drain) 320 and 321 are formed. P-type impurities are similarly doped in the embodiment circuit.

After doping, the impurities are activated by laser annealing. In this embodiment, a KrF excimer laser (wavelength 248 nm) is used as the laser. Laser energy density is 200-300m
J / cm ² is suitable. Instead of laser annealing, activation may be performed by thermal annealing as in the first embodiment. Further, thermal annealing may be performed after laser annealing. (Fig. 3 (F))

Subsequently, a first interlayer insulating film 324 is deposited by a plasma CVD method from a two-layer insulating film including a silicon nitride film having a thickness of 500 Å and a silicon oxide film having a thickness of 4000 Å as an interlayer insulating film, and a contact is made to this. Form a hole. Then, the source electrode / wiring is formed by a multilayer film of titanium and aluminum. Then, a silicon oxide film (second interlayer insulator) 32 having a thickness of 2000 Å is formed by plasma CVD method.
5 is deposited, a contact hole is formed in the pixel TFT,
The pixel electrode 326 of the transparent conductive film is connected here. Through the above steps, a monolithic active matrix circuit was manufactured. (Fig. 3 (G))

[Embodiment 3] This embodiment is an example in which a Corning 1737 glass substrate is used as a substrate in the structure shown in Embodiment 1 or Embodiment 2. Since the Corning 1737 glass substrate has a strain point of 667 ° C., it can withstand heat treatment at a temperature lower than this temperature.

According to experiments, the crystallization temperature of the amorphous silicon film formed by the plasma CVD method is about 590 ° C. This embodiment is characterized in that a crystalline silicon film is obtained by performing heat treatment at a temperature of 650 ° C. for 4 hours.

When the heat treatment is performed at a temperature above the crystallization temperature of such an amorphous silicon film, a crystalline silicon film having high crystallinity can be obtained by the action of the introduced nickel element.

[0064]

In the present invention, since a metal element that promotes crystallization of silicon is used, a silicon film having excellent crystallinity can be obtained. Further, since the silicon film in the peripheral logic circuit region and the silicon film in the active matrix circuit region are caused to have different crystal growth by the action of this catalytic element, a thin film transistor suitable for the peripheral logic circuit,
A thin film transistor suitable for an active matrix circuit can be manufactured over the same substrate by the same process.

[Brief description of drawings]

FIG. 1 shows an outline of a monolithic active matrix circuit.

FIG. 2 shows a manufacturing process of the TFT of Example 1.

FIG. 3 shows a manufacturing process of a TFT of Example 2.

FIG. 4 shows an arrangement example of a TFT and a lateral growth region of an active matrix circuit.

FIG. 5 shows an arrangement example of a TFT and a catalytic element addition region of an active matrix circuit.

[Explanation of symbols]

201 ... Glass substrate 202 ... Base film (silicon oxide film) 203 ... Silicon film 204 ... Silicon oxide film 205 ... Nickel acetate film 206 ... Vertical growth area 207 ... Amorphous region 208 ... Lateral growth area 209 to 211 ... Island-shaped silicon region (active layer) 212 ... Gate insulating film 213-215 ... Gate electrode 216 ... N-type impurity region 217, 218 ... P-type impurity region 219 ... First interlayer insulator 220-223 ... Wiring / electrodes 224 ... Second interlayer insulator 225 ... Pixel electrode

─────────────────────────────────────────────────── ─── Continuation of the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 29/786 H01L 21/336 H01L 21/20 G02F 1/1368

Claims (10)

(57) [Claims] 1. A thin film transistor using a crystalline silicon semiconductor, which is formed on a substrate having an insulating surface.
In a semiconductor device having an active matrix circuit and a peripheral logic circuit for driving the active matrix circuit, a crystalline silicon semiconductor of a thin film transistor of the active matrix circuit is a catalyst that promotes crystallization of amorphous silicon. An element is added and crystallized in the vicinity of a region for crystallizing amorphous silicon, and the crystalline silicon semiconductor of the thin film transistor of the peripheral logic circuit is formed by adding the catalyst element to amorphous silicon. A semiconductor device characterized by being crystallized over the entire surface. 2. The catalyst element is Ni, Pd, Pt, C
The semiconductor device according to claim 1, which is one or more elements selected from u, Ag, and Fe. 3. A thin film transistor using a crystalline silicon semiconductor formed on a substrate having an insulating surface.
In a semiconductor device having an active matrix circuit and a peripheral logic circuit for driving the active matrix circuit, the crystalline silicon semiconductor used in the active matrix circuit has a catalytic element that promotes crystallization of amorphous silicon. The crystalline silicon semiconductor added to the vicinity of the region for crystallizing the amorphous silicon and crystallized, and the crystalline silicon semiconductor used for the peripheral logic circuit is a region where the catalytic element for promoting the crystallization of the amorphous silicon is the region for obtaining the thin film transistor. The crystalline silicon semiconductor used for the active matrix circuit is mainly oriented in the (111) plane or the (220) plane, and the crystalline silicon semiconductor used for the peripheral logic circuit is Characterized by a lower degree of orientation than crystalline silicon semiconductors used in active matrix circuits Semiconductor device. 4. The semiconductor device according to claim 1, wherein the peripheral logic circuit is a shift register. 5. A method for manufacturing a semiconductor device having an active matrix circuit having a thin film transistor using a crystalline silicon semiconductor formed over a substrate having an insulating surface and a peripheral logic circuit for driving the active matrix circuit. in forms a first step of providing an amorphous silicon film on a substrate having an insulating surface, the entire surface and the active matrix circuit of a portion forming at least the peripheral logic circuit on the amorphous silicon film A second step of providing a mask exposing a part of the portion; a third step of selectively adding a catalytic element that promotes crystallization of amorphous silicon by using the mask; and a thermal annealing method. Alternatively, by the optical annealing method, the amorphous
Crystallize the silicon film to form a crystalline silicon film containing amorphous silicon.
A fourth step of forming, the crystalline silicon film is dry-etched, the peripheral Theory
Thin film transistor for processing circuit and active matrix
Channel formation area used for thin film transistor
A fifth step of forming an active layer including a region, and an active layer used in a thin film transistor of the peripheral logic circuit.
The layer is such that the channel forming region does not include the amorphous silicon.
Formed on the thin film transistor of the active matrix circuit.
In the active layer used in the transistor, the catalytic element is selectively
Make sure that the added region and the channel formation region do not overlap
A method for manufacturing a semiconductor device, comprising: 6. The method according to claim 5, wherein in the third step, the element is added in a line substantially parallel to a source line or a gate line in a portion forming an active matrix circuit. A method for manufacturing a semiconductor device. 7. The mask used in the second step is formed by photolithography using a material containing silicon oxide, silicon nitride, or silicon oxynitride as a main component. A method for manufacturing the semiconductor device described. 8. The method of manufacturing a semiconductor device according to claim 5, wherein in the fourth step, the silicon film is crystallized by an optical annealing method after the crystallization step by the thermal annealing method. 9. The manufacturing of a semiconductor device according to claim 5, wherein in the fourth step, the photo-annealing is performed under substantially the same conditions on any part of the substrate. Method. 10. The semiconductor device according to claim 5, wherein the thermal annealing method is performed by heating at a temperature not lower than the crystallization temperature of the amorphous thin film and not higher than 1100 ° C. Of manufacturing.