JPH11330488A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To manufacture thin-film transistors preferred for a peripheral logic circuit and a pixel circuit on the same substrate at the same time by a method, wherein in a crystal orientation of crystalline silicon for use in a plurality of thin-film transistors, the ratio of reflected intensity at (111) face to the sum of reflected strengths at (220) and (311) faces is increased. SOLUTION: An active matrix circuit (a pixel circuit) and a peripheral logic circuit for simultaneous use in a liquid crystal display unit are manufactured on the same glass substrate at the same time. A crystalline silicon film constituting thin-film transistors(TFTs) of the pixel circuit can be attained by a method, wherein a catalyst element promoting crystallization is added near to a region to be crystallized to be heat heated, so that the element is made to crystal-grow from the region to which it is added to a direction parallel to the substrate. Furthermore, a crystalline silicon film constituting the TFTs of the peripheral logic circuit can be attained by a method, in which a catalyst element promoting crystallization is added to a region containing a region obtaining the TFTs to be heated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a thin film transistor (T
FT) and a method for manufacturing the same. A semiconductor circuit manufactured by the present invention is formed on an insulating substrate such as glass or a semiconductor substrate such as single crystal silicon. In particular, the present invention relates to a matrix circuit such as a monolithic active matrix circuit (used for a liquid crystal display or the like) that requires a low off-current and a small variation in the off-current, a high-speed operation for driving the same, and an on-state. This is effective in a semiconductor circuit having a peripheral circuit that requires a small variation in current.

[0002]

2. Description of the Related Art In recent years, studies have been made on an insulating gate type semiconductor device having a thin-film active layer (also called an active region) on an insulating substrate. In particular, a thin film insulated gate transistor, a so-called thin film transistor (TFT), has been enthusiastically studied. These are formed on a transparent insulating substrate and used for controlling each pixel in a display device such as a liquid crystal having a matrix structure, and for a driving circuit. -Amorphous silicon TFTs and crystalline silicon TFTs are distinguished depending on the crystalline state.

Generally, the electric field mobility of a semiconductor in an amorphous state is small, and therefore, a TF which requires high-speed operation is required.
Not available for T. Therefore, recently, research and development of crystalline silicon TFTs have been promoted in order to produce higher performance circuits. In order to obtain a crystalline silicon film, there is known a method of thermally annealing amorphous silicon at a high temperature of about 600 ° C. or more for a long time, or a method of irradiating strong light such as laser light (light annealing). .

[0004] A crystalline semiconductor has a higher electric field mobility than an amorphous semiconductor, and therefore can operate at high speed. With crystalline silicon, not only an NMOS TFT but also a PMOS TFT can be manufactured in a similar manner, so that a CMOS circuit can be manufactured. For example, in an active matrix type liquid crystal display device, a circuit having a so-called monolithic structure (a monolithic active matrix circuit) in which not only an active matrix portion but also peripheral circuits (drivers and the like) are formed of CMOS crystalline TFTs. Are known.

[0005]

FIG. 1 shows a block diagram of a monolithic type active matrix circuit used for a liquid crystal display. As a peripheral driver circuit, a source driver (column driver) and a gate driver (row driver) are provided. In an active matrix circuit (pixel) region, many pixel circuits including switching transistors and capacitors are formed. The pixel transistors and the peripheral driver circuits of the circuit are connected by the same number of source lines and gate lines as the number of rows and columns. High-speed operation is required for a TFT used for a peripheral circuit, particularly a peripheral logic circuit such as a shift register, and therefore, a current (on-current) at the time of selection and a variation thereof are required to be large.

On the other hand, the TFT used in the pixel circuit is not selected so that the electric charge accumulated in the capacitor is retained for a long time, that is, the leakage current (both the off-current and the off-current) when a reverse bias voltage is applied to the gate electrode. ) Is required to be sufficiently low and the variation is small. Specifically, the off current is required to be 1 pA or less, and the variation is required to be within one digit. Conversely, a large ON current is not required.

There has been a demand for simultaneously forming TFTs having physically contradictory characteristics on the same substrate. That is, high on-current and low leakage current, and
All TFTs are characterized by their small variation.
Is required. However, it is easy to see that this is technically very difficult.

For example, in order to obtain a TFT having a high on-current (that is, a high field-effect mobility), it is effective to crystallize an amorphous silicon film by a light annealing method such as a laser annealing method. It is known.
However, experience has shown that it is impossible to simultaneously achieve high field-effect mobility and small variation in off-state current.

[0009] A method of crystallizing amorphous silicon by a thermal annealing method is also known. With this method, it is possible to reduce the variation in off-current, but high field-effect mobility could not be expected. The present invention seeks to provide an answer to such a difficult task.

[0010]

The inventor of the present invention has proposed nickel (Ni), platinum (Pt), palladium (Pd), copper (C
u), silver (Ag), iron (Fe) or other elemental element or its compound in a trace amount is substantially adhered to the amorphous silicon film surface, and then thermally or optically anneal (laser anneal or rapid thermal anneal). Anneal (RTA) or the like) has been found to facilitate crystallization and improve crystallinity more easily than conventional thermal anneal or optical anneal. For example, when the thermal annealing method is used, the time required for crystallization can be shortened and the crystallization temperature can be lowered as compared with the conventional case.

These are nickel, platinum, palladium,
It was confirmed that copper, silver, and iron function as catalytic elements that promote crystallization of the amorphous silicon film. That is, these catalytic elements form crystalline silicide with amorphous silicon at an energy lower than the crystallization energy of amorphous silicon. Next, the catalytic element of the silicide moves to the amorphous silicon ahead, and silicon enters the site of the catalytic element of the silicide, thereby forming crystalline silicon. That is, as the catalyst element moves through the amorphous silicon, the silicon film is crystallized.

In addition, it has been confirmed that the crystallization of the amorphous silicon film using the catalyst element has the following two forms. (1) A crystallization that occurs in a region where a catalyst element is introduced, and although it cannot be specified in particular as a direction of crystallization, a mode in which crystal growth proceeds in a direction perpendicular to the substrate is dared to be expressed. As the catalyst element moves from the introduced region to the region where the catalyst element was not introduced,
A mode in which the crystal growth region expands and crystal growth proceeds in a direction parallel to the substrate.

In particular, in the crystal growth mode (2), a form in which columnar crystals grow in a direction parallel to the substrate has been confirmed by observation using a TEM (transmission electron microscope). In the following, the crystal growth mode of (1) is referred to as vertical growth, the region crystallized by that mode is referred to as the vertical growth region, the crystal growth mode of (2) is laterally grown, and the region crystallized by that mode is horizontal growth. It is referred to as an area.

For example, if a thin film of a catalytic element or a compound containing the same is formed substantially on the amorphous silicon film by some means, and thermal annealing is performed, the film is formed primarily by vertical growth in the initial stage. The portion of silicon that has been crystallized is crystallized, and then the crystallized region expands to the surrounding region by lateral growth. As described above, by performing appropriate optical annealing after crystal growth by thermal annealing, crystallinity can be further improved. The main effect of optical annealing in this case is to increase the field effect mobility and lower the threshold voltage.

There is also a difference in the crystal orientation between vertical growth and horizontal growth. Generally, in the vertical growth, the crystal orientation is not so high, and the orientation of the (111) plane is slightly higher than the substrate plane. In contrast, in lateral growth, remarkable orientation is observed. For example, when the silicon film surface is covered with a silicon oxide film or a silicon nitride film and crystallized by a thermal annealing method, the (111) plane is mainly oriented. Specifically, the ratio of the reflection intensity of the (111) plane to the sum of the reflection intensities of the (111), (220), and (311) planes by X-ray diffraction is 80% or more. This becomes more remarkable by additionally performing optical annealing after crystallization by the thermal annealing method as described above, and the ratio to the sum of the reflection intensities of the above surfaces becomes 90% or more.

On the other hand, when the silicon film is crystallized by the thermal annealing method without covering the surface of the silicon film, the orientation of the (220) plane becomes strong, and the reflection intensity of the (111) plane and the (220) plane becomes 9%.
0% or more.

In order to carry out lateral growth, it is necessary to selectively introduce a catalytic element, which usually comprises silicon oxide, silicon nitride, and silicon oxynitride formed on an amorphous silicon film as main components. A hole for introduction is formed in the film of the material to be formed by photolithography, and a thin film, cluster, or the like of the catalyst element alone or its compound is formed by means such as sputtering, CVD, or spin coating. However, as a result of research conducted by the present inventors, it has been found that when the diameter is 7 μm or less, the probability of occurrence of crystal growth failure is significantly increased.

This is not advantageous in a highly integrated portion such as a peripheral logic circuit. In particular, it cannot be adopted at all in the case of a design rule of 5 μm or less. On the other hand, in the active matrix circuit, since the distance between the TFTs is sufficient, there is no problem even in the case of lateral growth.

However, it has become clear that the lateral growth need not be employed for the peripheral logic circuit. As a result of the study by the present inventors, it was found that there was no significant difference in the field effect mobility between the lateral growth and the vertical growth. However, by performing the optical annealing after the thermal annealing, the field effect mobility was doubled. It became clear that it could be improved to the extent. Typical field effect mobility, but only the thermal annealing is 50~80cm ² / Vs, for example, when this to add laser annealing, 100~200cm ² / V
s. In any case, the value is sufficient for use in the TFT of the peripheral logic circuit.

In the above-described optical annealing, it is not necessary to change the conditions between the vertical growth region and the horizontal growth region. Therefore, as long as they are on the same substrate, substantially the same conditions (unintended) If the optical annealing is performed under the same conditions except for a typical change in conditions, it is effective in terms of mass productivity. A remarkable difference between the vertical growth and the lateral growth is observed in the magnitude and variation of the off-state current. In other words, the off-current and the variation tend to be large in the vertical growth, while the off-current is small and the variation is small in the lateral growth.

The present invention utilizes the characteristics of the vertical growth and the lateral growth to crystallize the active matrix circuit by the lateral growth and the peripheral logic circuit by the vertical growth to produce a TFT. I do. Here, the peripheral logic circuit is a circuit included in the source driver and the gate driver, but a circuit such as an analog switch may be grown vertically or horizontally.

The present invention is characterized in that a region crystallized by lateral growth is used for a TFT of an active matrix circuit. In this case, there are some variations in the arrangement of the TFT. Fig. 4 shows one of them.
Shown in In FIG. 4, reference numeral 401 denotes a portion to which a catalytic element is added, that is, a region crystallized by vertical growth. Then, a region 402 crystallized by lateral growth expands around this portion.

In this case, if the catalyst element addition region 401 is rectangular, an elliptical lateral growth region is formed as shown in the figure. In such a case, the gate electrode 404 may be substantially parallel to the region 401 as in the case of the TFT 1, and the crystal may be grown in the direction from the drain 405 to the source 403 or in the opposite direction. Also, as in the case of the TFT 2 in the figure, the region 401 and the gate electrode 407 may be arranged substantially perpendicularly, and the source 406 and the drain 408 may be crystal-grown almost simultaneously. It has been confirmed that there is no great difference in the characteristics of the TFT by any of the methods.

Further, with respect to the active matrix circuit, a catalytic element may be added linearly substantially in parallel with the source line or the gate line. FIG.
7 shows an example in which catalyst element addition regions 501 and 506 are provided in parallel with the reference numeral 07. FIG. 5A corresponds to the TFT 2 of FIG. 4 and shows a case where a catalytic element is added substantially vertically to the gate electrodes of the TFTs 503 to 505. FIG. 5B shows the TF of FIG.
This corresponds to T1 and is a case where a catalytic element is added substantially parallel to the gate electrodes of the TFTs 508 to 510. The same applies to the case where the catalytic element addition region is provided substantially parallel to the source line.

As described above, the orientation of the (111) plane or the (220) plane is remarkable in the lateral growth region, and these orientations decrease in the vertical growth region.
Therefore, in the present invention, the crystalline silicon semiconductor (lateral growth region) used for elements such as TFTs, resistors and capacitors of the active matrix circuit is mainly composed of (111)
On the other hand, crystalline silicon semiconductors used for peripheral logic circuits are characterized by a lower degree of orientation than crystalline silicon semiconductors used for active matrix circuits.

When the thermal annealing for crystallization is performed at a temperature higher than the crystallization temperature of the amorphous silicon thin film, the same crystallinity as that obtained when laser annealing is used together can be obtained. The crystallization temperature of the amorphous silicon thin film varies depending on the film forming method and the film forming conditions.
° C. That is, by performing the heat treatment at a temperature higher than this temperature (preferably as high as possible is preferable), a crystalline silicon film having high crystallinity can be obtained. Note that the upper limit of the heat treatment temperature is preferably about 1100 ° C. In the case of using this high-temperature heat treatment, the substrate must be a quartz substrate or a glass substrate that can withstand high temperatures.

[0027]

In the present invention, in order to obtain a crystalline silicon semiconductor of a peripheral logic circuit with a high degree of integration, crystal growth is carried out by vertical growth using a catalytic element in the relevant portion. As a result,
Regardless of the degree of integration, T with high field-effect mobility
FT can be obtained. On the other hand, in an active matrix circuit, crystal growth is performed by vertical growth using a catalytic element. As a result, the off current is small, and
A TFT with small variations can be obtained. In particular, when this heat treatment is performed at a temperature higher than the crystallization temperature of the amorphous silicon thin film, high crystallinity can be obtained.

[0028]

[Embodiment 1] This embodiment relates to a process of simultaneously manufacturing an active matrix circuit (pixel circuit) and a peripheral logic circuit used for a liquid crystal display device on the same glass substrate. That is, the crystalline silicon film constituting the TFT of the active matrix circuit is formed by adding a catalytic element that promotes crystallization to the vicinity of a region to be crystallized and performing a heat treatment so that the catalytic element becomes parallel to the substrate from the region to which the element is added. It is obtained by growing crystals in various directions.

The crystalline silicon film constituting the TFT of the peripheral logic circuit is formed by adding a catalytic element for promoting crystallization to a region including a region where the TFT is obtained and subjecting the region to heat treatment to crystallize the entire surface of the portion. It is obtained by having FIG. 2 shows a conceptual cross-sectional view of a manufacturing process of a TFT for a peripheral logic circuit and an active matrix circuit. In the figure, a region for forming a peripheral logic circuit (peripheral circuit region) is shown on the left side, and a region for forming pixels (pixel region) is shown on the right side.
Is shown. Although the peripheral circuit region and the pixel region are shown as being adjacent to each other in the drawing, they are not actually adjacent as shown in the drawing.

The TFT in the pixel area is shown in FIG.
FIG. 4 shows a state in which the catalytic element addition region and the gate electrode are arranged substantially in parallel as in TFT 1 of FIG.
As in 2, the catalyst element addition region and the gate electrode may be arranged so as to be substantially perpendicular. The manufacturing process is described below.

First, the substrate 201 (Corning 7059)
No. or other borosilicate glass).
Using EOS (tetraethoxysilane) and oxygen as source gases, a 2000-nm-thick silicon oxide base film 202 is formed by a plasma CVD method.

Then, the plasma CVD method or the LPCV
According to the D method, the thickness is 300 to 1500 °, for example, 50
An amorphous silicon film 203 to which almost no conductive impurities (such as phosphorus and boron) are added is formed. Next, a silicon oxide film 204 having a thickness of 100 to 2000 〜, for example, 200 連 続 is continuously formed by a plasma CVD method. Then, the silicon oxide film 204 is selectively etched,
An exposed region of the amorphous silicon film 203 is formed. In this step, in the peripheral circuit region on the left side of the figure, the silicon oxide film 204 is completely removed, and the amorphous silicon film 2 is removed.
03 was exposed. On the other hand, in the pixel region on the right side of the figure, the silicon oxide film 204 is selectively removed.

Then, on the surface of the amorphous silicon film 203 exposed by the above process, an extremely thin oxide film (several tens of mm thick) is formed. This is to prevent the solution from being repelled on the surface of the amorphous silicon film 203 in the subsequent solution coating step. This oxide film may be formed by a thermal oxidation method, irradiation of ultraviolet light in an oxygen atmosphere, or treatment with a highly oxidizing solution such as aqueous hydrogen peroxide.

Thereafter, a nickel acetate solution containing a nickel element which is a catalyst element for promoting crystallization is applied, and an extremely thin film 2 of nickel acetate is formed on the surface of the amorphous silicon film 203.
05 is formed. This film 205 is extremely thin, and therefore may not be a complete film. This step was performed using a spin coating method or a spin dry method. An appropriate concentration (in terms of weight) of nickel in the acetic acid solution was 1 to 100 ppm. In this embodiment, the concentration is set to 10 ppm. (Fig. 2 (A))

Thereafter, at 400 to 580 ° C., here 55
A thermal annealing treatment was performed at 0 ° C. for 4 hours to crystallize the amorphous silicon film 203. As a result, in the peripheral circuit region, almost the entire region grows vertically and changes to the crystalline silicon region 206. In the pixel region, the region grows laterally starting from the region to which nickel is added, and changes to a crystalline silicon region 208. In a portion far from the region to which nickel is added, the amorphous silicon region 207 remains. (FIG. 2 (B))

Next, the silicon oxide film 204 is removed, and the entire surface is irradiated with KrF excimer laser light (wavelength: 248 nm) to improve the crystallinity. The laser beam is irradiated for 2 to 20 shots per one place. Energy density is 250 ~
Although 350 mJ / cm ² was appropriate, the optimum energy density varies depending on the silicon film. Therefore, conditions are determined in advance to determine the optimum energy density.
Laser irradiation conditions are set in the same manner on the entire surface of the substrate. Of course, the time variation (fluctuation) of the energy density occurs during laser irradiation, and in very microscopic observation, the number of shots irradiated by the laser and the cumulative irradiation energy fluctuate depending on the location. The change is not intended from the outset. In the present embodiment, the variation of the cumulative irradiation energy in an arbitrary 1 cm ² is 10
% Laser irradiation.

Other lasers include a XeCl excimer laser (wavelength: 308 nm), an ArF excimer laser (wavelength: 193 nm), and a XeF excimer laser (wavelength: 3 nm).
An excimer laser such as 53 nm) or another pulsed laser may be used. This step may be performed using a rapid thermal annealing (RTA) method.

In the crystalline silicon film thus crystallized,
Concentration of nickel by secondary ion mass spectrometry (SIMS)
According to this, typically in the vertically grown crystalline region 206
Is 1 × 10¹⁸~ 1 × 10¹⁹Atom / cm^ThreeGrew laterally
1 × 10 in the crystalline region 208 ¹⁷~ 5 × 10¹⁸Atom / c
m^ThreeMet.

After the above steps are completed, the silicon film is dry-etched to form island-shaped active layer regions 209, 210, 2
11 is formed. Here, the active layer 210 partially includes the amorphous silicon region 207, which is
There is no problem because it does not become the channel formation region of

In the active layer 211, the region into which nickel has been directly introduced (the region not covered with the silicon oxide film 204 when nickel acetate was applied) is arranged so as not to overlap the channel formation region of the TFT. This is because it has been confirmed that nickel is present at a higher concentration in the region where nickel is directly introduced (vertical growth region) than in the lateral growth region, and in particular, the off current is low and its variation is small. This is because it is not preferable for a TFT in a required pixel region to include a vertically grown region in a part of the channel formation region. (Fig. 2 (C))

Thereafter, the silicon oxide film 303 functioning as a gate insulating film is formed by a plasma CVD method at 1500.degree.
Formed to a thickness of As a raw material of the plasma CVD method,
Monosilane (SiH ₄ ) and dinitrogen monoxide (N ₂ O) are used. In the present embodiment, a monosilane of 10 SCCM and a dinitrogen monoxide of 100 SCCM were introduced into the reaction chamber, and the substrate temperature was set at 43 SCCM.
0 ° C., reaction pressure 0.3 Torr, input power (13.56
MHz) 250 W. These conditions vary depending on the reactor used. The deposition rate of the silicon oxide film formed under the above conditions is about 1000 ° / min, and a mixed solution of hydrofluoric acid 1, acetic acid 50, and ammonium fluoride 50 (20 ° C.)
Is about 1000 ° / min.

Subsequently, a polycrystalline silicon film (containing 0.1 to 2% phosphorus for improving conductivity) having a thickness of 2000 to 8000 °, for example 4000 °, is formed by a low pressure CVD method, and this is etched. Gate electrodes 213 and 21
4, 215 are formed. Next, the active layer 209 is formed by an ion doping method (also called a plasma doping method).
To 211 using the gate electrodes 213 to 215 as a mask.
Doping with an impurity imparting N conductivity type and P conductivity type in a self-aligned manner. Here, the TFT in the pixel region is of a P-channel type. That is, the active layer 21 shown in FIG.
0 and 211 are doped with P-type impurities, and the active layer 209 is doped with N-type impurities. In order to dope impurities having different conductivity types as described above, a known CMOS technology may be used.

In this embodiment, the doping gas is N
Phosphine (PH ₃ ) is used for doping of the type, and diborane (B ₂ H ₆ ) is used for doping of the P type. The acceleration voltage is 60 to 100 kV in the former case, for example, 90 kV, and 40 to 80 kV in the latter case. , For example, 70 kV. The dose amount is 1 × 10 ¹⁴ to 8 × 10 ¹⁵ atoms / cm ² ,
For example, the N-type impurity is 4 × 10 ¹⁴ atoms / cm ² and the P-type impurity is 1 × 10 ¹⁵ atoms / cm ² . As a result, the N-type impurity regions 216 and the P-type impurity regions 217 and 218
Can be formed.

Thereafter, thermal annealing is performed at 400 to 550 ° C. for 1 to 12 hours, typically at 450 ° C. for 2 hours to activate the doped impurities. As is common to the present invention, such a low-temperature, short-time thermal annealing is sufficient for activation because the catalytic element for promoting crystallization of amorphous silicon is contained in the active layer. The resistance of the region can be reduced to about 1 kΩ / □ or less. (FIG. 2 (D))

Subsequently, a silicon nitride film having a thickness of 500 ° (which has a passivation effect for preventing moisture and mobile ions from entering the TFT from the outside) and a thickness of 4000
An insulating film 219 consisting of two layers of a silicon oxide film of Å is formed as a first interlayer insulator by a plasma CVD method, and a contact hole is formed in the insulating film 219 to form a metal material, for example, a multilayer film of titanium and aluminum. In the example, titanium 5
00% and 4000 ° aluminum)
T electrodes / wirings 220 to 223 are formed. (Figure 2
(E))

Thereafter, a silicon oxide film 224 having a thickness of 2000 .ANG. Is formed by a plasma CVD method, and this is used as a second interlayer insulator. Then, the TF of the pixel area
A contact hole is formed in the impurity region forming the pixel electrode of T, and an ITO (indium tin oxide) film having a thickness of 800 ° is formed by a sputtering method, and the film is etched to form a pixel electrode 225. I do. (Figure 2
(F)) Thus, the pixel region and the peripheral circuit region in the active matrix liquid crystal display device can be simultaneously formed on the same glass substrate.

[Embodiment 2] FIG. 3 is a sectional view showing a manufacturing process of this embodiment. The left side of the figure shows the logic circuit area, and the right side shows the pixel area. In an actual circuit, the logic circuit is an N-channel T
Although it is a CMOS circuit composed of an FT and a P-channel TFT, for the sake of simplicity, the figure shows only an N-channel TFT for a logic circuit. N-channel type T
FT was used. In this embodiment, as the TFT, the source /
Although a structure in which low-concentration impurity regions other than the drain are provided adjacent to them is adopted, the difference between the N-channel TFT and the P-channel TFT is that And the same except for the concentration.

First, the substrate (Corning 7059) 301
A 2000-nm-thick silicon oxide base film 302 is formed thereon by sputtering. Furthermore, plasma CVD
Depending on the method, a thickness of 300 to 1000 mm, for example, 500 mm
An intrinsic (I-type) amorphous silicon film 302 is deposited. Further, a silicon oxide film 303 having a thickness of 200 ° is formed by a sputtering method, and is etched as in the first embodiment.
A region for introducing a catalytic element (nickel) is formed, and a thin film of nickel acetate (not shown) is formed by a spin coating method.

Then, the amorphous silicon film 302 is thermally annealed at 550 ° C. for 4 hours in a nitrogen atmosphere to be crystallized.
A vertical growth region 304 and a horizontal growth region 306 are formed. Region 305 remained amorphous. Then, the crystallinity was improved by irradiating a laser beam. In this example, a KrF excimer laser was used. Its energy density is 250
３５０350 mJ / cm ² was appropriate. After the laser irradiation, thermal annealing was again performed at 550 ° C. for one hour in order to alleviate distortion due to laser annealing. (FIG. 3 (A))

The silicon film crystallized in this manner is etched to form an island-like active layer region 307 (TFT for logic circuit).
308 (used for a pixel TFT) is formed in the same manner as described above. Furthermore, monosilane (SiH ₄ ) and oxygen (O
₂ ) Thickness of 1200mm by thermal CVD using raw material
Of silicon oxide film 309 is deposited. Furthermore, after film formation, it was subjected to thermal annealing for 1 to 12 hours at dinitrogen monoxide (N ₂ O) atmosphere at 1 atm 400 to 500 ° C..

Subsequently, by a sputtering method,
An aluminum film having a thickness of 2000 to 8000, for example, 4000, is deposited. An extremely thin (50-200 °) anodic oxide film (not shown) is formed on this surface to improve the adhesion to the photoresist. Then, a photoresist is applied, and photoresist masks 310 and 311 are formed by a known photolithography method.
The aluminum film is etched to form the gate electrodes 312, 3
13 is formed. Aluminum has a scandium (S) content of 0.1 to 0.5% by weight in order to suppress the occurrence of abnormal crystal growth (hillock) in the heating and subsequent anodic oxidation steps.
c) or yttrium (Y) was mixed. The photoresist masks 310 and 311 used as etching masks are left on the gate electrodes 312 and 313 as they are. (FIG. 3 (B))

Further, the gate electrode 312,
Anodization is performed by passing an electric current through 313 to form anodic oxides 314 and 315 having a thickness of 1 to 5 μm, for example, 2 μm. The electrolytic solution may be a 3-20% citric acid or an acidic aqueous solution of oxalic acid, phosphoric acid, chromic acid, sulfuric acid, or the like, and may be 1%.
A constant current of 0 to 30 V is applied. In this embodiment, pH =
In a 0.9-1.0 oxalic acid solution (30 ° C.)
Anodize at 0V. The thickness of the anodic oxide is controlled by the anodic oxidation time.

The anodic oxide 31 thus obtained
4, 315 were porous. In this anodic oxidation step, a thin anodic oxide film existing between the gate electrodes 312 and 313 and the photoresist masks 310 and 311 suppresses the leakage of current from the photoresist masks 310 and 311. As a result, anodic oxidation can be advanced only on the side surfaces of the gate electrodes 312 and 313. (FIG. 3 (C))

Next, photoresist masks 310, 3
11 is removed, and the gate electrode 3 is again placed in the electrolytic solution.
Current is applied to 12,12. This time, pH = at least one of 3-10% tartaric acid, boric acid, and nitric acid was included.
Use 6.9-7.1 ethylene glycol ammonia solution. If the temperature of the solution is lower than room temperature of about 10 ° C., a favorable oxide film can be obtained. Therefore, the gate electrode 312,
Anodic oxides 316 and 317 are formed on the top and side surfaces of 313. The thickness of the anodic oxides 316 and 317 is almost proportional to the applied voltage, and the applied voltages are 150 V and 2,000 ° anodic oxides 316 and 317 are formed. Anodic oxide 31
6 and 317 were dense and hard, and were effective in protecting the gate electrodes 312 and 313 in the subsequent heating step. (FIG. 3 (D))

After that, the silicon oxide film 309 is etched by a dry etching method. Since the porous anodic oxides 314 and 315 are not etched in this etching, the underlying silicon oxide film can be left as the gate insulating films 318 and 319 without being etched.
(FIG. 3 (E))

Thereafter, the porous anodic oxides 314 and 315 are etched using a mixed acid of phosphoric acid, acetic acid and nitric acid. In this etching, only the anodic oxides 314 and 315 were etched, and the etching rate was about 600 ° / min. The gate insulating films 318 and 319 thereunder remain as they are.

Next, impurities (phosphorus) are implanted into the active layer regions 307 and 308 by ion doping using the gate electrodes 312 and 313 and the gate insulating films 318 and 319 as masks. Phosphine (PH ₃ ) is used as a doping gas, and two-stage doping is performed.
The first stage has an acceleration voltage of 80 kV and a dose of 5 × 10 ¹²
Atoms / cm ² . In this doping, phosphorus ions pass through the gate insulating films 318 and 319, and are also implanted into a region thereunder. Since the dose at this time is small, low concentration impurity regions 322 and 323 are formed.

In the second stage, the acceleration voltage is 30 kV, and the dose is 5 × 10 ¹⁴ atoms / cm ² . In this doping, phosphorus ions cannot pass through the gate insulating films 318 and 319, and are mainly implanted into portions of the active layer where silicon is exposed. Since the dose at this time is large, high concentration impurity regions (source / drain) 320 and 321 are formed. In the embodiment circuit, the P-type impurity is also doped.

After doping, the impurities are activated by laser annealing. In this embodiment, a KrF excimer laser (wavelength: 248 nm) is used as a laser. Laser energy density 200-300m
J / cm ² is appropriate. Activation by thermal annealing as in the first embodiment may be performed instead of laser annealing. Further, thermal annealing may be performed after laser annealing. (FIG. 3 (F))

Subsequently, a first interlayer insulator 324 is deposited by a plasma CVD method from a two-layer insulating film of a silicon nitride film having a thickness of 500 ° and a silicon oxide film having a thickness of 4000 ° as an interlayer insulator. Form a hole. Then, a source electrode and a wiring are formed by a multilayer film of titanium and aluminum. Subsequently, a silicon oxide film (second interlayer insulator) 32 having a thickness of 2000 .ANG.
5 and a contact hole is formed in the pixel TFT,
The pixel electrode 326 made of a transparent conductive film is connected here. Through the above steps, a monolithic active matrix circuit was manufactured. (Fig. 3 (G))

[Embodiment 3] This embodiment is an example in which a Corning 1737 glass substrate is particularly used as the substrate in the structure shown in Embodiment 1 or 2. Since the Corning 1737 glass substrate has a strain point of 667 ° C., it can withstand heat treatment at a temperature lower than this temperature.

According to the experiment, the crystallization temperature of the amorphous silicon film formed by the plasma CVD method is about 590 ° C. In this embodiment, a crystalline silicon film is obtained by performing a heat treatment at a temperature of 650 ° C. for 4 hours.

When heat treatment is performed at a temperature equal to or higher than the crystallization temperature of such an amorphous silicon film, a crystalline silicon film having high crystallinity can be obtained by the action of the introduced nickel element.

[0064]

According to the present invention, since a metal element which promotes crystallization of silicon is used, a silicon film having excellent crystallinity can be obtained. Further, by the action of the catalytic element, the silicon film in the peripheral logic circuit region and the silicon film in the active matrix circuit region are made to grow different crystals, so that a thin film transistor suitable for the peripheral logic circuit,
A thin film transistor suitable for an active matrix circuit and a thin film transistor can be manufactured over the same substrate by the same process.

[Brief description of the drawings]

FIG. 1 shows an outline of a monolithic type active matrix circuit.

FIG. 2 shows a manufacturing process of the TFT of Example 1.

FIG. 3 shows a manufacturing process of the TFT of Example 2.

FIG. 4 shows an example of arrangement of TFTs and lateral growth regions of an active matrix circuit.

FIG. 5 shows an example of arrangement of TFTs and catalytic element addition regions in an active matrix circuit.

[Explanation of symbols]

 Reference numeral 201: glass substrate 202: base film (silicon oxide film) 203: silicon film 204: silicon oxide film 205: nickel acetate film 206: vertical growth region 207: amorphous Quality region 208 lateral growth region 209 to 211 island silicon region (active layer) 212 gate insulating film 213 to 215 gate electrode 216 N-type impurity region 217, 218 ..P-type impurity region 219 ... first interlayer insulator 220-223 ... wiring / electrode 224 ... second interlayer insulator 225 ... pixel electrode

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁶ Identification code FI H01L 29/78 627G

Claims (11)

[Claims] In a semiconductor device having a plurality of thin film transistors using a semiconductor film formed on an insulating substrate, at least one of the plurality of thin film transistors has a semiconductor film having a (111) plane, (22)
It has orientations in the (0) plane and the (311) plane, and the ratio of the reflection intensity of the (111) plane to the sum of the reflection intensities of the (111) plane, the (220) plane, and the (311) plane is 90% or more. , (1
The semiconductor device, wherein the semiconductor film having an orientation in the (11) plane, the (220) plane, and the (311) plane has crystal growth in a direction parallel to the insulating substrate. 2. A semiconductor device having a plurality of thin film transistors using a semiconductor film formed on an insulating substrate, wherein in one region of the semiconductor film, the (111) plane has a reflection intensity of (111) plane; The ratio of the reflection intensity of the (220) plane to the sum of the reflection intensities of the (311) plane is larger than 80%, and smaller than 80% in other regions of the semiconductor film, and one region of the semiconductor film is parallel to the insulating substrate. A semiconductor device having crystal growth. 3. An active matrix circuit having a plurality of thin film transistors arranged in a first direction on a substrate, wherein the plurality of thin film transistors have a semiconductor layer made of crystalline silicon, and have source, drain, and channel formation regions. Has a gate insulating film in contact with the channel formation region and a gate electrode in contact with the gate insulating film, and the semiconductor layer of the thin film transistor has a crystal grown in a second direction parallel to the substrate. The crystal has an orientation in the (111) plane, the (220) plane and the (311) plane, and the reflection intensity in the (111) plane, the (220) plane and the (311) plane of the reflection intensity in the (111) plane. The active matrix electro-optical device is characterized in that the ratio to the sum of is larger than 90%. 4. An active matrix electro-optical device having a gate line extending on a substrate in a first direction and an active matrix circuit using a plurality of thin film transistors arranged on the substrate in a first direction. The plurality of thin film transistors have a semiconductor layer made of crystalline silicon, and a source, a drain, and a channel formation region are formed in the semiconductor layer, and a gate insulating film in contact with the channel formation region and a gate in contact with the gate insulating film An electrode, the gate electrode being connected to a gate line, the semiconductor layer of the thin film transistor having a crystal grown in a second direction parallel to the substrate, the crystal being a (111) plane, ) And (311) planes, and the (111) plane and the (220) plane and (311) plane An active matrix electro-optical device ratio, wherein greater than 90% with respect to. 5. An active matrix electro-optical device having a gate line extending on a substrate in a first direction and an active matrix circuit using a plurality of thin film transistors arranged on the substrate in a first direction. Wherein the plurality of thin film transistors have a semiconductor layer made of crystalline silicon, a source, a drain, and a channel formation region are formed in the semiconductor layer, and a gate insulating film in contact with the channel formation region and a gate insulating film A gate electrode connected to the thin film transistor, wherein the gate electrode is connected to a gate line, the semiconductor layer of the thin film transistor has a crystal grown in a second direction parallel to the substrate, and the first and second directions are An active matrix electro-optical device which is parallel to each other. 6. An active matrix electro-optical device having a source line extending on a substrate in a first direction and an active matrix circuit including a plurality of thin film transistors arranged on the substrate in a first direction. Wherein the plurality of thin film transistors have a semiconductor layer made of crystalline silicon; a source, a drain, and a channel formation region are formed in the semiconductor layer; and one of the source and the drain is connected to the source line. Being connected, a gate insulating film in contact with the channel formation region and a gate electrode in contact with the gate insulating film, the semiconductor layer of the thin film transistor having a crystal grown in a second direction parallel to the substrate, The crystal has orientations in the (111) plane, the (220) plane, and the (311) plane, and the (111) plane, (2) having a reflection intensity of the (111) plane. 0) is the ratio to the sum of the reflection intensity of the plane and the (311) plane active matrix electro-optical device being greater than 90%. 7. An active matrix electro-optical device having an active matrix circuit including a source line extending on a substrate in a first direction and a plurality of thin film transistors arranged on the substrate in a first direction. Wherein the plurality of thin film transistors have a semiconductor layer made of crystalline silicon; a source, a drain, and a channel formation region are formed in the semiconductor layer; and one of the source and the drain is the source line. Having a gate insulating film in contact with the channel formation region and a gate electrode in contact with the gate insulating film, the semiconductor layer of the thin film transistor having a crystal grown in a second direction parallel to the substrate, An active matrix electro-optical device, wherein the first and second directions are parallel to each other. 8. A semiconductor device comprising: a plurality of thin film transistors formed of a semiconductor film formed on an insulating substrate; and a semiconductor layer formed of crystalline silicon, wherein at least one of the plurality of thin film transistors has a semiconductor film of (111). The ratio of the reflection intensity of the (111) plane to the sum of the reflection intensities of the (111), (220) and (311) planes is 9
The semiconductor device, wherein the semiconductor film is larger than 0% and the semiconductor film grows in a direction parallel to the insulating substrate. 9. A semiconductor device having a thin film transistor using a semiconductor film formed on an insulating substrate, wherein the semiconductor film of the thin film transistor has an orientation on a (111) plane and a reflection intensity of (111) on a (111) plane. ), The ratio to the sum of the reflection intensities of the (220) plane and the (311) plane is greater than 90%. 10. A semiconductor device having a plurality of thin film transistors using a semiconductor film formed on an insulating substrate, wherein at least one semiconductor film of the plurality of thin film transistors has an orientation on a (220) plane; The ratio of the reflection intensity of the plane to the sum of the reflection intensities of the (111) plane, the (220) plane and the (311) plane is greater than 90%, and the semiconductor film grows in a direction parallel to the insulating substrate. A semiconductor device characterized by the above-mentioned. 11. A semiconductor device having a plurality of thin film transistors using a semiconductor film formed on an insulating substrate, wherein at least one semiconductor film of the plurality of thin film transistors has an orientation in a (220) plane; A semiconductor device, wherein the ratio of the reflection intensity of the surface to the sum of the reflection intensity of the (111) plane, the (220) plane, and the (311) plane is greater than 90%.