JPH07193247A - Thin-film transistor and its manufacture - Google Patents

Abstract

PURPOSE:To manufacture a thin-film circuit having a high performance even when the size of the thin-film circuit is larger than the size of an excimer laser beam, in the process wherein the thin-film circuit comprising planar type TFTs is manufactured by an excimer laser annealing method. CONSTITUTION:On a glass substrate 101, an a-Si layer 103 and a second protective oxide film 104 are formed in succession, and in some parts of the second protective oxide film 104, grooves of markers 105 are formed. Then, an alignment is performed by the markers 105, and on the a-Si layer 103, an excimer laser beam 108 is projected. At this time, on the region for a TFT to be formed in future, the excimer laser beam having a uniform intensity is projected, and thereby, a region 110 having a uniform crystalline quality is formed. Subsequently, in this region 110, a data driver and a gate driver are formed respectively.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a thin film transistor, and more particularly to a method of manufacturing a thin film transistor using a crystallized semiconductor layer by excimer laser annealing.

[0002]

2. Description of the Related Art With the progress of the advanced information age, the importance of input / output devices is rapidly increasing, and higher performance of the devices is required. Under such circumstances, an active matrix liquid crystal display element (AM-LCD) using a thin film transistor (TFT) and a contact image sensor (CIS).
Research and development such as is actively carried out. TFTs are roughly classified into polycrystalline silicon thin film transistors (poly-Si).
TFT) and amorphous silicon thin film transistor (a-Si TFT).
The TFT has a mobility of 10 to 1 as compared with the a-Si TFT.
It has a feature that it is about 00 times higher, and high-speed operation of a thin film circuit is possible. Therefore, the peripheral drive circuit connected to the outside of the device can be formed on the same substrate as the device. By integrating this peripheral drive circuit, LS
The cost for I connection can be reduced, the device can be downsized, and the reliability can be improved. As a device using a poly-Si TFT, a drive circuit integrated LCD using a high temperature process similar to that of a silicon LSI has been put into practical use. (Reference S-ID 84 digest (S
ID 84 DIGEST) pp. 316-319) However, in the high temperature process, the maximum process temperature is 1200 ° C.
In order to reach the vicinity, it is necessary to use an expensive quartz substrate, and it is difficult to manufacture a long or large device at low cost. Therefore, using a low-temperature process at 600 ° C. or lower, which enables the use of an inexpensive glass substrate, poly-Si
A technology for improving the performance of TFT is required. As a method therefor, excimer laser annealing (ELA)
A law has been proposed and has been actively studied in recent years. This method is a method of irradiating a semiconductor layer with an extremely long and short pulse excimer laser beam to melt and crystallize only the semiconductor layer, and a high-quality semiconductor layer can be formed without damaging the substrate. 100 cm ² / V · by using ELA method
poly-Si TF having field effect mobility of s or more
T can be manufactured, and high-speed operation of a thin film circuit can be realized.

The intensity profile of an excimer laser beam generally used at present is shown in FIGS. 5 (a) and 5 (b). FIG. 2B is a conceptual plan view of the intensity profile, and FIG. 1A shows the position dependence of the beam intensity at AA ′ in FIG. As shown in FIG. 6B, a region 501 having a non-uniform beam intensity exists around the region 502 having a uniform beam intensity. At present, the beam size is several mm square. Therefore, in order to form a thin film circuit having a size larger than the beam by the ELA method, it is necessary to irradiate the region where the active layer is formed with the beam in a superimposed manner.

As an example, an example in which the conventional ELA method is applied to the production of a drive circuit for a contact image sensor is shown in FIG.
Shown in. In the excimer laser annealing of the active layer, the first shot 505, the second shot 506, while overlapping the beam from the end of the region 504 where the drive circuit is formed,
Irradiation is sequentially performed with the third shot 507 to crystallize the entire active layer. At this time, the region 508 where the beam periphery is irradiated
In this case, since the beam intensity changes abruptly, the crystallinity in this region is significantly different from the crystallinity in the region where the beam intensity is uniform, and the variation due to the position is large. Since the TFT characteristics greatly depend on the crystallinity of the active layer, the TFT characteristics also greatly differ between the beam peripheral portion and the central portion. Therefore, in the method of overlapping the beams, there are problems that the yield is reduced and it is difficult to improve the performance of the thin film circuit because the TFT characteristics are non-uniform. Therefore, in order to solve these problems, a block irradiation method has been proposed.
(Reference S-ID 93 digest (SID 93
DIGEST) pp. 356-358) This method is shown in FIG.
As shown in (d), the driving circuit is divided into a plurality of blocks each having a smaller beam intensity than the uniform region, and the laser annealing of the active layer of the TFT formed in each block is performed only in the region having the uniform beam intensity. This is the method used. According to this method, since the TFT is not formed in the region irradiated with the beam having a non-uniform intensity in the peripheral portion of the beam, the crystallinity of the active layer is uniform both inside and between blocks. In this way, since the TFT characteristics can be made uniform between blocks within a block, a drive circuit capable of high speed operation can be manufactured with a high yield rate. A manufacturing process of a forward stagger type n-ch TFT using this method will be described with reference to FIG. First, as shown in FIG. 6A, the glass substrate 6
01 on top of SiO by low pressure vapor deposition (LPCVD) method.
_Two films are deposited to form a protective film 602. Next, an n ⁺ poly-Si film containing phosphorus at a high concentration is deposited and then patterned to form source / drain regions 603. At this time, the marker 604 for alignment at the time of excimer laser annealing is simultaneously formed by patterning. Further, an a-Si film is deposited by the LPCVD method to form a semiconductor layer 605. Next, as shown in FIG. 6B, alignment is performed using a marker 604, and the semiconductor layer 605 is irradiated with an excimer laser beam. At this time, the beam 60 having a non-uniform intensity is formed around the beam 606 having a uniform intensity.
There are seven. Therefore, in the semiconductor layer 605, a region 608 irradiated with a beam having uniform intensity and a region 609 around the region 609 irradiated with a beam having nonuniform intensity are formed. Here, by performing the alignment, the source / drain region 60 is formed in the region irradiated with the beam having a uniform intensity.
Irradiate so that 3 is included. Next, as shown in FIG. 6C, patterning is performed to obtain a beam 60 with uniform intensity.
An active layer 610 is formed in Further, a SiO ₂ film is deposited by the LPCVD method to form a gate insulating film 611, and then an n ⁺ poly-Si film containing phosphorus at a high concentration is deposited by the LPCVD method, followed by patterning to form a gate electrode 612. To form. Further, a SiNx film is deposited by a plasma CVD method to form an interlayer insulating film 613.
After the formation, the interlayer insulating film 61 is patterned.
3, a part of the three layers of the gate insulating film 611 and the active layer 610 is etched to form a contact hole. Further, after depositing aluminum by a sputtering method, patterning is performed to form a gate electrode 612. In this way, the crystallinity of the active layer becomes uniform among the TFTs, so that T
The FT characteristic becomes uniform, and a high-performance thin film circuit can be manufactured.

On the other hand, in order to improve the performance of the device, it is important to reduce the leak current. poly-Si T
FT is a MOSFE formed in bulk silicon by an electric field emission current through a level near the midgap.
A leak current larger than that of T flows. (Reference: IE Trans. On Electron Devices)
on Devices), Vol. ED-32 No.
9 pp. 1878) In order to reduce this leak current, it is effective to relax the electric field at the drain end, and up to now LDD (Lightly Doped) has been proposed.
Drain) structure (Literature IEICE General Conference, 2
-20, pp. 271 1978) and an offset structure (literature IEEE Electron Device Letters).
Letters), Vol. EDL-8 No. 9 p
p. 434, 1987) have been proposed. Furthermore, E
It is considered that the cap annealing method in which the insulating film used as the protective film in the LA method is used as it is for the gate insulating film is advantageous for improving the performance of the TFT. (Japanese Patent Laid-Open No. 03-0339
This is because the interface between the semiconductor layer and the insulating film is heated to near the melting point of the semiconductor layer during laser annealing, so that atoms forming the interface change into a stable structure and the interface level is reduced. . Here, an example of a manufacturing process of an offset structure n-ch TFT using the cap annealing method will be described. First, as shown in FIG. 7A, SiO _{2 is} deposited on the glass substrate 701 by LPCVD.
A film is deposited to form a first protective film 702. Next, LPC
The a-Si film is deposited by the VD method to form the semiconductor layer 703, and further, the SiO ₂ film is deposited by the LPCVD method to deposit the second protective film 704, and then the excimer laser beam 705 is irradiated to irradiate the semiconductor. Crystallize layer 703. Next, as shown in FIG. 3B, the crystallized semiconductor layer 70 is formed.
3 and the second protective film 704 are patterned into an island structure using the same mask to form an active layer 706 and a first gate insulating film 707. Further, after depositing a SiO ₂ film by LPCVD to form a second gate insulating film 708, LPCV is performed.
N ⁺ poly-S containing a high concentration of phosphorus by the D method
After depositing the i film, patterning is performed to form the gate electrode 7
09 is formed. Next, as shown in FIG. 3C, patterning is performed using the gate electrode as a mask to etch the first gate insulating film 707 and the second gate insulating film 708, and then phosphorus ions 710 are implanted by an ion implantation method, A source / drain region 711 is formed on a part of the active layer 706.
To form. Next, as shown in FIG. 9D, the gate electrode 709 is patterned to form an offset region 712, and then a SiO ₂ film is deposited by LPCVD to form an interlayer insulating film 713. Further, after patterning is performed to form contact holes, aluminum is deposited by a sputtering method and patterning is performed to form source / drain electrodes 714. By thus forming the offset structure, the electric field at the drain end is relaxed, and the leak current can be reduced.

[0006]

As described above, when the source / drain regions are formed under the semiconductor layer which becomes the active layer like the staggered TFT, when the source / drain regions are patterned. Since the marker can be formed at the same time in the laser annealing, and the block irradiation method can be adopted, the region where the thin film circuit is formed in the semiconductor layer can be laser annealed by using a beam with uniform intensity. It can be carried out. For this reason, the TFT characteristics of the thin film circuit are uniform, and a high performance thin film circuit can be manufactured. On the other hand, planar type TF
In the case of T, a pattern to be a marker is not formed below the semiconductor layer that will be the active layer. Therefore, the block irradiation method as described above cannot be used, and the irradiation is performed by scanning while excimer laser beams are partially overlapped. In this case, as described above, since the beam intensity sharply changes in the beam peripheral portion, the crystallinity largely changes, and the TF formed in the irradiated region of the beam peripheral portion.
The characteristics of T were non-uniform. For this reason, it has been difficult for the planar type to improve the performance of a thin film circuit larger than the beam size.

Further, in the conventional offset structure, it is necessary to reduce the shape of the gate electrode after the ion implantation step, which causes a problem that the number of steps is increased.

It is an object of the present invention to provide a thin film transistor capable of producing a thin film circuit having a size larger than the beam size with high performance, and a method for producing the thin film transistor even in a planar type TFT.

[0009]

In order to solve the above-mentioned problems, the first invention is to provide a source / drain region containing an impurity at a high concentration formed on an insulating substrate, an active layer, and A gate insulating film, a gate electrode, an interlayer insulating film,
In a thin film transistor including source / drain electrodes, an active layer made of a semiconductor having an island structure, a first gate insulating film formed so as to cover a part of the active layer, the active layer and the first gate insulating film. A second gate insulating film formed so as to cover the film, a gate electrode formed so as to cover a part of the first gate insulating film, and only the second gate insulating film of the active layer is formed. The source / drain regions containing a high concentration of impurities formed in the formed regions, and the impurities formed in the regions of the active layer in which the first gate insulating film and the second gate insulating film are formed. A low impurity concentration region whose concentration is lower than that of the source / drain region, an interlayer insulating film formed to cover the second gate insulating film and the gate electrode, the interlayer insulating film and the A contact hole formed in a part of the second gate insulating film through the contact hole,
A thin film transistor including a source / drain electrode electrically connected to the source / drain region is provided.

In addition, a source formed on the insulating substrate
In a method of manufacturing a thin film transistor including a drain region, an active layer, a gate insulating film, a gate electrode, an interlayer insulating film, and a source / drain electrode, a semiconductor layer such as amorphous silicon or polycrystalline silicon is formed on an insulating substrate. Forming an active layer, a step of forming a protective film made of a transparent insulating film that does not absorb a laser beam on the active layer, and a step of removing a part of the protective film by etching or the like to form a groove. And a step of performing positioning by using the groove as a marker and irradiating a laser to crystallize the active layer, thereby providing a method of manufacturing a thin film transistor.

Further, a step of forming an amorphous semiconductor film to be an active layer on the insulating substrate, and a step of forming a second protective film to be a first gate insulating film on the semiconductor film,
Patterning the second protective film to form a marker and simultaneously forming a first gate insulating film; and irradiating a laser with the marker as a mark to crystallize the semiconductor film,
A step of forming the active layer leaving a region of the laser-irradiated region irradiated with a beam having a uniform intensity; and a second gate insulation so as to cover the active layer and the first gate insulating film. A step of forming a film, a step of forming a gate electrode so as to cover a part of the first gate insulating film through the second gate insulating film, and ion implantation of impurities using the gate electrode as a mask, Forming a source / drain region containing a high concentration of impurities in a region where the first gate insulating film is not formed; and forming an interlayer insulating film so as to cover the second gate insulating film and the gate electrode. A step of forming a contact hole in a part of the interlayer insulating film and the second gate insulating film on the source / drain region, and the source / drain region through the contact hole. To provide a manufacturing method of a thin film transistor comprising the step of forming the in-region and electrically connected to the source and drain electrodes.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the invention according to claim 2 will be described with reference to the drawings. As one embodiment of the present invention, an example in which the present invention is applied to a liquid crystal display device integrated with a drive circuit will be shown.
First, as shown in FIG. 1A, a SiO ₂ film is formed on a cleaned glass substrate 101 by a LPCVD method at a substrate temperature of 400 ° C. using a silane gas and an oxygen gas.
Angular deposition was performed to form the first protective film 102. Next, the a-Si film is processed to 1000 by LPCVD.
Then, the semiconductor layer 103 was deposited to 1000 angstrom. Furthermore, by the LPCVD method, S
A second protective film 104 was formed by depositing an iO ₂ film. Further, patterning was performed by a photolithography method, and a part of the second protective film was dry-etched to form a groove to form an alignment marker 105. Next, FIG.
As shown in (b), alignment was performed using the marker 105, and the semiconductor layer 103 was irradiated with an excimer laser beam to crystallize a region including a region where a TFT is to be formed in the future. At this time, in the excimer laser beam, a beam 107 having a non-uniform intensity exists around the beam 106 having a uniform intensity, and both beams are irradiated to different regions of the semiconductor layer 103. Therefore, in the semiconductor layer 103, a region 109 irradiated with a beam having a non-uniform intensity is formed around the region 108 irradiated with a beam having a uniform intensity. Next, FIG.
As shown in (c), after peeling off the second protective film 104,
A region 108 irradiated with a beam having a uniform intensity was patterned into an island structure by photolithography to form an active layer 110. Further, by the LPCVD method, SiO
After depositing ₂ films of 1000 angstrom, LPCV
N containing ³ or more ^- phosphorus at a substrate temperature of 600 ℃ 10 ^{2 1} cm by using silane gas and phosphine gas by Method D
After depositing a ⁺ poly-Si film at 2000 angstrom, patterning was performed to form a gate insulating film 111 and a gate electrode 112. Further, phosphorus ions 113 are accelerated by an ion implantation method at an acceleration voltage of 40 KeV and an implantation amount of 5 × 1.
0 ^{1 5} cm ^- was injected at ^2, the source-drain regions 114
Was formed. Next, as shown in FIG. 1D, 600 ° C.
After anneal to activate the source / drain regions, a SiNx film is deposited to 2000 angstrom by plasma CVD method to form an interlayer insulating film 115,
A contact hole was formed. Further, 3000 angstroms of aluminum was deposited by the sputtering method and patterned by the photolithography method to form the source / drain electrodes 116. Furthermore, poly-
Annealing was performed in a hydrogen plasma atmosphere in order to terminate dangling bonds existing at grain boundaries in the Si film.

FIG. 2 shows a plan view of the LCD integrated with the driving circuit, which is manufactured through the above-mentioned steps. As shown in the figure,
The drive circuit including the data driver 118 and the gate driver 119 connected to the active matrix array 117 is formed by being divided into several blocks. As described above, these drive circuits are configured by the planar type TFT having the active layer crystallized by using the excimer laser beam having uniform intensity. As described above, not only the uniformity of the TFT characteristics in each block is improved, but also the TFT characteristics are improved between the blocks, and the T, such as mobility, threshold value, ON current, OFF current, etc. of the entire drive circuit is improved.
The variation in FT characteristics could be suppressed to ± 3% or less.
In this way, by improving the uniformity of the TFT characteristics, it was possible to realize high performance of the thin film circuit, and it was possible to operate the drive circuit at a drive voltage of 10 V and a maximum clock frequency of 5 MHz.

Next, an embodiment of the invention described in claims 1 and 3 will be described with reference to the drawings. First, as shown in FIG. 3 (a), LP on the glass substrate 301.
A SiO ₂ film is deposited to a thickness of 2000 Å by the CVD method to form a first protective film 302, and LPCVD is performed.
Then, the semiconductor layer 303 was formed by depositing an a-Si film of 1000 angstrom by the method. Further, a SiO ₂ film is deposited to a thickness of 1000 Å by the LPCVD method to form a second protective film 304, and then patterning is performed.
The gate insulating film 306 and the marker 305 were formed. Next, as shown in FIG. 3B, an excimer laser beam was irradiated to crystallize the semiconductor layer 303. At this time, the beam 30 having a non-uniform intensity is formed around the beam 307 having a uniform intensity.
8 exist and both are irradiated to the semiconductor layer 303. Therefore, in the semiconductor layer 303, a region 310 irradiated with a beam having a non-uniform intensity is formed around the region 309 irradiated with a beam having a uniform intensity. Next, as shown in FIG. 3C, a region 309 irradiated with a beam having a uniform intensity was patterned to form an active layer 311 having an island structure. Next, as shown in FIG. 4A, a SiO ₂ film was deposited to a thickness of 500 Å by LPCVD to form a second gate insulating film 313. Next, by the LPCVD method, phosphorus is added to 10 by using silane gas and phosphine gas.
^{2 1} cm ^{− 3} or more containing n ⁺ poly-Si film
After depositing 000 Å, patterning was performed to form a gate electrode 313. At this time, the gate electrode 313 is patterned so as to be smaller than the first gate insulating film 306. Next, the gate electrode 313 as a mask, phosphorus ions 314 acceleration voltage 60 KeV, a dose of 6 × 10 ^{1 5} cm by ion implantation ^- was injected at ^2. At this time, phosphorus is added to the active layer 311 having only the second gate insulating film having a thickness of 500 Å.
0 ^{2 1} cm ^{- 3} source and drain regions 31 containing more than
5 is formed. On the other hand, the phosphorus concentration is 10 in a region where the gate electrode 313 is not formed and the first gate insulating film 306 having a film thickness of 1500 angstrom and the second gate insulating film 312 having a film thickness of 500 angstrom are formed.
An offset region 316 having a size of ¹⁹ cm ⁻³ or less is formed. Next, as shown in FIG. 4B, a SiNx film is deposited to 2000 angstroms by a plasma CVD method to form an interlayer insulating film 317, a contact hole is formed, and aluminum is further deposited to 3000 angstroms by a sputtering method. Patterning is performed to form source / drain electrodes 318.

According to this method, when forming the offset region, the step of patterning the gate electrode after ion implantation can be omitted. Therefore, the offset structure TF
It was possible to fabricate T in a smaller number of steps than in the past.
Furthermore, since the protective insulating film used during the excimer laser annealing is used as it is as the gate insulating film, a good interface with a low interface state density is formed, a low leak current, and a high threshold voltage. It was possible to fabricate different TFTs. Although the offset structure has been described in this embodiment, the impurity concentration of the low concentration impurity region can be changed by changing the gate insulating film thickness and the ion implantation acceleration voltage, and the LDD structure TFT is manufactured using the same mask. It is also possible.

[0016]

As described above, according to the second aspect of the present invention, even when a marker is not formed under the semiconductor layer as in the planar type TFT, the excimer laser is provided at a desired position of the semiconductor layer. Beam irradiation was possible, and the block irradiation method could be applied to planar TFTs. Therefore, the characteristic variation of the TFT formed on the glass substrate of 50 cm × 50 cm can be suppressed within ± 3%, and the drive circuit can be operated at the drive voltage of 10 V and the maximum clock frequency of 5 MHz.

Further, since the excimer laser annealing is performed by providing the protective oxide film on the semiconductor layer, the mixing of impurities into the semiconductor layer during the excimer laser annealing is 1 / 100th of the case where the protective oxide film is not formed. It was possible to suppress it to the following, and a high quality poly-Si film was obtained. Furthermore, since the protective film is formed, the surface irregularities that occur during the melting / crystallization process during excimer laser annealing can be suppressed to ± 5 nm or less, and the field effect mobility of 200 can be achieved.
A poly-Si TFT having cm ² / V · s could be manufactured.

Further, the interface between the active layer and the gate insulating film is heated to 1400 ° C. or higher by irradiating the excimer laser beam through the gate insulating film used as the protective film to melt and crystallize the active layer. Therefore, the interface state density is 1/10 that of the conventional excimer laser annealing method.
It could be suppressed to 0 or less.

According to the first and third aspects of the invention, when the offset length is 0.5 μm, the leak current can be reduced to 0.1 pA or less while keeping the on-current at 1 mA. It was Furthermore, by using the protective insulating film used during the excimer laser annealing as the gate insulating film, a good interface can be obtained and the threshold voltage can be reduced to n−c.
It was possible to suppress the voltage to as low as 3 V for the h TFT and −3 V for the p-ch TFT. Furthermore, since the activation is performed using only the region where the intensity of the excimer laser beam is uniform,
± 3% variation in characteristics of TFTs formed on a large area substrate
It was possible to suppress the difference within the range, and the manufactured shift register could be operated at the maximum clock frequency of 5 MHz.

[Brief description of drawings]

1 is an embodiment of the invention according to claim 2;

FIG. 2 is an embodiment of the invention according to claim 2;

FIG. 3 is an embodiment of the invention described in claims 1 and 3.

FIG. 4 is an embodiment of the invention described in claims 1 and 3;

FIG. 5: Excimer laser beam profile and TFT
Uniformity of properties.

FIG. 6 is a process drawing of a staggered TFT by a block irradiation method.

FIG. 7 is a process drawing of an offset structure TFT.

[Explanation of symbols]

 101 glass substrate 102 first protective film 103 semiconductor layer 104 second protective film 105 marker 106 beam with uniform intensity 107 beam with non-uniform intensity 108 region irradiated with beam with uniform intensity 109 beam with non-uniform intensity Irradiated area 110 Active layer 111 Gate insulating film 112 Gate electrode 113 Phosphorus ion 114 Source / drain region 115 Interlayer insulating film 116 Source / drain electrode 117 Active matrix array 118 Data driver 119 Gate driver area 301 Glass substrate 302 First protective film 303 semiconductor layer 304 second protective film 305 marker 306 first gate insulating film 307 beam with uniform intensity 308 beam with non-uniform intensity 309 region irradiated with beam with uniform intensity 330 beam with non-uniform intensity Irradiated region 311 Active layer 312 Second gate insulating film 313 Gate electrode 314 Phosphorous ion 315 Source / drain region 316 Offset region 317 Interlayer insulating film 318 Source / drain electrode 501 Region with non-uniform beam intensity 502 Region with uniform beam intensity 503 glass substrate 504 region where drive circuit is formed 505 first shot 506 second shot 507 third shot 508 region irradiated with beam with non-uniform intensity 509 sensor array 510 glass substrate 511 region where drive circuit is formed 512 First shot 513 Second shot 514 Third shot 515 Sensor array 516 Area irradiated with beam with uniform intensity 517 Area irradiated with beam with non-uniform intensity 601 Glass substrate 602 Protective film 603 Source / source Rain region 604 Marker 605 Semiconductor layer 606 Uniform intensity beam 607 Non-uniform intensity beam 608 Region irradiated with uniform intensity beam 609 Region irradiated with non-uniform intensity 610 Active layer 611 Gate insulating film 612 Gate electrode 613 Interlayer insulating film 614 Source / drain electrode 701 Glass substrate 702 First protective film 703 Semiconductor layer 704 Second protective film 705 Excimer laser beam 706 Active layer 707 First gate insulating film 708 Second gate insulating film 709 Gate electrode 710 phosphorus ion 711 source / drain region 712 offset region 713 interlayer insulating film 714 source / drain electrode

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location 9056-4M H01L 29/78 311 Y

Claims (3)

[Claims] 1. A thin film transistor formed on an insulating substrate, comprising a source / drain region, an active layer, a gate insulating film, a gate electrode, an interlayer insulating film and a source / drain electrode. An island-shaped active layer made of a semiconductor such as polycrystalline silicon; a first gate insulating film formed so as to cover a part of the active layer; and a first gate insulating film covering the active layer and the first gate insulating film. A formed second gate insulating film, a gate electrode formed so as to cover a part of the first gate insulating film through the second gate insulating film, and a second gate of the active layer An insulating film is formed,
And source / drain regions containing a high concentration of impurities formed in a region where the first gate insulating film is not formed, and the first gate insulating film and the second gate insulating film in the active layer And a low impurity concentration region formed in a region where the gate electrode is not formed and having an impurity concentration lower than that of the source / drain regions, and the second gate insulating film and the gate electrode. The formed interlayer insulating film, the contact hole formed in a part of the interlayer insulating film and the second gate insulating film on the source / drain region, and the source / drain region electrically via the contact hole. Thin film transistor including a source / drain electrode electrically connected to each other. 2. A method for manufacturing a thin film transistor comprising a source / drain region formed on an insulating substrate, an active layer, a gate insulating film, a gate electrode, an interlayer insulating film, and a source / drain electrode, which comprises: Forming an active layer made of a semiconductor layer such as amorphous silicon or polycrystalline silicon on a flexible substrate; forming a protective film made of a transparent insulating film that does not absorb a laser beam on the active layer; A part of the groove is removed by etching or the like to form a groove, and a step of positioning the groove as a marker and irradiating a laser to crystallize the active layer, the method of manufacturing a thin film transistor. . 3. A step of forming an amorphous semiconductor film to be an active layer on an insulating substrate; a step of forming a protective film to be a first gate insulating film on the semiconductor film; Patterning the protective film to form a marker and simultaneously forming a first gate insulating film; irradiating a laser with the marker as a mark to crystallize the semiconductor film; A step of forming the active layer leaving a region irradiated with a beam having a uniform intensity; and a second step of covering the active layer and the first gate insulating film.
Forming a gate insulating film, forming a gate electrode so as to cover a part of the first gate insulating film through the second gate insulating film, and ion-implanting impurities using the gate electrode as a mask Then
Forming a source / drain region containing a high concentration of impurities in a region where the first gate insulating film is not formed; and forming an interlayer insulating film so as to cover the second gate insulating film and the gate electrode. A step of forming a contact hole in a part of the interlayer insulating film and the second gate insulating film on the source / drain region, and electrically connecting to the source / drain region via the contact hole Method of manufacturing a thin film transistor, which comprises the step of forming the formed source / drain electrodes.