JP3539821B2 - Method for manufacturing semiconductor device - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method for manufacturing an insulated gate semiconductor element such as a thin film transistor (TFT) having a non-single-crystal crystalline silicon film and other semiconductor devices in the process of manufacturing an impurity (Ni or the like) contained in the crystalline silicon film. The present invention relates to a doping technique for minimizing an adverse effect on a device. In particular, the present invention is particularly useful when the crystalline silicon film is formed with the aid of a crystallization catalyst element (such as Ni).
[0002]
[Prior art]
In recent years, studies have been made on an insulated gate semiconductor device having a thin-film active layer (also referred to as an active region) on an insulating substrate. In particular, a thin film insulated gate transistor, a so-called thin film transistor (TFT), has been enthusiastically studied. Thin film transistors are classified into amorphous silicon TFTs and crystalline silicon TFTs according to the material and crystalline state of the semiconductor used. However, crystalline silicon is not single crystal but non-single crystal. Therefore, these are collectively referred to as non-single-crystal silicon TFTs.
[0003]
In general, the electric field mobility of a semiconductor in an amorphous state is small, and therefore, it cannot be used for a TFT requiring high-speed operation. Further, in the case of amorphous silicon, since the P-type electric field mobility is extremely small, a P-channel TFT (PMOS TFT) cannot be manufactured. Therefore, a complementary MOS circuit (CMOS) cannot be formed in combination with an N-channel TFT (NMOS TFT).
[0004]
On the other hand, a crystalline semiconductor has higher electric field mobility than an amorphous semiconductor, and thus can operate at high speed. In crystalline silicon, not only an NMOS TFT but also a PMOS TFT can be obtained in the same manner, so that a CMOS circuit can be formed.
[0005]
The non-single-crystal crystalline silicon film is obtained by thermally annealing an amorphous silicon film obtained by a vapor growth method at an appropriate temperature (usually 600 ° C. or higher) for a long time or irradiating a strong light such as a laser ( Light annealing).
[0006]
Regarding the method by thermal annealing, as described in JP-A-6-244104, elements such as nickel, iron, cobalt, platinum and palladium (hereinafter referred to as crystallization catalyst elements or simply catalyst elements) are made of amorphous silicon. By utilizing the effect of accelerating the crystallization of the crystalline silicon film, a crystalline silicon film can be obtained by thermal annealing at a lower temperature and for a shorter time than usual.
[0007]
Other similar techniques are disclosed in JP-A-6-318701 and JP-A-6-333951. In the silicon film having such a crystallization catalyst element, impurity regions such as a source and a drain were formed by irradiating and implanting N-type or P-type impurity ions by means such as ion doping. It has been clarified that the activation of the impurity element can be performed by thermal annealing at a lower temperature than in the past. (JP-A-6-267980, JP-A-6-267789)
[0008]
For this purpose, the concentration of the crystallization catalyst element is 1 × 10¹⁵~ 1 × 10¹⁹Atom / cm^Three It is desirable that If the concentration is lower than this range, crystallization is not promoted, and if the concentration is higher than this range, the characteristics of the silicon semiconductor are adversely affected. In this case, the concentration of the catalyst element is defined as a maximum value analyzed by secondary ion mass spectrometry (SIMS). In many cases, the catalytic element shows a distribution in the film.
[0009]
[Problems to be solved by the invention]
However, in a semiconductor device manufactured using crystalline silicon containing a catalyst element that promotes the above-mentioned crystallization, many devices having high electric field mobility and high OFF current have poor characteristics. In particular, when a large number of the semiconductor devices are formed on the same substrate, not only the OFF current is high but also the value of the OFF current greatly varies among the semiconductor devices.
[0010]
It is considered that the cause of the increase in the OFF current and the above-mentioned variation are caused by the catalyst element which promotes the crystallization. That is, it is presumed that the main cause is that the catalytic element that promotes the crystallization is applied to the junction.
[0011]
Such characteristics are fatal defects particularly for TFTs constituting a pixel portion of a liquid crystal display.
[0012]
[Means for Solving the Problems]
Among semiconductor devices manufactured using crystalline silicon into which nickel has been introduced as a catalyst element for promoting crystallization, those having impurity regions such as source and drain formed of phosphorus have a relatively low OFF current (10 pA). (Or less) or less, and the above-mentioned variation was hardly observed. Based on this fact, the characteristics of phosphorus have been carefully studied, and as a result, it has been found that phosphorus has been reported to have the property of gettering impurities.
[0013]
According to the report, phosphorus shows a particularly high gettering function for nickel. In addition, elements that are considered to have an adverse effect on a semiconductor device, such as copper and iron, can be gettered by phosphorus. From these facts, it can be inferred that phosphorus neutralizes the characteristics of nickel in the above-described semiconductor device in some way and suppresses the adverse effect on the OFF current characteristics of nickel.
[0014]
A first aspect of the present invention is that a source-drain region of an active layer composed of a crystalline silicon film into which a catalytic element for promoting crystallization is introduced is doped with phosphorus-containing ions by a known ion doping method (also referred to as a plasma doping method). After the ion implantation, the N-type semiconductor device is obtained by improving the crystallinity of the silicon film and activating impurities by thermal annealing or optical annealing (or both).
[0015]
A second aspect of the present invention is that a source-drain region of an active layer composed of a crystalline silicon film into which a catalytic element for promoting crystallization is introduced is doped with phosphorus-containing ions by a known ion doping method (also referred to as a plasma doping method). After ion implantation, P-type impurities are further implanted into silicon which has been converted into N-type with phosphorus by the same method as phosphorus, and the crystallinity of the silicon film is improved by thermal annealing or optical annealing (or both). And activation of impurities to obtain a P-type semiconductor device.
[0016]
A third aspect of the present invention is a known ion doping method (also referred to as a plasma doping method) in which phosphorus-containing ions are added to source / drain regions of an active layer formed of a crystalline silicon film into which a catalytic element that promotes crystallization is introduced, Alternatively, after implantation by an ion implantation method, a P-type impurity is further implanted into a desired portion of silicon which has been converted into N-type with phosphorus by a method similar to that of phosphorus, and the silicon film is subjected to thermal annealing or optical annealing (or both). By improving crystallinity and activating impurities, an N-type semiconductor device and a P-type semiconductor device are selectively obtained on the same substrate.
[0017]
A fourth aspect of the present invention is that a phosphorus-containing ion is doped in the LDD region and the source / drain region of the active layer made of a crystalline silicon film into which a catalytic element for promoting crystallization is introduced by a known ion doping method (plasma doping method). Or by ion implantation, and then improving the crystallinity of the silicon film and activating impurities by thermal annealing or optical annealing (or both) to obtain an N-type semiconductor device. And
[0018]
A fifth aspect of the present invention is that a phosphorus-containing ion is introduced into an LDD region of an active layer made of a crystalline silicon film into which a catalytic element for promoting crystallization is introduced by a known ion doping method (also referred to as a plasma doping method) or ion implantation. After implantation, a P-type impurity is further implanted into the LDD region and the source / drain region in the same manner as phosphorus, and the crystallinity of the silicon film is improved by thermal annealing or optical annealing (or both). And activation of impurities to obtain a P-type semiconductor device.
[0019]
According to a sixth aspect of the present invention, phosphorus-containing ions are doped in the LDD region and the source / drain region of the active layer made of a crystalline silicon film into which a catalytic element for promoting crystallization is introduced by a known ion doping method (plasma doping method). Or an ion implantation method, and then implant a P-type impurity into the N-type silicon with phosphorus in the same manner as phosphorus, and thermally or optically anneal (or both) the silicon film. A P-type semiconductor device is obtained by improving crystallinity and activating impurities.
[0020]
According to a seventh aspect of the present invention, in an active layer made of a crystalline silicon film into which a catalytic element for promoting crystallization is introduced, ions containing phosphorus in the LDD region and the source / drain regions are formed by a known ion doping method (plasma). After doping by ion implantation, P-type impurities are further implanted into a desired portion of silicon which has been converted into N-type with phosphorus by a method similar to that for phosphorus, and then thermal annealing or optical annealing (or the like) is performed. In both cases, the N-type semiconductor device and the P-type semiconductor device are obtained on the same substrate by improving the crystallinity of the silicon film and activating impurities.
[0021]
In the first to seventh aspects of the present invention, a metal element such as nickel, platinum, cobalt, iron, or palladium may be used as a catalyst element for promoting crystallization. In particular, the effect of promoting crystallization of silicon is excellent.
[0022]
The concentration of the catalyst element is 1 × 10¹⁵~ 1 × 10¹⁹Atom / cm^Three Is preferably within the range. 1 × 10¹⁵Atom / cm^Three If the concentration is lower than the above, the effect of promoting crystallization cannot be obtained. Also, 1 × 10¹⁹Atom / cm^Three This is because at such a high concentration, silicon has metallic properties and the semiconductor properties disappear. In this specification, the concentration of a catalytic element in a silicon film is defined as the maximum value of values analyzed and measured by secondary ion mass spectrometry (SIMS).
[0023]
【Example】
[Embodiment 1] In this embodiment, a transistor during fabrication is formed on a crystalline silicon film into which nickel has been introduced as a catalyst element for promoting crystallization, and ions containing phosphorus are formed in the source / drain regions by known ions. After implantation by a doping method (also referred to as a plasma doping method), the crystallinity of the silicon film is improved and the impurities are activated by thermal annealing or optical annealing (or both), thereby providing a high-performance N-type semiconductor device. Here is how to get Hereinafter, a high-performance semiconductor device refers to a device having an OFF current of about 10 pA or less and a small variation in characteristics between elements. FIG. 1 shows a manufacturing process of the thin film transistor of this embodiment.
[0024]
First, a 2000-mm-thick base silicon oxide film 102 is formed on a glass substrate (Corning 7059 is used in this embodiment) 101, and a 500-mm-thick amorphous silicon film 103 is continuously formed thereon by a plasma CVD method. I do. Then, a 10 ppm aqueous solution of nickel acetate is applied to the silicon surface, and a nickel acetate layer (not shown) is formed by spin coating. It is better to add a surfactant to the aqueous nickel acetate solution. (Fig. 1 (A))
[0025]
Then, the amorphous silicon film 103 is crystallized by thermal annealing at 550 ° C. for 4 hours to obtain a crystalline silicon film 104. At this time, nickel plays a role of a crystal nucleus, and crystallization of the amorphous silicon film 103 is promoted.
[0026]
The processing at a low temperature of 550 ° C. for 4 hours (below the strain point temperature of Corning 7059) and in a short time is due to the action of nickel. Details are described in JP-A-6-244104.
[0027]
The concentration of the catalyst element is 1 × 10¹⁵~ 1 × 10¹⁹Atom / cm^Three Is preferably within the range. The concentration of the catalytic element in the silicon film described in this embodiment is 1 × 10¹⁷~ 5 × 10¹⁸Atom / cm^Three This value is defined by the maximum value of the analysis and measurement values by secondary ion mass spectrometry (SIMS).
[0028]
In order to further enhance the crystallinity of the crystalline silicon film 104 obtained as described above, the film is irradiated with an excimer laser which is a high-power pulse laser. In this embodiment, a KrF excimer laser (wavelength 248 nm, pulse width 30 nsec) is used. Laser energy density is 100mJ / cm^Two   ~ 500mJ / cm^Two Is selected so that the crystallinity of the crystalline silicon film 104 is as high as possible, and irradiation is performed. In this embodiment, 370 mJ / cm^Two Laser irradiation. When the area of the irradiation object exceeds the beam size of the excimer laser, the irradiation is performed while the laser beam is relatively shifted with respect to the non-irradiation object. At this time, focusing on one point of the non-irradiated object, the laser light of 2 to 20 shots is irradiated. The substrate temperature during laser irradiation is set to 200 ° C. (FIG. 1 (B))
[0029]
Next, the crystalline silicon film 104 is etched into an island shape to form an island-shaped silicon region 105. Further, a silicon oxide film 106 having a thickness of 1200 ° was deposited as a gate insulating film by a plasma CVD method. TEOS and oxygen were used as source gases for plasma CVD. The substrate temperature during film formation was 250 to 380 ° C, for example, 300 ° C. (Fig. 1 (C))
[0030]
Subsequently, a gate electrode 107 is formed by depositing and etching an aluminum film (containing 0.1 to 2% of silicon) having a thickness of 3000 to 8000, for example, 6000, by a sputtering method. (Fig. 1 (C))
[0031]
Next, phosphorus ions are implanted into the island-shaped silicon region 105 using the gate electrode 107 as a mask by an ion doping method. Phosphine (PH) diluted to 1 to 10% with hydrogen is used as a doping gas._Three ) Is used. The acceleration voltage is 60 to 90 kV, for example, 80 kV, and the dose is 1 × 10¹³~ 8 × 10¹⁵Atom / cm^Three :For example, 2 × 10¹⁴Atom / cm^Three And Under these conditions, phosphorus ions are 3 × 10¹⁹Atom / cm^Three Is added to the island-shaped silicon region 105 at a concentration of As a result, N-type impurity regions 108 (source) and 109 (drain) are formed. (Fig. 1 (D))
[0032]
According to the inventor's experience, the concentration of the impurity imparting N-type or P-type conductivity in the silicon region is 3 × 10¹⁹~ 1 × 10^{twenty one}Atom / cm^Three It is good to be in the range. The substrate temperature during ion doping is room temperature.
[0033]
Then, optical annealing is performed using a KrF excimer laser to activate the doped phosphorus and cause the phosphorus to getter nickel. Laser energy density is 100-350mJ / cm^Three For example, 250 mJ / cm^Three And When the area of the irradiation object exceeds the beam size of the excimer laser, the irradiation is performed while the laser beam is relatively shifted with respect to the non-irradiation object. At this time, focusing on one point of the non-irradiated object, the laser light of 2 to 20 shots is irradiated. The substrate temperature during laser irradiation is set to 200 ° C. Thereafter, thermal annealing is performed at 350 ° C. for 2 hours in a nitrogen atmosphere. In this step, both the optical annealing and the thermal annealing are performed, but only one of them may be performed. (FIG. 1 (E))
[0034]
Subsequently, a silicon oxide film 110 having a thickness of 6000 ° is formed as an interlayer insulator by a plasma CVD method, and a contact hole is formed in the silicon oxide film 110. Then, a metal material, for example, a multilayer film of titanium and aluminum is formed and patterned to form the source / drain electrodes / wirings 111 and 112 of the TFT. Finally, thermal annealing at 200 to 350 ° C. is performed in a hydrogen atmosphere at 1 atm. (FIG. 1 (F))
[0035]
[Embodiment 2] In this embodiment, in a process of manufacturing a transistor using a crystalline silicon film into which nickel has been introduced as a crystallization catalyst element, ions containing phosphorus in the source / drain regions are formed by a known ion doping method. (Also referred to as a plasma doping method), and then implanted with P-type impurity ions (in the present embodiment, ions containing boron). A method for obtaining a high-performance P-type semiconductor device by improving and activating impurities will be described.
[0036]
In this embodiment, a step of implanting P-type impurity ions (in this embodiment, ions containing boron) into the source / drain regions may be added to the steps of the first embodiment. This step may be performed after doping with phosphorus ions shown in FIG. 1C or before doping with phosphorus ions. Hereinafter, only the doping process of the added P-type impurity ions will be described.
[0037]
In this embodiment, boron is implanted into the silicon region as a P-type impurity ion using the gate electrode as a mask. Diborane (B2H6) diluted to 5% with hydrogen is used as a doping gas. The acceleration voltage is 60 to 90 kV, for example, 80 kV, and the dose is 1 × 10¹³~ 8 × 10¹⁵Atom / cm^Three , For example, 4 × 10¹⁴Atom / cm^Three And
[0038]
Note that the density obtained by subtracting the density of phosphorus in the region from the maximum value of the density of boron implanted in the source / drain regions in the region by this step is 3 × 10¹⁹~ 1 × 10^{twenty one}Atom / cm^Three The dose is adjusted so that The substrate temperature during ion doping is room temperature. As a result, P-type impurity regions 108 (source) and 109 (drain) are formed.
[0039]
In this embodiment, when a P-type TFT is manufactured, nickel and phosphorus are added to an active layer made of a crystalline silicon film, in addition to an impurity such as boron that imparts P-type conductivity. Therefore, by the catalytic action of nickel, a silicon film having excellent crystallinity can be obtained at a low temperature and in a short time, and nickel which is no longer necessary due to phosphorus can be gettered. In addition, a TFT with less variation in characteristics for each element can be manufactured.
[0040]
[Embodiment 3] In this embodiment, a plurality of transistors during fabrication are formed in a crystalline silicon film into which nickel has been introduced as a catalyst element for promoting crystallization, and ions containing phosphorus are known in source / drain regions. Is implanted by an ion doping method (also referred to as a plasma doping method), and P-type impurity ions (in the present embodiment, ions containing boron) are selectively implanted to form a high-performance N-type semiconductor on the same substrate. A method for separately producing the device and the P-type semiconductor device will be described.
[0041]
FIG. 2 is a manufacturing process diagram of the TFT of this embodiment, and shows a manufacturing process of a CMOS type TFT. First, as shown in FIG. 2A, a silicon oxide film 202 serving as a base film is formed on a glass substrate (Corning 1737) 201 by a plasma CVD method using monosilane and dinitrogen monoxide as raw materials at 1000 to 5000 °. For example, a film is formed to a thickness of 2000 mm. Further, an amorphous silicon film 203 having a thickness of 1000 ° is formed by a plasma CVD method using monosilane as a raw material.
[0042]
Next, a very thin silicon oxide film (not shown) is formed on the surface of the amorphous silicon film 203 using a hydrogen peroxide solution. Next, an acetate solution containing 1 to 30 ppm, for example, 10 ppm of nickel is applied by a spin coating method and dried to form a catalyst layer 204 containing nickel. (Fig. 2 (A))
[0043]
Thereafter, the amorphous silicon film 203 was crystallized by annealing at 550 ° C. for 4 hours in a nitrogen atmosphere. At this time, nickel moves from the amorphous silicon film 203 to the underlying silicon oxide film 202, and crystallization proceeds from top to bottom.
[0044]
After the crystallization step by annealing, XeCl laser (wavelength 308 nm) is irradiated to further improve the crystallinity of the crystallized silicon film.
[0045]
Next, as shown in FIG. 2B, the crystallized silicon film is etched into islands to form island-shaped silicon regions 205 and 206, respectively. After that, a silicon oxide film 207 having a thickness of 1000 ° is formed as a gate insulating film by a plasma CVD method using monosilane and dinitrogen monoxide as raw materials.
[0046]
Subsequently, an aluminum film (containing 0.1 to 2% of scandium) having a thickness of 3000 to 8000 °, for example, 4000 ° was formed by a sputtering method and etched to form gate electrodes 208 and 209.
Next, as shown in FIG. 2 (C), phosphorus ions are doped in a self-aligned manner into the island-shaped silicon regions 205 and 206 by using the gate electrodes 208 and 209 as masks. Phosphine (PH) diluted to 1 to 10% with hydrogen is used as a doping gas._Three) Is used. The acceleration voltage is 60 to 90 kV, and the dose is 1 × 10¹³~ 8 × 10¹⁵Atom / cm^ThreeAnd it is sufficient. In this embodiment, the acceleration voltage is set to 80 kV and 2 × 10¹⁴Atom / cm^ThreeAnd Under these conditions, 3 × 10¹⁹Atom / cm^ThreeIs added to each of the island-shaped silicon regions 205 and 206 to form N-type impurity regions 210 to 213.
[0048]
Next, as shown in FIG. 2D, a region to be an N-type TFT is covered with a resist mask 214 by a known photoresist method. In this state, P-type impurity ions are added to the island-shaped silicon region 206 by ion doping using the gate electrode 209 as a mask. In this embodiment, boron is added. As a doping gas, diborane (B) diluted to 5% with hydrogen_Two H₆ ) Is used. The acceleration voltage is 60 to 90 kV, and the dose is 1 × 10¹³~ 8 × 10¹⁵Atom / cm^Three And it is sufficient. In this embodiment, the acceleration voltage is 80 kV and the dose is 4 × 10¹⁴Atom / cm^Three And As a result, in the island-shaped silicon region 206, the conductivity types of the N-type impurity regions 212 and 213 are inverted, and P-type impurity regions 215 (source) and 216 (drain) are formed. On the other hand, the conductivity types of the impurity regions 210 and 211 covered with the resist mask 214 are stored as N-type.
[0049]
In this step, the density obtained by subtracting the concentration of phosphorus in the source / drain regions 215 and 216 from the maximum value of boron in the region is 3 × 10 5.¹⁹~ 1 × 10^{twenty one}Atom / cm^Three The dose is adjusted so that The substrate temperature during ion doping is room temperature.
[0050]
Further, in this embodiment, boron is added after adding phosphorus ions. However, phosphorus ions may be added after adding boron first. In this case, first, as shown in FIG. 2D, the region of the N-type TFT is covered with a resist mask 214, and boron ions are added. Then, after removing the resist mask 214, phosphorus ions may be added.
[0051]
Next, after removing the resist mask 214, as shown in FIG. 2E, the added impurities are activated by laser annealing, and the island-shaped silicon regions 205 and 206 damaged by the doping process are activated. Restores crystallinity. In this embodiment, the N type impurity regions 210 and 211 and the P type impurity regions 215 and 216 contain 3 × 10 3 phosphorus.¹⁹Atom / cm^Three , Nickel is gettered by phosphorus by laser irradiation. As a laser beam, a KrF excimer laser (wavelength 248 nm) is used. In order to effectively getter nickel, the irradiation condition of the laser beam is such that the energy density is 200 to 400 mJ / cm.^Two , For example, 250 mJ / cm^Two It is good to Further, it is preferable that the laser light of 2 to 20 shots is irradiated per one place. The substrate temperature at the time of laser light irradiation is 200 ° C.
[0052]
After the laser annealing, thermal annealing is performed at 350 ° C. for 2 hours in a nitrogen atmosphere. In this embodiment, both the laser annealing and the thermal annealing are performed, but either one of the laser annealing and the thermal annealing may be performed.
[0053]
Subsequently, as shown in FIG. 2F, a silicon oxide film 216 having a thickness of 6000 ° is formed as an interlayer insulator by a plasma CVD method. Then, a contact hole is formed in the interlayer insulator 216, and electrodes and wirings 217 to 221 of an N-type TFT and a P-type TFT are formed using a metal material, for example, a laminated film of a titanium film and an aluminum film. Finally, heat treatment is performed in a hydrogen atmosphere at 350 ° C. for 2 hours. (FIG. 2 (F))
[0054]
Through the above steps, a CMOS TFT in which an N-type TFT and a P-type TFT are complementarily combined is completed.
[0055]
Embodiment 4 In this embodiment, when a thin film transistor having an LDD structure is manufactured using a crystalline silicon film into which nickel is introduced as a catalyst element for promoting crystallization, a source / drain region, an LDD region, Then, ions containing phosphorus are implanted by a known ion doping method (also referred to as a plasma doping method), and then thermal anneal and / or optical anneal (or both) are performed to improve the crystallinity of the silicon film and activate the impurities. In this manner, a method for obtaining an N-type semiconductor device having high characteristics will be described.
[0056]
The steps up to the formation of the crystalline silicon film are performed by the method described in the first embodiment. Thereafter, a thin film transistor having a known LDD structure is formed by a known method. The activation of the source / drain region and the LDD region follows the method described in the first embodiment. FIG. 3 shows a TFT having an LDD structure having sidewalls.
[0057]
As shown in FIG. 3, a low-concentration impurity region 302 having a lower impurity concentration than the source / drain region is formed between the source / drain region 301 and the channel region. In particular, the low concentration impurity region 302 on the drain side is called an LDD region.
[0058]
In this embodiment, the source / drain region 301 contains 1 × 10²⁰~ 1 × 10^{twenty one}Atom / cm^Three It is injected so much. In the low concentration impurity region 302, 4 × 10¹⁶~ 7 × 10¹⁷Atom / cm^Three It is injected so much. When doping is performed at these values, unnecessary nickel due to phosphorus can be effectively gettered, so that a TFT having a small variation in characteristics between elements and a low OFF current can be obtained.
[0059]
[Embodiment 5] In this embodiment, when a thin film transistor having an LDD structure is manufactured using a crystalline silicon film into which nickel has been introduced as a crystallization catalyst element, ions containing phosphorus are known in the LDD region. Is implanted by an ion doping method (also referred to as a plasma doping method), P-type impurity ions are further implanted into the source / drain region and the LDD region, and then silicon is subjected to thermal annealing or optical annealing (or both). A method for obtaining a high-performance P-type semiconductor device by improving crystallinity of a film and activating impurities will be described.
[0060]
The steps are almost the same as in Example 4. The difference is that the LDD regions (215 and 216) have a concentration of 3 × 10¹⁷~ 3 × 10¹⁸Atom / cm^Three With the addition of boron, the LDD region is inverted from N-type to P-type. The concentration of boron in the LDD region is 3 × 10¹⁷~ 3 × 10¹⁸Atom / cm^Three And In the source (312) / drain (313) region, boron is replaced by 3 × 10 3 instead of phosphorus.¹⁹~ 1 × 10^{twenty one}Atom / cm^Three Implanted to show N-type conductivity.
[0061]
Since the concentration of phosphorus added to the LDD region is about two to four orders of magnitude lower than the concentration of phosphorus added to the zose / drain region, when inverting the LDD region from N-type to P-type, the dose of boron is reduced. The conductivity of the source / drain region can be made smaller than when the conductivity is inverted. In order to invert the LDD region from N-type to P-type, the density obtained by subtracting that of phosphorus in the region from the maximum value of the density of boron in the LDD region in the region is 3 × 10 3.¹⁷~ 3 × 10¹⁸Atom / cm^Three Adjust so that
[0062]
In this embodiment, when a P-type TFT is manufactured, nickel and phosphorus are added to an active layer made of a crystalline silicon film, in addition to an impurity such as boron that imparts P-type conductivity. Therefore, by the catalytic action of nickel, a silicon film having excellent crystallinity can be obtained at a low temperature and in a short time, and nickel which is no longer necessary due to phosphorus can be gettered. In addition, a TFT with less variation in characteristics for each element can be manufactured.
[0063]
[Embodiment 6] In this embodiment, when a thin film transistor having an LDD structure is formed using a crystalline silicon film into which nickel is introduced as a crystallization catalyst element, phosphorus is contained in a source / drain region and an LDD region. Ions are implanted by a known ion doping method (also referred to as a plasma doping method), and then P-type impurity ions are further implanted into the source / drain region and the LDD region. In both cases, a method for obtaining a high-performance P-type semiconductor device by improving the crystallinity of a silicon film and activating impurities will be described.
[0064]
The steps are almost the same as in the fifth embodiment. The difference is that in the source (212) / drain (213) regions, boron is contained in a concentration exceeding 3 × 10¹⁹~ 1 × 10^{twenty one}Atom / cm^Three It is injected so much. Also, in the LDD regions (215 and 216), boron is contained in a concentration exceeding 3 × 10 3 at a concentration exceeding phosphorus.¹⁷~ 4 × 10¹⁸Atom / cm^Three It is injected so much. Therefore, the source / drain region and the LDD region shift from N type to P type.
[0065]
For this purpose, the density obtained by subtracting the maximum density of boron in the source / drain region in the region from the maximum value of the density of boron in the region is 3 × 10 4.¹⁹~ 1 × 10^{twenty one}Atom / cm^Three And the maximum density of boron implanted in the LDD region minus the density of phosphorus in the region is 3 × 10¹⁷~ 3 × 10¹⁸Atom / cm^Three The boron doping condition is determined so that
[0066]
In this embodiment, when a P-type TFT is manufactured, nickel and phosphorus are added to an active layer made of a crystalline silicon film, in addition to an impurity such as boron that imparts P-type conductivity. Therefore, a silicon film having excellent crystallinity can be obtained at a low temperature and in a short time by the catalytic action of nickel, and nickel can be gettered by phosphorus, so that electrical characteristics are excellent and each element has A TFT with less variation in characteristics can be manufactured.
[0067]
[Embodiment 7] In this embodiment, an example in which a CMOS thin film transistor in which an N type thin film transistor and a P type thin film transistor are complementarily combined is formed. FIG. 4 shows this embodiment. First, an intrinsic (I-type) amorphous silicon film is formed to a thickness of 500 ° by a plasma CVD method on a glass substrate (corning 7059 or 1737) 401 on which an underlayer is formed on the upper surface. A silicon oxide film 402 is formed to a thickness of, for example, 2000 °.
[0068]
Next, the surface of the amorphous silicon film 403 is oxidized by a UV oxidation method to form an extremely thin oxide film (not shown). With this oxide film, the surface characteristics of the amorphous silicon film 403 are improved. Next, an acetate solution containing 1 to 30 ppm, for example, 10 ppm of nickel is applied by a spin coating method and dried to form a nickel acetate layer 404. Note that the nickel acetate layer 404 does not always form a complete layer. (FIG. 4A)
[0069]
After that, thermal annealing is performed at 550 ° C. for 4 hours in a nitrogen atmosphere to crystallize the amorphous silicon film 403. By the heat treatment, the nickel acetate layer 404 is decomposed, and as the nickel element diffuses from the surface of the amorphous silicon film 403 to the underlying silicon oxide film 402 through the oxide film (not shown), the crystal growth of the amorphous silicon film 403 occurs. Progresses. After the crystallization step, laser light may be irradiated to further improve the crystallinity of the crystallized silicon film.
[0070]
The metal element such as nickel is 1 × 10¹⁹When present in a crystallized silicon film at a high concentration of at least atoms / cm 2, metallic properties appear in silicon and semiconductor characteristics disappear, and the concentration of 1 × 10¹⁵Atom / cm^Three If it is less than the above, the crystallization effect cannot be obtained. Therefore, the concentration of nickel in the crystallized silicon film is 1 × 10¹⁵~ 1 × 10¹⁹Atom / cm^Three Must be within the range. Therefore, the nickel concentration in the acetate solution, the application conditions of the acetate solution, and the like are determined in advance.
[0071]
The crystallized silicon film is etched to form island-shaped silicon regions 405 and 406 as shown in FIG. The island-shaped silicon region 405 forms the active layer of the N-type TFT, while the island-shaped silicon region 406 forms the active layer of the P-type TFT.
[0072]
Further, a 1500-nm-thick silicon oxide film 407 is deposited by a plasma CVD method. Next, an aluminum film is deposited to a thickness of 4000 ° by sputtering. This aluminum film constitutes the gate electrodes 408 and 409. The aluminum film contains 0.2 wt% of scandium in advance to suppress generation of hillocks and whiskers.
[0073]
Next, the aluminum film is anodized in an electrolytic solution to form a dense anodic oxide film (not shown) on the surface to a thickness of about 100 °, and a photoresist mask 410 is formed on the dense anodic oxide film. Then, gate electrodes 408 and 409 are formed by patterning the aluminum film.
[0074]
As shown in FIG. 4C, the gate electrodes 408 and 409 are anodized again with the photoresist mask 410 attached. As the electrolytic solution, an acidic solution containing 3 to 20% of citric acid, oxalic acid, chromic acid or sulfuric acid, for example, a 3% oxalic acid aqueous solution is used. In this case, since a photoresist mask 410 and a dense anodic oxide film (not shown) are present on the surfaces of the gate electrodes 408 and 409, porous anodic oxides 411 and 412 are formed only on the side surfaces of the gate electrodes 408 and 409. It is formed. The length of the low concentration impurity region (LDD region) is determined by the growth distance of the porous anodic oxides 411 and 412. This growth distance can be controlled by the anodic oxidation treatment time. In this embodiment, porous anodic oxides 411 and 412 are grown to a length of 7000 °.
[0075]
After removing the photoresist mask 410, the gate electrodes 411 and 412 are anodized again to form dense and strong anodic oxide films 409 and 410. In this embodiment, a 3% tartaric acid ethylene glycol solution is neutralized to pH 6.9 with aqueous ammonia and used as an electrolytic solution. (FIG. 4 (D))
[0076]
Next, using the porous anodic oxides 411 and 412 and the dense anodic oxides 413 and 414 as masks, the silicon oxide film 407 is etched to form gate insulating films 415 and 416, respectively. As an etching method, any of a wet etching method and a dry etching method may be employed as long as only the silicon oxide film 407 can be etched without etching the anodic oxides 411 to 414. In this embodiment, ClF_Three The silicon oxide film 407 is etched by dry etching using a gas.
[0077]
As shown in FIG. 4E, a dense anodic oxide (not shown) and porous anodic oxides 411 and 412 are sequentially removed. The dense anodic oxide (not shown) is removed with buffered hydrofluoric acid, and the porous anodic oxides 411 and 412 are removed with a mixed acid of phosphoric acid, acetic acid and nitric acid. Since the porous anodic oxides 411 and 412 can be easily removed, the dense and strong anodic oxides 413 and 414 are not etched.
[0078]
Next, impurities are implanted into the island-shaped silicon 405 and 406 by ion doping using the gate electrodes 408 and 409 as a mask. In this embodiment, phosphine (PH3) diluted to 1 to 10% with hydrogen is used as a doping gas to implant phosphorus. The substrate temperature during doping is room temperature. In this case, doping conditions such as an acceleration voltage, a dose amount, and the number of times of doping are appropriately set so that the gate insulating films 415 and 416 function as a translucent mask.
[0079]
By doping, in the island-shaped silicon regions 405 and 406, the regions whose surfaces are exposed are implanted with high-concentration phosphorus ions to form N-type high-concentration impurity regions 417 to 420. These N-type high-concentration impurity regions 417 to 420 become source / drain regions of the TFT. In addition, since the regions immediately below the gate electrodes 405 and 406 are not implanted with phosphorus ions, channel formation regions 421 and 422 are formed. Further, in a region covered only by the gate insulating films 415 and 416, since the phosphorus ions are blocked by the gate insulating films 415 and 416, a small amount of phosphorus is implanted, and the N-type low-concentration impurity regions 423 to 426 are removed. It is formed. (FIG. 4E)
[0080]
Note that in the above doping step, the concentration of phosphorus ions is 3 × 10 4 in the N-type high-concentration impurity regions 417 to 429.¹⁹~ 1 × 10^{twenty one}Atom / cm^Three In the low concentration impurity regions 423 to 426, 4 × 10¹⁶~ 7 × 10¹⁷Atom / cm^Three The conditions of the doping step are set so that
[0081]
Next, as shown in FIG. 4 (F), the resist is covered with a resist 427, and patterning is performed to remove a portion of the resist which will become a P-type TFT. Subsequently, boron is implanted by an ion doping method as an impurity for imparting P-type conductivity. As a doping gas, diborane (B) diluted to 5% with hydrogen_Two H₆ ) Is used. The substrate temperature during ion doping is room temperature. As a result, in the island-shaped silicon region 406, the conductivity types of the N-type high-concentration impurity regions 419 and 420 and the N-type low-concentration impurity regions 425 and 426 are respectively inverted, and the P-type high-concentration impurity regions 428 ( Source), 429 (drain), and P-type low-concentration impurity regions 430, 431. On the other hand, the conductivity types of the high-concentration impurity regions 417 (source) and 418 (drain) and the low-concentration impurity regions 423 and 424 covered with the resist 427 are kept as N-type.
[0082]
In the P-type high-concentration impurity regions 428 and 429 serving as source / drain regions, the concentration of boron is 3 × 10 higher than the concentration of phosphorus in the regions.¹⁹~ 1 × 10^{twenty one}Atom / cm^Three In the high P-type low concentration impurity regions 430 and 431, the boron concentration is 3 × 10¹⁷~ 4 × 10¹⁸Atom / cm^Three The conditions of the doping step are determined so as to be higher.
[0083]
Next, after removing the resist mask 214, as shown in FIG. 4G, the added impurities are activated by laser annealing, and the island-like silicon regions 405 and 406 damaged by the doping process are activated. Restores crystallinity.
[0084]
In this embodiment, the N / P type source / drain 417, 418, 428, 429 contains 1 × 10 phosphorus.²⁰~ 1 × 10^{twenty one}Atom / cm^Three And the N-type and P-type low-concentration impurity regions 423, 424, 430, and 432 further contain 4 × 10¹⁶~ 7 × 10¹⁷Atom / cm^Three Since it is injected at a concentration, nickel is effectively gettered by phosphorus by irradiating a laser.
[0085]
When a KrF excimer laser (wavelength: 248 nm) is used as the laser beam, the laser beam is irradiated under the condition that the energy density is 200 to 400 mJ / cm in order to effectively getter nickel.^Two , For example, 250 mJ / cm^Two It is good to Further, it is preferable that the laser light of 2 to 20 shots is irradiated per one place. The substrate temperature at the time of laser light irradiation is 200 ° C.
[0086]
After the laser annealing, thermal annealing is performed at 350 ° C. for 2 hours in a nitrogen atmosphere. In this embodiment, both the laser annealing and the thermal annealing are performed, but either one of the laser annealing and the thermal annealing may be performed.
[0087]
As shown in FIG. 4H, a silicon oxide film having a thickness of 1 μm is formed as an interlayer insulating film 432 by a plasma CVD method, and a contact hole is formed thereon. Then, source / drain electrodes and wirings 433, 434, and 435 are formed on the contact hole using a metal material, for example, a multilayer film of titanium and aluminum. Finally, heat treatment is performed for 2 hours in a hydrogen atmosphere at 350 ° C. Through the above steps, a CMOS thin film transistor is completed. (FIG. 4 (H))
[0088]
Further, in this embodiment, boron is added after adding phosphorus ions. However, phosphorus ions may be added after adding boron first. In this case, first, as shown in FIG. 2D, the region of the N-type TFT is covered with a resist 427, and boron ions are added. Then, after removing the resist 427, phosphorus ions may be added.
[0089]
【The invention's effect】
According to the present invention, even when a crystalline silicon film into which a crystallization catalyst element is introduced, a thin-film TFT having a low OFF current and small variations in characteristics can be manufactured.
[0090]
In particular, when nickel was used as a catalyst element for promoting crystallization, the effect was remarkable. This effect is particularly effective when a plurality of elements having the same function are formed on the same substrate. This is because if the OFF current varies greatly between the elements, the characteristics will be non-uniform between the elements. Such non-uniformities are particularly detrimental to pixels formed in TFT liquid crystal display devices. Therefore, the present invention is considered to be industrially useful.
[Brief description of the drawings]
FIG. 1 is a manufacturing process diagram of a thin film transistor of Examples 1 and 2.
FIG. 2 is a manufacturing process diagram of the thin film transistor of Example 3.
FIG. 3 is a configuration diagram of a thin film transistor according to a fourth embodiment.
FIG. 4 is a manufacturing process diagram of the thin film transistor of Example 7.
[Explanation of symbols]
101 glass substrate
102 Underlayer
103 amorphous silicon film
105 Active layer
106 Gate insulating film
107 Gate electrode
108, 212 source area
109, 213 drain region
110, 217 interlayer insulating film
111, 218 source electrode
112, 219 Drain electrode

Claims (6)

Etching the crystalline silicon film, into which a catalytic element promoting silicon crystallization is introduced, into islands to form island silicon,
Forming a gate insulating film on the island-shaped silicon;
Forming a gate electrode on the gate insulating film;
By adding phosphorus to the island-shaped silicon using the gate electrode as a mask , a source region, a drain region, and a low-concentration impurity region are formed in the island-shaped silicon, and phosphorus is adjacent to the low-concentration impurity region. Forming a channel forming region not added ,
The source region and the drain region are doped so that the phosphorus is contained at 1 × 10 ²⁰ to 1 × 10 ²¹ atoms / cm ³ , and the low concentration impurity region is doped with the phosphorus at 4 × 10 ^{16 to} 7 × 10 7 atoms / cm ^3. Is added so as to contain ¹⁷ atoms / cm ³ ,
A method for manufacturing a semiconductor device, wherein the catalyst element that promotes crystallization of silicon is gettered to the phosphorus added to the island-shaped silicon. The crystalline silicon film into which nickel has been introduced is etched into islands to form island-like silicon,
Forming a gate insulating film on the island-shaped silicon;
Forming a gate electrode on the gate insulating film;
By adding phosphorus to the island-shaped silicon using the gate electrode as a mask , a source region, a drain region, and a low-concentration impurity region are formed in the island-shaped silicon, and phosphorus is adjacent to the low-concentration impurity region. Forming a channel forming region not added ,
The source region and the drain region are doped so that the phosphorus is contained at 1 × 10 ²⁰ to 1 × 10 ²¹ atoms / cm ³ , and the low concentration impurity region is doped with the phosphorus at 4 × 10 ^{16 to} 7 × 10 7 atoms / cm ^3. Is added so as to contain ¹⁷ atoms / cm ³ ,
A method for manufacturing a semiconductor device, wherein the nickel is gettered to the phosphorus added to the island-shaped silicon. After forming a nickel acetate layer on the amorphous silicon film, the amorphous silicon film is crystallized by thermal annealing to form a crystalline silicon film into which nickel has been introduced,
The crystalline silicon film in which the nickel is introduced is etched into an island shape to form an island silicon,
Forming a gate insulating film on the island-shaped silicon;
Forming a gate electrode on the gate insulating film;
By adding phosphorus to the island-shaped silicon using the gate electrode as a mask , a source region, a drain region, and a low-concentration impurity region are formed in the island-shaped silicon, and phosphorus is adjacent to the low-concentration impurity region. Forming a channel forming region not added ,
The source region and the drain region are doped so that the phosphorus is contained at 1 × 10 ²⁰ to 1 × 10 ²¹ atoms / cm ³ , and the low concentration impurity region is doped with the phosphorus at 4 × 10 ^{16 to} 7 × 10 7 atoms / cm ^3. Is added so as to contain ¹⁷ atoms / cm ³ ,
A method for manufacturing a semiconductor device, wherein the nickel is gettered to the phosphorus added to the island-shaped silicon. Etching a crystalline silicon film into which a catalytic element for promoting crystallization of silicon is introduced into an island shape to form a first island silicon and a second island silicon;
Forming a gate insulating film on the first island-shaped silicon and the second island-shaped silicon;
Forming a first gate electrode and a second gate electrode on the gate insulating film and on the first island-shaped silicon and the second island-shaped silicon, respectively;
The first island-like silicon and the second island-like silicon are doped by adding phosphorus to the first island-like silicon and the second island-like silicon using the first gate electrode and the second gate electrode as a mask . Forming a source region, a drain region, and a low-concentration impurity region in each of the island-shaped silicon, and forming a channel formation region adjacent to the low-concentration impurity region to which phosphorus is not added ;
With the first gate electrode and the first island-shaped silicon covered with a resist mask, the source region, the drain region, and the low-concentration impurity of the second island-shaped silicon are formed using the second gate electrode as a mask. Adding boron to the area ,
Removing the resist mask,
The source region and the drain region of each of the first island-shaped silicon and the second island-shaped silicon are doped with the phosphorus so as to contain 1 × 10 ²⁰ to 1 × 10 ²¹ atoms / cm ³ , Is added to the low-concentration impurity regions of each of the island-shaped silicon and the second island-shaped silicon so that the phosphorus is contained at 4 × 10 ^{16 to} 7 × 10 ¹⁷ atoms / cm ³ ,
A method for manufacturing a semiconductor device, wherein a catalytic element for promoting crystallization of silicon is gettered to the phosphorus added to the first island-shaped silicon and the second island-shaped silicon. Etching the crystalline silicon film into which nickel has been introduced into an island shape to form a first island silicon and a second island silicon;
Forming a gate insulating film on the first island-shaped silicon and the second island-shaped silicon;
Forming a first gate electrode and a second gate electrode on the gate insulating film and on the first island-like silicon and the second island-like silicon, respectively;
The first island-like silicon and the second island-like silicon are doped by adding phosphorus to the first island-like silicon and the second island-like silicon using the first gate electrode and the second gate electrode as a mask . Forming a source region, a drain region, and a low-concentration impurity region in each of the island-shaped silicon, and forming a channel formation region adjacent to the low-concentration impurity region to which phosphorus is not added ;
With the first gate electrode and the first island-shaped silicon covered with a resist mask, the source region, the drain region, and the low-concentration impurity of the second island-shaped silicon are formed using the second gate electrode as a mask. Adding boron to the area ,
Removing the resist mask,
The source region and the drain region of each of the first island-shaped silicon and the second island-shaped silicon are doped with the phosphorus so as to contain 1 × 10 ²⁰ to 1 × 10 ²¹ atoms / cm ³ , Is added to the low-concentration impurity regions of each of the island-shaped silicon and the second island-shaped silicon so that the phosphorus is contained at 4 × 10 ^{16 to} 7 × 10 ¹⁷ atoms / cm ³ ,
A method for manufacturing a semiconductor device, wherein the nickel is gettered by the phosphorus added to the first island-shaped silicon and the second island-shaped silicon. After forming a layer containing nickel on the amorphous silicon film, the amorphous silicon film is crystallized by thermal annealing to form a crystalline silicon film in which nickel is introduced,
Etching the crystalline silicon film introduced with nickel into islands to form first island-like silicon and second island-like silicon;
Forming a gate insulating film on the first island-shaped silicon and the second island-shaped silicon;
Forming a first gate electrode and a second gate electrode on the gate insulating film and on the first island-shaped silicon and the second island-shaped silicon, respectively;
The first island-like silicon and the second island-like silicon are doped by adding phosphorus to the first island-like silicon and the second island-like silicon using the first gate electrode and the second gate electrode as a mask . Forming a source region, a drain region, and a low-concentration impurity region in each of the island-shaped silicon, and forming a channel formation region adjacent to the low-concentration impurity region to which phosphorus is not added ;
With the first gate electrode and the first island-shaped silicon covered with a resist mask, the source region, the drain region, and the low-concentration impurity of the second island-shaped silicon are formed using the second gate electrode as a mask. Adding boron to the area ,
Removing the resist mask,
Wherein the first island-shaped silicon and the second island-shaped silicon respective source and drain regions are added such that the phosphorus contained 1 × 10 ²⁰ ~1 × 10 ²¹ atoms / cm ^3, the first Is added to the low-concentration impurity regions of each of the island-shaped silicon and the second island-shaped silicon so that the phosphorus is contained at 4 × 10 ^{16 to} 7 × 10 ¹⁷ atoms / cm ³ ,
A method for manufacturing a semiconductor device, wherein the nickel is gettered by the phosphorus added to the first island-shaped silicon and the second island-shaped silicon.

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