JP3535465B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [0001] The present invention relates to a non-single-crystal semiconductor thin film.
Having thin film transistor (TFT) and manufacturing method thereof
It is about. The thin film formed by the present invention
The transistor is made of single-crystal silicon on an insulating substrate such as glass.
Etc. are formed on any semiconductor substrate. In particular, the invention
Is produced through crystallization and activation by thermal annealing
It relates to a thin film transistor. [0002] 2. Description of the Related Art Recently, a thin active layer is formed on an insulating substrate.
Insulating gate type semiconductor device having an active region
Has been studied. In particular, a thin insulating gate
The transistor, the so-called thin film transistor (TFT), is heated
Researched in mind. These are the semiconductor materials used
-Depending on the crystal state, amorphous silicon TFTs and
It is distinguished as a crystalline silicon TFT. crystal
Silicon is not a single crystal, but a non-single crystal
It is. In general, the electric field transfer of a semiconductor in an amorphous state
Mobility is small, and therefore TF for which high-speed operation is required
Not available for T. Also, with amorphous silicon
Indicates that the P-type electric field mobility is extremely small,
Type TFT (PMOS TFT)
Therefore, an N-channel TFT (NMOS TF)
T) and complementary MOS circuit (CMOS)
Cannot be formed. On the other hand, crystalline semiconductors are amorphous semiconductors.
Electric field mobility and therefore high-speed operation
Noh. In crystalline silicon, only NMOS TFT
Instead, a PMOS TFT can be obtained in the same
It is possible to form an S circuit. Also, better features
In order to obtain the property, it is done with MOSIC of single crystal semiconductor
It is necessary to provide an LDD (low concentration drain) structure
Are preferred. [0005] SUMMARY OF THE INVENTION To obtain an LDD structure
Requires the following process:   Formation of island-shaped semiconductor region and gate insulating film   Formation of gate electrode   Introduction of low concentration impurities (ion implantation or ion implantation
Doping method)   LDD region mask formation (insulation covering gate electrode)
Anisotropic etching of film or anodic oxidation of gate electrode
By selective oxidation of   Introduction of high concentration impurities (ion implantation or ion implantation
Doping method)   Activation of impurities (laser annealing or thermal annealing)
According to the rules) The biggest problem with these processes is that
It is a process of. What is laser annealing?
Irradiates an equivalent strong light
This is a method of activating silicon,
Due to force instability or very short process times
There is no prospect of mass production due to the coming instability
No. In addition, laser light is irradiated from above the gate electrode
Therefore, the LDD region is blocked by the mask formed in the step
Therefore, sufficient activation cannot be expected. At present, those who can be practically employed
The method is to activate impurities in silicon by heat.
Is the law. In this method, the LDD region is sufficiently activated.
And there is little variation between batches. However, usually
In order to activate the impurities in the recon film,
Prolonged annealing at temperature or above 1000 ° C
High temperature annealing was required. Adopt the latter method
In this case, the substrate that can be selected is limited to quartz, and
Always higher. With the former method, there is more room for substrate selection.
However, if an inexpensive substrate is used, the substrate during thermal annealing can be used.
Shrinkage etc. become a problem, and the yield due to mask alignment failure etc.
And treatment at lower temperatures is required.
You. Specifically, various alkali-free substrates used as substrates
Below the glass distortion temperature (preferably from the glass distortion temperature
Temperature lower than 50 ° C).
You. The present invention provides an answer to such a difficult task.
It is something to do. [0008] As a result of the research by the present inventors,
Trace amount of catalyst on silicon film in amorphous state
Addition of elements promotes crystallization,
Clearly lower temperature and shorter crystallization time
Became. Nickel (Ni), iron
(Fe), cobalt (Co), platinum (Pt) are preferred
No. Specifically, these catalyst elements alone or
Compound film such as silicide on amorphous silicon
Or by an ion implantation method or the like.
These catalytic elements are introduced into the fac silicon film,
Later, this is brought to a suitable temperature, typically a temperature of 580 ° C. or less.
Can be crystallized by thermal annealing
You. As a matter of course, the annealing temperature is high.
The shorter the crystallization time, the shorter the crystallization time. Also, Nicke
The higher the concentration of iron, cobalt, platinum, the higher the crystallization temperature
And the crystallization time is short. The inventor
Research has shown that to promote crystallization,
The concentration of at least one element is 1 × 10¹⁵cm^-3that's all,
Preferably 5 × 10¹⁸cm^-3Must exist
I found it. On the other hand, all of the above catalyst materials are converted to silicon.
It is an undesirable material, so
It is desired that the concentration be low. In our study, this
The total concentration of these catalyst materials was 2 × 10¹⁹cm^-3Beyond
It is hoped that there is no. The present inventor pays attention to the effect of this catalytic element.
And use it to solve the above problem.
I found that. That is, in the present invention,
These catalyst elements become amorphous by introducing impurities.
Crystallization temperature by introducing into the silicon
Of the doping impurities (recrystallization)
Decrease temperature. In particular, according to the research by the present inventors,
Uniform from the beginning by ion implantation or ion doping
Extremely high crystallization when catalyst elements are distributed
It was easy. Typically, temperatures below 550 ° C are sufficient
Crystallization and activation are possible, and annealing time is 8
It has been found that an hour, typically four hours, is sufficient.
won. In the conventional crystallization by thermal annealing,
Difficult to crystallize silicon films below 1000Å
However, in the present invention, it is very easy
Crystallization could be performed at a lower temperature and in a shorter time. 10
TFT with thin active area of less than 00Å, especially less than 500Å
Is not only excellent in characteristics, but also gate
Less defects at steps of insulating film and gate electrode, yield
Had the advantage of being high. However, conventionally
Because of the difficulty of crystallization, laser
There was no production method other than crystallization with a tool. Book
The invention was monopolized by laser annealing until then
Technology areas can be implemented by thermal annealing.
Breakthrough in the sense that the yield can be improved for the reasons mentioned
It is something. The present invention will be described in more detail using the following examples.
Explain the light. [0013] [Embodiment 1] FIG. 1 shows the manufacturing process of this embodiment.
FIG. First, the substrate (Corning 7059) 10
2000 mm thick silicon oxide by sputtering
An elementary base film 11 was formed. Furthermore, a plasma CVD method
Depending on the thickness, for example, 500-1500 °, for example, 1500 °
Intrinsic (I-type) amorphous silicon film 12
And a 200 Å thick acid by sputtering.
A silicon oxide film 13 was deposited. And this silicon film
Nickel ions were implanted by an ON implantation method. Do
Size is 2 × 10¹³~ 2 × 10¹⁴cm^-2, For example, 5 × 10
¹³cm^-2And As a result, the amorphous silicon film 1
The nickel concentration of 2 was 5 × 10¹⁸cm ^-3About
Was. This step involves depositing a nickel silicide film between 5 and 100 degrees.
Can also be substituted. However, in that case, oxidation
It is desirable not to have the silicon film 13. (Fig. 1 (A)) Then, this amorphous silicon film is nitrided.
Crystallize by annealing at 550 ° C for 4 hours in elementary atmosphere
Was. After annealing, pattern the silicon film to form an island
Form silicon region 12a, and then sputter
Gate of silicon oxide film 14 with a thickness of 1000 mm
Deposited as an edge film. Sputtering target
The substrate temperature during sputtering is
200 to 400 ° C, for example 250 ° C, sputtering atmosphere
The atmosphere is oxygen and argon, and argon / oxygen = 0 to 0.1.
5, for example, 0.1 or less. Subsequently, the thickness is reduced by a low pressure CVD method.
3000-8000Å, for example, 6000Å silicon film
(Containing 0.1-2% phosphorous). This acid
The silicon oxide and silicon film deposition process must be performed continuously.
Is desirable. And pattern the silicon film,
The gate electrode 15 was formed. (FIG. 1 (B)) Next, the plasma doping method is used to
Impurity (phosphorus) is implanted in the recon region using the gate electrode as a mask.
Injected. Phosphine (PH) as doping gas
_Three), And the acceleration voltage is 60 to 90 kV, for example, 80 kV.
V. Dose amount is 1 × 10¹³~ 8 × 10¹³cm^-2,
For example, 2 × 10¹³cm^-2And As a result, the N-type low
Concentration impurity regions 16a and 16b were formed. (Figure 1
(C)) Subsequently, the substrate was placed in a citric acid solution (1 to 5%).
Immersed in the electrode and pass a current through the gate electrode.
An anodic oxide layer 17 was grown on the surface. Anodic oxide thickness
Is 1000-5000５, especially 2000-3000Å
I liked it. Here, it was 2500 °. And re
The silicon region by plasma doping.
Impurities using the anode electrode and the surrounding anodic oxide as a mask
(Phosphorus) was injected. Phosphine as doping gas
(PH_Three), The acceleration voltage is 60 to 90 kV, for example.
For example, it was set to 80 kV. Dose amount is 1 × 10¹⁵~ 8 × 10¹⁵
cm^-2, For example, 2 × 10¹⁵cm^-2And As a result,
N-type high-concentration impurity regions 18a and 18b were formed.
Also, the anodic oxide is used as a mask and partially formed first
The low-concentration impurity region (LDD) thus left remains. (Figure 1
(D)) Thereafter, in a nitrogen atmosphere at 500 ° C. for 4 hours.
The impurities were activated by annealing. This
The activation temperature is expected to be lower than the previous crystallization temperature.
Good. This is to minimize the shrinkage of the substrate.
You. At this time, nickel is distributed in the silicon film.
Easy recrystallization despite low temperature annealing
Advanced. Thus, impurity regions 16a, 16b and 1
8a and 18b could be activated. Things to note here
This activation process is due to thermal annealing,
In the laser annealing method, sufficient activation was impossible.
DD is also activated. In addition, impurity regions and active
The crystallinity of the active region was also continuous. Subsequently, a silicon oxide film 19 having a thickness of 6000.degree.
Is formed as an interlayer insulator by a plasma CVD method,
A contact hole is formed in this, and a metal material, such as
For example, a TFT with a multilayer film of titanium nitride and aluminum
To form electrodes / wirings 20 of the source region and the drain region
Was. Finally, in a hydrogen atmosphere of 1 atm.
Annealing was performed. Through the above steps, the thin film transformer
The Vista is completed. (FIG. 1E) Secondary ion mass spectrometry
(SIMS) method to determine the concentration of nickel
Of course, both the impurity region and the active region of the TFT are 1 × 10¹⁸~
5 × 10¹⁸cm^-3At a concentration of. [Embodiment 2] FIG. 2 shows a manufacturing process of this embodiment.
FIG. First, the substrate (Corning 7059) 2
Oxidation of 2000mm thick by sputtering method on 1
A silicon base film 22 was formed. Furthermore, plasma CVD
Depending on the method, the thickness is 500-1500 °, for example 500 °
An intrinsic (I-type) amorphous silicon film was deposited.
This silicon film is patterned to form an island-shaped silicon
A con film 23 was formed. Further, tetraethoxysilane (Si)
(OC_TwoH_Five)_Four, TEOS) and oxygen as raw materials
Gate isolation of crystalline silicon TFT by plasma CVD
A silicon oxide 24 having a thickness of 1000 ° is formed as an edge film.
Was. In addition to the above gases, trichloroethylene
(C_TwoHCl_Three) Was used. Oxygen in chamber before film formation
Flow at 400 SCCM, substrate temperature 300 ° C, total pressure 5P
a, A plasma is generated at an RF power of 150 W
I kept it for 10 minutes. Then, oxygen 300S in the chamber
15CMCM for CCM and TEOS, Trichlorethylene
Was introduced into 2SCCM to form a silicon oxide film.
Was. The substrate temperature, RF power and total pressure are 300
° C, 75W, and 5Pa. After film formation is completed, the chamber
100 Torr of hydrogen is introduced into the reactor at 350 ° C. for 35 minutes.
Hydrogen annealing was performed. Subsequently, by a sputtering method,
Tanta with a thickness of 3000-8000Å, for example, 6000Å
Film was deposited. Titanium or tangs instead of tantalum
Tens, molybdenum and silicon may be used. However, later activity
It is necessary to have heat resistance enough to withstand the change. Note that this
The process of forming the silicon oxide 24 and the tantalum film is performed continuously.
Is desirable. And pattern the tantalum film
Thus, a gate electrode 26 of the TFT was formed. Gate electrode
(= Channel length) was 5 to 20 μm. (FIG. 2
(A)) Next, the amorphous silicon is formed by ion implantation.
Impurities in the silicon region using the gate electrode as a mask
(Phosphorus) was injected. The acceleration voltage was 80 kV. Dose
The quantity is 2 × 10¹³cm^-2And As a result, the low concentration of N-type
Impurity regions 26a and 26b were formed. (FIG. 2
(B)) Subsequently, a gate electrode is formed by ion implantation.
Nickel was injected using the pole as a mask. The dose is 2 ×
10¹³~ 2 × 10¹⁴cm^-2, For example, 1 × 10¹⁴cm^-2When
did. As a result, the nip of the amorphous silicon region 23 is reduced.
The concentration of Kel is 1 × 10 ¹⁹cm^-3It was about. (FIG. 2
(C)) Next, the surface of the tantalum wiring is anodized.
Thus, an oxide layer 27 was formed on the surface. Anodizing is sake
Performed in 1-5% ethylene glycol solution of folic acid
Was. The thickness of the obtained oxide layer was 2000 °. So
And again mask the gate electrode by ion implantation.
As an impurity (phosphorus). The acceleration voltage is 80 kV
And the dose is 2 × 10¹⁵cm^-2And As a result, N
Mold high-concentration impurity regions 28a and 28b were formed.
(FIG. 2 (D)) Then, at 500 ° C. for 4 hours in a nitrogen atmosphere.
By annealing, the amorphous silicon film
Crystallization and impurity activation were performed. At this time,
N-type impurity regions 28a, 28b and 26a and 26
Since nickel is implanted in b,
Thus, activation proceeded easily. On the other hand, below the gate electrode
Nickel was not implanted in the active region of
Crystallization due to diffusion of nickel from region 26
Has progressed. Completely crystalline with a channel length of 10 μm or less
Could be transformed. But with longer channel lengths
Was difficult to completely crystallize. But ani
When the rule temperature is 550 ° C, the channel of 20 μm
Crystallization of the active region was observed even with a long one. like this
Raise the annealing temperature to promote efficient lateral crystallization.
Or increase the annealing time.
Was. Subsequently, as an interlayer insulator, a thickness of 2000
Plasma silicon oxide film 29 made of TEOS as a raw material
The contact hole is formed in this by the D method.
Metal materials, such as titanium nitride and aluminum.
The source / drain electrode / wiring 30 is formed by the layer film.
Was. The semiconductor circuit was completed by the above steps. (FIG. 2
(E)) Field effect transfer of the fabricated thin film transistor
Mobility is 70-100cm at a gate voltage of 10V^Two/ V
s, the threshold is 2.5-4.0V, and the gate is -20V.
Leakage current when voltage is applied is 10^-13A or less
Was. [0028] According to the present invention, for example, a temperature of 500 to 550 ° C.
Amorph in such a low temperature and as short as 4 hours
Crystallization of base silicon film and doping in silicon
By activating impurities, throughput is improved.
Can be improved. In addition, conventionally,
When the above process is adopted, the shrinkage of the glass substrate
Although this was a problem as a cause of reduced retention, the present invention
Can be used to solve such problems at once.
Was. This means that a large area substrate can be processed at once.
It means that you can. That is, large area substrate
By processing many semiconductors from one substrate
Unit price by starting circuit (matrix circuit etc.)
Can be greatly reduced. This is the liquid crystal display
When applied to ray, the improvement of mass productivity and improvement of characteristics
It is planned. In this specification, two examples are shown.
However, especially in the process of Example 2, the amorphous
Simultaneous crystallization of silicon film and activation of impurities
It is noted that. Conventionally, as shown in the first embodiment,
After crystallization, it is common to activate by introducing impurities.
It was through. However, in such a method, the process is heavy.
Active area formed by initial crystallization
And the source and drain that are recrystallized after impurity introduction
Discontinuity in crystal growth, which may adversely affect reliability.
I did it. As in Example 2, crystallization and activation occur simultaneously
What is done is to simplify the process (and
Increased throughput) and continuity of crystallinity
This has the effect of improving the performance. Thus, the present invention
This is an industrially useful invention.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a cross-sectional view showing a manufacturing step in Example 1. FIG. 2 shows a cross-sectional view of a manufacturing process in Example 2. DESCRIPTION OF SYMBOLS 10 ... substrate 11 ... base insulating film (silicon oxide) 12 ... amorphous silicon film 13 ... silicon oxide film 12a ... island-shaped silicon region 14 ... gate insulating film ( 15 ... Gate electrode (phosphorus-doped silicon) 16 ... Low-concentration impurity region (LDD) 17 ... Anodic oxide (silicon oxide) 18 ... Source, drain 19 ... Interlayer Insulator (silicon oxide) 20 ... Metal wiring / electrode (titanium nitride / aluminum)

────────────────────────────────────────────────── ─── front page continued (51) Int.Cl. ⁷ identifications FI H01L 21/265 P (56) references Patent Rights 6-333951 (JP, a) Patent Rights 5-55581 (JP, a) JP-A-4-11226 (JP, A) JP-A-4-340725 (JP, A) JP-A-5-67635 (JP, A) JP-A-3-218073 (JP, A) JP-A-4-360580 (JP, A) JP-A-2-84775 (JP, A) C.I. Hayzelden. J. L. Batstone, R.A. C. Camm arata, In situ tran emission election microscopy studies of silicide-media ted crystallizatio n of amorphous s, Appl. Phys. Lett. , January 13, 1992, Vol. 60 No. 2, p. 225-227 (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 29/736 H01L 21/20 H01L 21/336

Claims (1)

(57) [Claims 1 to form an amorphous silicon film on an insulating substrate, and patterning the amorphous silicon film into a plurality of island-like silicon region, a gate insulating film on the island silicon region on Forming a gate having a width of 5 to 20 μm on the gate insulating film
An electrode is formed , an impurity is introduced into the island-shaped silicon region at a first dose using the gate electrode as a mask , and the island-shaped silicon region is implanted using the gate electrode as a mask.
Promotes the crystallization of ionized silicon in the region
After forming an insulating film covering the gate electrode by introducing
Forming a mask of the LDD region by etching, and using the gate electrode and the mask of the LDD region,
In larger second dose than the first dose, to introduce the same conductivity type impurity and the <br/> impurities, by a pre Kishimajo silicon region is thermally annealed, activation and crystallization
A method for manufacturing a semiconductor device.