JP3369244B2 - Thin film transistor - Google Patents

Description

Detailed Description of the Invention

[0001]

The present invention relates to a thin film transistor (T
FT) and its manufacturing method. The thin film transistor manufactured by the present invention is formed on either an insulating substrate such as glass or a semiconductor substrate such as single crystal silicon. In particular, the present invention relates to a thin film transistor manufactured through crystallization and activation by thermal annealing.

[0002]

2. Description of the Related Art Recently, research has been conducted on an insulating gate type semiconductor device having a thin film active layer (also called an active region) on an insulating substrate. In particular, thin-film insulating gate transistors, so-called thin film transistors (TFTs), have been eagerly studied. These are intended to be used for controlling each pixel in a display device such as a liquid crystal having a matrix structure formed on a transparent insulating substrate and for a driving circuit. Amorphous silicon TFTs and crystalline silicon TFTs are distinguished by the crystalline state.

Generally, the electric field mobility of a semiconductor in an amorphous state is small, and therefore TF which requires high speed operation.
Not available for T. Further, in amorphous silicon, since the P-type electric field mobility is extremely small, a P-channel type TFT (PMOS TFT) cannot be manufactured. Therefore, an N-channel type TFT (NMOS TF) is not produced.
T) combined with complementary MOS circuit (CMOS)
Cannot be formed.

On the other hand, a crystalline semiconductor has a larger electric field mobility than an amorphous semiconductor, and therefore can operate at high speed. With crystalline silicon, not only NMOS TFTs but also PMOS TFTs can be obtained, so CMO
An S circuit can be formed. For example, in an active matrix type liquid crystal display device, a so-called monolithic structure is formed in which not only the active matrix portion but also peripheral circuits (drivers and the like) are composed of CMOS crystalline TFTs. Those who have are known. For these reasons, research and development of TFTs using crystalline silicon have recently been actively conducted.

[0005]

As one of methods for obtaining crystalline silicon, there is a method of crystallizing amorphous silicon by irradiating a laser or strong light equivalent thereto, but the instability of the laser output is mentioned. Due to instability resulting from the extremely short process, there is no prospect for mass production.

[0006] Methods currently considered practically be employed is a method of crystallizing amorphous silicon by heat. With this method, it is possible to obtain crystalline silicon with little variation between batches. But it's not without problems.

Usually, 600 ° C. is required to obtain crystalline silicon.
Long annealing at moderate temperature or 1000
Annealing at high temperature above ℃ was required. If the latter method is adopted, the substrate that can be selected is limited to quartz, and the substrate cost becomes very high. The former method expands the choice of substrates, but has another problem.

The conventional TFT manufacturing process when an inexpensive alkali-free glass substrate (Corning 7059, etc.) is used is generally as follows. (1) Formation of amorphous silicon film (2) Crystallization of amorphous silicon film (600 ° C. or higher, 24 hours or longer) (3) Gate insulating film formation (4) Gate electrode formation (5) Doping impurity introduction (By ion implantation or ion doping method) (6) Activation of doping impurities (600 ° C. or higher, 24
(More than time) (7) Formation of interlayer insulator (8) Formation of source and drain electrodes

Here, the problems (2) and (6) are particularly problematic. The strain temperature of many alkali-free glasses is around 600 ° C (5 for Corning 7059).
Since the temperature is 93 ° C.), the treatment at such a temperature causes a problem of chipping and warping of the substrate. At the stage (2), which is the first annealing process, the patterning is not yet performed, so the shrinkage of the substrate is not a big problem. However, at the stage of (6), since the circuit is patterned, the contraction of the substrate makes it impossible to perform mask alignment thereafter, which is a major cause of a decrease in yield. Therefore, it is desired that the process temperature of (2) is performed at a strain temperature of the substrate or lower, while the process of (6) is performed at a lower temperature (preferably a temperature lower than the strain temperature of glass by 50 ° C. or more, more preferably, It is desired that the temperature be 50 ° C. or more lower than the maximum heat treatment temperature of 2).

For that purpose, for example, a method using a laser as described above may be considered, but in addition to the instability of the laser, a portion irradiated with the laser (source and drain regions) and a portion not irradiated with the laser ( Active area =
It was observed that stress was generated due to the difference in temperature rise between the gate electrode and the area below the gate electrode), resulting in a decrease in reliability.

Therefore, it is difficult to use a laser or the like in mass production. On the other hand, it was the current situation that no effective method could be found as another method. The present invention is intended to provide an answer to such a difficult task. An object of the present invention is to solve the above problems while maintaining mass productivity.

[0012]

As a result of the research conducted by the present inventor,
It has been revealed that the addition of a trace amount of a catalyst material to the substantially amorphous silicon coating can promote crystallization, lower the crystallization temperature, and shorten the crystallization time. Suitable catalyst materials are simple substances of nickel (Ni), iron (Fe), cobalt (Co), platinum (Pt), or compounds thereof such as silicides. Specifically, a film, particles, clusters or the like having these catalytic elements are formed in close contact with each other under or on the amorphous silicon film, or these catalytic elements are formed in the amorphous silicon film by a method such as an ion implantation method. Can then be crystallized by thermal annealing at a suitable temperature, typically below 580 ° C.

As a matter of course, the higher the annealing temperature, the shorter the crystallization time. In addition, the higher the concentration of nickel, iron, cobalt, and platinum, the lower the crystallization temperature and the shorter the crystallization time. According to the research by the present inventor, in order to promote crystallization, the concentration of at least one of these elements is 1 × 10 ¹⁷ cm ⁻³ or more,
It has been found that it is necessary to preferably exist at 5 × 10 ¹⁸ cm ⁻³ or more.

On the other hand, all of the above catalyst materials are unfavorable materials for silicon, so that it is desirable that the concentration thereof be as low as possible. In the study of the present inventors, the concentration of these catalyst materials is 1 in total in order to obtain sufficient reliability and characteristics, especially when used as an active region.
It is desired not to exceed 0 ²⁰ cm ^-3 . On the other hand, the source,
It has been clarified that even if a relatively large amount is present in the drain or the like, it does not pose a problem.

The present inventor has paid attention to the effect of this catalytic element and found that the above problem can be solved by utilizing it. The manufacturing process of the TFT in the present invention is generally as follows. (1) Formation of amorphous silicon film (1) 'Introduction of catalytic element (by ion implantation or ion doping method) (2) Crystallization of amorphous silicon film (600 ° C or less, within 8 hours) (3) Gate insulating film Film formation (4) Gate electrode formation (5) Doping impurity introduction (by ion implantation or ion doping method) (5) 'Film formation of substance having catalytic element on silicon film (6) Activation of doping impurities (600 ° C or less, 8
(Within time) (7) Formation of interlayer insulator (8) Formation of source and drain electrodes

Alternatively, (1) film formation of an amorphous silicon film (1) 'introduction of catalytic element (by ion implantation or ion doping method) (2) crystallization of amorphous silicon film (600 ° C. or less, within 8 hours) ( 3) Gate insulating film formation (4) Gate electrode formation (5) Doping impurity introduction (by ion implantation or ion doping method) (5) 'Catalyst element introduction (by ion implantation or ion doping method) (6) ) Activation of doping impurities (600 ° C or lower, 8
(Within time) (7) Formation of interlayer insulator (8) Formation of source and drain electrodes

In these steps, the order of (5) and (5) 'can be reversed. Further, the step (1) ′ may be replaced with “a step of adhering a coating film or the like having a catalytic element on or under the amorphous silicon film”. Means such as an ion implantation method is desirable in the sense that the concentration of the catalyst element is precisely controlled, but from the viewpoint of simplifying the process and suppressing the equipment investment, if the characteristics of the obtained TFT permit, A process may be adopted.

In the present invention, the catalyst element introduced into the amorphous silicon film in the above step (1) 'significantly promotes its crystallization, and the catalyst element introduced mainly into the source and drain regions by (5)'. The element is
It significantly promotes recrystallization in that region. Therefore, for crystallization and activation, the temperature is 600 ° C or lower, typically 55 ° C.
Temperatures below 0 ° C are sufficient and annealing time is 8
Within hours, typically within 4 hours is sufficient. In particular,
When the catalytic element was evenly distributed from the beginning by the ion implantation method or the ion doping method, crystallization was extremely easy to proceed.

In the present invention, no matter which process is adopted, since the gate electrode is present on the active region,
In the step (5) ′, the catalytic element is not directly adhered to or injected into the active region. Therefore, it is possible to change the concentration of the catalyst element in the active region and the impurity region. For example, by making the concentration of the catalyst element added to the active region relatively small, the adverse effect on the characteristics and reliability of the TFT is minimized, and the concentration of the catalyst element added to the impurity region is made relatively large. By lowering the activation temperature, the shrinkage and warpage of the substrate can be suppressed and the yield can be increased. Further, for that reason, the reliability and characteristics of the TFT are hardly impaired.

Further, in the present invention, due to the action of the catalytic element, a thin amorphous silicon film of 100 nm or less which is not crystallized by ordinary thermal annealing is also crystallized. The thickness of the crystalline silicon film is required to be 100 nm or less, preferably 50 nm or less, from the viewpoint of preventing pinholes and insulation failure of the gate insulating film in the step portion of the TFT, and disconnection of the gate electrode. Conventionally, it could not be realized by a method other than laser crystallization, but according to the present invention, it could be realized by thermal annealing even at low temperature. It goes without saying that this contributes to further improvement in yield. Hereinafter, the present invention will be described in more detail with reference to examples.

[0021]

[Embodiment] [Embodiment 1] FIG. 1 shows a cross-sectional view of a manufacturing process of this embodiment. First, a base film 11 of silicon oxide having a thickness of 200 nm was formed on a substrate (Corning 7059) 10 by a sputtering method. Further, the thickness of 500 to
An intrinsic (I-type) amorphous silicon film 12 of 150 nm , for example 150 nm , was deposited. Then, 1 × 10 ^{13 is formed in the} amorphous silicon film by an ion implantation method.
Nickel ions were implanted at a dose of ˜5 × 10 ¹⁴ cm ⁻² , for example 5 × 10 ¹³ cm ⁻² . As a result, nickel was present in the amorphous silicon film at a concentration of about 5 × 10 ¹⁸ cm ⁻³ . (Fig. 1 (A))

This was crystallized by annealing at 550 ° C. for 4 hours in a nitrogen atmosphere. After the annealing, the silicon film was patterned to form the island-shaped silicon region 13, and the silicon oxide film 14 having a thickness of 100 nm was deposited as the gate insulating film by the sputtering method. For sputtering, silicon oxide is used as a target, and the substrate temperature during sputtering is 200 to 400 ° C., for example 250.
The sputtering atmosphere was oxygen and argon, and argon / oxygen was 0 to 0.5, for example, 0.1 or less.

Subsequently, a silicon film (containing phosphorus of 0.1 to 2%) having a thickness of 300 to 800 nm , for example 600 nm , was deposited by the low pressure CVD method. It is desirable that the steps of forming the silicon oxide and the silicon film are continuously performed. Then, pattern the silicon film,
The gate electrode 15 was formed. (Fig. 1 (B))

Next, impurities (phosphorus) were implanted into the silicon region by plasma doping using the gate electrode as a mask. As doping gas, phosphine (PH
₃ ) is used and the acceleration voltage is 60 to 90 kV, for example 80 kV.
It was set to V. The dose is 1 × 10 ¹⁵ to 8 × 10 ¹⁵ cm ^-2 ,
For example, it is set to 2 × 10 ¹⁵ cm ⁻² . As a result, N type impurity regions 16a and 16b were formed. (Fig. 1 (C))

Next, the silicon oxide film 14 on the impurity region is etched to expose the impurity region 16, and a nickel silicide film (0.5 nm to 20 nm in average thickness, for example, 2 nm) is formed by a sputtering method. Chemical formula NiSi _x , 0.4
≦ x ≦ 2.5, for example, x = 2.0) 17 was formed on the entire surface as shown in the figure. At a thickness of about 2 nm , the film was not continuous, and rather appeared as an aggregate of particles, but there is no problem in this example. (Fig. 1
(D))

After that, the impurities were activated by annealing in a nitrogen atmosphere at 480 ° C. (70 ° C. lower than the annealing temperature in the previous crystallization) for 4 hours. At this time, since nickel diffuses into the N-type impurity regions 16a and 16b from the nickel silicide film deposited thereon, recrystallization easily proceeds by this annealing.
Thus, the impurity regions 16a and 16b are activated.

Then, a silicon oxide film 18 having a thickness of 600 nm is formed.
Is formed by plasma CVD as an interlayer insulator,
A contact hole is formed in this, and a TFT is formed by a metal material, for example, a multilayer film of titanium nitride and aluminum
Source / drain region electrodes / wirings 19a, 19
b was formed. Finally, in a hydrogen atmosphere at 1 atm, 350
Annealing was performed at 30 ° C. for 30 minutes. The thin film transistor was completed through the above steps. (Fig. 1 (E))

The concentration of nickel in the active region (under the gate electrode) of the obtained TFT was analyzed by the secondary ion mass spectrometry (SIMS) method to be 1 × 10 ¹⁸ to
It was about 5 × 10 ¹⁸ cm ⁻³ , and the concentration in the impurity region 16 was about 1 × 10 ^{19 to} 5 × 10 ¹⁹ cm ⁻³ .

[Embodiment 2] FIG. 2 shows a cross-sectional view of a manufacturing process of this embodiment. First, the substrate (Corning 7059) 2
An underlayer film 21 of silicon oxide having a thickness of 200 nm was formed on the substrate 0 by sputtering. Furthermore, plasma CVD
Depending on the method, the thickness is 50 to 150 nm , for example 150 nm
Then, an intrinsic (I-type) amorphous silicon film 22 and a silicon oxide film 23 having a thickness of 20 nm were deposited by the sputtering method. Then, nickel ions were implanted into this amorphous silicon film by an ion implantation method at a dose amount of 5 × 10 ¹³ cm ⁻² . (FIG. 2 (A)) Next, this amorphous silicon film is exposed to 550 ° C. in a nitrogen atmosphere.
It was annealed for 8 hours to be crystallized. Then, this silicon film was patterned to form island-shaped silicon regions 24.

Furthermore, tetra-ethoxy-silane (Si
A silicon oxide film 25 having a thickness of 100 nm was formed as a gate insulating film of a crystalline silicon TFT by plasma CVD using (OC ₂ H ₅ ) ₄ , TEOS) and oxygen as raw materials. As the raw material, trichlorethylene (C ₂ HCl ₃ ) was used in addition to the above gas. Oxygen 400SCCM flow into the chamber before film formation, substrate temperature 300 ° C, total pressure 5P
a, plasma was generated with an RF power of 150 W, and this state was maintained for 10 minutes. After that, 300S oxygen is added to the chamber.
A silicon oxide film was formed by introducing 15 SCCM of CCM and TEOS and 2 SCCM of trichloroethylene. The substrate temperature, RF power, and total pressure are each 300
C., 75 W, 5 Pa. After the film formation was completed, 100 Torr of hydrogen was introduced into the chamber, and hydrogen annealing was performed at 350 ° C. for 35 minutes.

Subsequently, by the sputtering method,
A tantalum film having a thickness of 300 to 800 nm , for example 600 nm , was deposited. Instead of tantalum, titanium, tungsten, molybdenum, or silicon may be used. However, the heat resistance is required to withstand the subsequent activation. It is desirable that the steps of forming the silicon oxide film 25 and the tantalum film be continuously performed. Then, the tantalum film was patterned to form the gate electrode 26 of the TFT. Further, the surface of this tantalum wiring is anodized to form an oxide layer 2 on the surface.
Formed 7. Anodization was performed in a 1-5% ethylene glycol solution of tartaric acid. The thickness of the obtained oxide layer was 200 nm . (Fig. 2 (B))

Next, impurities (phosphorus) were implanted into the silicon region by plasma doping using the gate electrode as a mask. As doping gas, phosphine (PH
₃ ) was used and the acceleration voltage was set to 80 kV. Dose amount is 2
It was set to × 10 ¹⁵ cm ^-2 . As a result, the N-type impurity region 2
8a and 28b were formed. At this time, due to the anodic oxide, the gate electrode 26 and the impurity region 28 are in an offset state. (Fig. 2 (C))

Further, this time, nickel ions are implanted into the silicon region by ion implantation using the gate electrode as a mask. The dose is 1 × 10 ¹⁴ to 2 × 10 ¹⁵ cm ^-2 ,
For example, it is set to 5 × 10 ¹⁴ cm ⁻² . As a result, the concentration of nickel in the N type impurity regions 28a and 28b is 5 × 10 ^19.
It became about cm ^-3 . (Fig. 2 (D))

Then, the impurities were activated by annealing at 450 ° C. for 4 hours in a nitrogen atmosphere. At this time, since nickel ions were implanted in the N-type impurity regions 28a and 28b, recrystallization was easily promoted by this annealing. Thus, the impurity region 28
a and 28b were activated.

Then, as an interlayer insulator, the thickness is 200 nm.
CV using TEOS as the raw material for the silicon oxide film 29 of
D method is used to form contact holes therein, and the source / drain electrodes / wirings 30a, 30 are made of a metal material such as a multilayer film of titanium nitride and aluminum.
b was formed. The semiconductor circuit is completed through the above steps. (Fig. 2 (E))

The field effect mobility of the manufactured thin film transistor is 70 to 100 cm ² / V at a gate voltage of 10V.
s, the threshold value was 2.5 to 4.0 V, and the leak current when a voltage of -20 V was applied to the gate was 10 ^-13 A or less.

[0037]

INDUSTRIAL APPLICABILITY The present invention improves throughput by crystallization of amorphous silicon and activation of doping impurities in silicon at a low temperature of 400 to 550 ° C. and a short time of 4 hours. Can be made. In addition, conventionally, when a process of 600 ° C. or higher is adopted, shrinkage of the glass substrate has been a cause of a decrease in yield, but by using the present invention, such a problem can be solved at once. .

This means that a large area substrate can be processed at one time. That is, by processing a large-area substrate, a large number of semiconductor circuits (matrix circuits, etc.) can be cut out from one substrate, and the unit price can be significantly reduced. When this is applied to a liquid crystal display, mass productivity and characteristics can be improved. Thus, the present invention is an industrially useful invention.

[Brief description of drawings]

1A to 1C are cross-sectional views of a manufacturing process of Example 1.

2A to 2C are cross-sectional views of a manufacturing process of Example 2.

[Explanation of symbols]

10 ... Substrate 11 ... Base insulating film (silicon oxide) 12 ... Amorphous silicon film 13 ... Island silicon region 14 ... Gate insulating film (silicon oxide) 15 ... Gate electrode (phosphorus) Doped silicon 16 ... Source / drain regions 17 ... Catalytic element-containing coating (nickel silicide) 18 ... Interlayer insulator (silicon oxide) 19 ... Metal wiring / electrode (titanium nitride / aluminum)

─────────────────────────────────────────────────── ─── Continuation of front page (56) References JP-A-63-56912 (JP, A) JP-A-2-140915 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 29/786 H01L 21/20 H01L 21/265 H01L 21/336

Claims (7)

(57) [Claims] 1. In a thin film transistor having a crystalline silicon film formed on a substrate, an active region, and an impurity region adjacent to the active region, a metal element for promoting crystallization of amorphous silicon in the impurity region. Is higher than that in the active region, and the concentration of the metal element in the active region is 1 × 10 ¹⁷ to 1 × 1.
A thin film transistor having a ^thickness of 0 ²⁰ cm ^-3 . 2. A thin film transistor, comprising: a crystalline silicon film formed on a substrate; an active region; an impurity region adjacent to the active region; and a gate electrode formed on the active region. The concentration of the metal element that promotes crystallization of amorphous silicon in the region is higher than that in the active region, and the concentration of the metal element in the active region is 1 × 10 ¹⁷ to 1 × 1.
0 ²⁰ cm ⁻³ , wherein the metal element in the impurity region is introduced using the gate electrode as a mask. 3. A crystalline silicon film formed on a substrate, comprising a source region, a drain region, an active region between the source region and the drain region, and an active region between the active region and the source region. And a offset region between the active region and the drain region, wherein the concentration of the metal element that promotes crystallization of the amorphous silicon in the impurity region is the active region and the offset region.
Higher than the area , and the active area and the offset area
The concentration of the metal element in the region is 1 × 10 ¹⁷ to 1 × 10 ²⁰ c
A thin film transistor characterized by being m ⁻³ . 4. A any one of claims 1 to 3, a metal element that promotes crystallization of the amorphous silicon thin film transistor, wherein the nickel, iron, the cobalt or platinum. 5. A any one of claims 1 to 4, the concentration of the metal element for promoting the crystallization of the amorphous silicon may be equal to a value measured by secondary ion mass spectrometry TFT. 6. A liquid crystal display device characterized by using a thin film transistor according to any one of claims 1 to 5. 7. A semiconductor circuit, characterized in that using a thin film transistor according to any one of claims 1 to 5.