JP2000269502A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To accelerate crystallization, lower crystallization temperatures, and shorten a crystallization time by a method wherein a fine amount of catalytic material is added to a silicon film in a substantially amorphous state so as not to exceed a predetermined concentration. SOLUTION: After an amorphous silicon film is formed to crystallize, a gate electrode 14 is formed. Thereafter, impurities are doped to a silicon region with using the gate electrode 14 as a mask, to form N-type impurity regions 15a, 15b by a plasma doping method. The sum total of concentrations of this catalytic material does not exceed 1022 cm-3 in total. Thereafter, it is annealed in the nitrogen atmosphere, for example, at 500 deg.C, for example, for 4 hours, to activate impurities. With this configuration, it is possible to activate doping impurities in silicon at lower temperatures, for example, at 500 deg.C, and in a short time, for example, for 4 hours, and to enhance a throughput.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a thin film transistor (TFT) and a method for manufacturing the same. The thin film transistor manufactured by the present invention is formed on an insulating substrate such as glass and a semiconductor substrate such as single crystal silicon. In particular, the present invention relates to a thin film transistor manufactured through crystallization and activation by thermal annealing.

[0002]

2. Description of the Related Art In recent years, studies have been made on an insulating gate type semiconductor device having a thin-film active layer (also called an active region) on an insulating substrate. In particular, a thin film insulated gate transistor, a so-called thin film transistor (TFT), has been enthusiastically studied. These are formed on a transparent insulating substrate and are used for controlling each pixel or for a driving circuit in a display device such as a liquid crystal having a matrix structure. The amorphous silicon TFT and the crystalline silicon TFT are distinguished according to the crystalline state.

Generally, the electric field mobility of a semiconductor in an amorphous state is small, and therefore, a TF which requires high-speed operation is required.
Not available for T. Further, in the case of amorphous silicon, the P-type electric field mobility is extremely small, so that a P-channel TFT (PMOS TFT) cannot be manufactured.
T) and complementary MOS circuit (CMOS)
Cannot be formed.

On the other hand, a crystalline semiconductor has a higher electric field mobility than an amorphous semiconductor, and therefore can operate at high speed. In crystalline silicon, not only NMOS TFTs but also PMOS TFTs can be obtained in the same manner.
An S circuit can be formed. For example, in an active matrix type liquid crystal display device, a so-called monolithic structure in which not only the active matrix portion but also peripheral circuits (drivers and the like) are formed of CMOS crystalline TFTs is used. Are known. For these reasons, research and development of TFTs using crystalline silicon have recently been active.

[0005]

One method of obtaining crystalline silicon is to crystallize amorphous silicon by irradiating a laser or an equivalent intense light. And there is no prospect of mass production due to the instability caused by the extremely short process.

At present, a possible method that can be practically employed is a method of crystallizing amorphous silicon by heat. According to this method, crystalline silicon with less variation between batches can be obtained. However, it is not without problems.

Normally, to obtain crystalline silicon, a temperature of 600 ° C.
Long annealing at a temperature of about
Annealing at a high temperature of not less than ° C was necessary. If the latter method is adopted, the selectable substrate is limited to quartz, and the substrate cost becomes very high. Although the former method provides more room for substrate selection, it has another problem.

[0008] The conventional TFT fabrication process when an inexpensive alkali-free glass substrate (Corning No. 7059 or the like) is employed generally follows the flow described below. Amorphous silicon film formation Amorphous silicon film crystallization (600 ° C or higher,
24 hours or more) Formation of gate insulating film Formation of gate electrode Introduction of doping impurities (by ion implantation or ion doping method) Activation of doping impurities (600 ° C. or more, 24 hours or more) Formation of interlayer insulator Source and drain electrodes Formation

Here, the process is particularly problematic. At this stage, the distortion temperature of many alkali-free glasses is around 600 ° C. (59 for Corning 7059).
3 ° C.), which causes a problem of substrate shrinkage. At the stage of the first annealing process, the shrinkage of the substrate was not a problem because it had not been patterned yet. However, at this stage, since the circuit is patterned, if the substrate shrinks, subsequent mask alignment cannot be performed, which causes a large decrease in yield. Therefore, it has been desired to carry out this process at a lower temperature (preferably at a temperature lower by at least 50 ° C. than the distortion temperature of the glass).

For this purpose, for example, a method using a laser or the like as described above can be considered. However, in addition to the instability of the laser, a portion irradiated with the laser (source and drain regions) and a portion not irradiated with the laser ( Active area =
It was observed that stress was generated due to the difference in temperature rise between the region (below the gate electrode) and the reliability was reduced.

Therefore, it has been difficult to employ a laser or the like in terms of mass production. On the other hand, at present, no effective method can be found as another method. The present invention seeks to provide an answer to such a difficult task. An object of the present invention is to solve the above problems while maintaining mass productivity.

[0012]

As a result of the research by the present inventors,
It has been found that the crystallization can be promoted by adding a small amount of a catalyst material to the silicon film in a substantially amorphous state, the crystallization temperature can be reduced, and the crystallization time can be shortened. As the catalyst material, a simple substance of nickel (Ni), iron (Fe), cobalt (Co), platinum (Pt), or a compound such as a silicide thereof is suitable. Specifically, films, particles, clusters, and the like having these catalyst elements are formed in close contact with or below the amorphous silicon film, or these catalyst elements are formed in the amorphous silicon film by a method such as ion implantation. And then crystallized by thermal annealing at a suitable temperature, typically at or below 580 ° C.

As a matter of course, the higher the annealing temperature, the shorter the crystallization time. In addition, the higher the concentration of nickel, iron, cobalt and platinum, the lower the crystallization temperature and the shorter the crystallization time. According to the study of the present inventor, in order for crystallization to proceed, the concentration of at least one of these elements should be more than 1 × 10 ¹⁷ cm ⁻³ , preferably be 5 × 10 ¹⁸ cm ⁻³ or more. Turned out to be necessary.

On the other hand, all of the above catalyst materials are converted to silicon.
It is an unfavorable material.
It is desired that the concentration be low. In our study, this
The total concentration of these catalyst materials is 10²⁰cm^-3Does not exceed
It is desired. Especially when used as an active layer,
1 × 10 to obtain sufficient reliability and characteristics¹⁷cm ^-3
Less than 1 × 10¹⁶cm^-3Less than
Is required.

The present inventors have paid attention to the effect of this catalytic element, and have found that the above problem can be solved by using the catalytic element. The manufacturing process of the TFT according to the present invention is generally as follows. Amorphous silicon film formation Amorphous silicon film crystallization (600 ° C or higher,
24 hours or more) Deposition of gate insulating film Formation of gate electrode Introduction of doping impurities (by ion implantation or ion doping method) 'Deposition of a substance containing a catalytic element on silicon film Activation of doping impurities (600 ° C or lower, Within 8 hours) Formation of interlayer insulator Formation of source and drain electrodes

Alternatively, crystallization of an amorphous silicon film (at 600 ° C. or higher,
24 hours or more) Gate insulating film formation Gate electrode formation Doping impurity introduction (by ion implantation or ion doping method) 'Catalyst element introduction (by ion implantation or ion doping method) Activation of doping impurity (600 ° C or less) , Within 8 hours) Formation of interlayer insulator Formation of source and drain electrodes

In these steps, and 'can also reverse the order. In the present invention, the catalyst element mainly introduced into the source / drain regions by the above-mentioned process ′ remarkably promotes crystallization of the regions. Therefore, for activation, a temperature of 600 ° C. or less, typically 550 ° C. or less is sufficient, and an annealing time of 8 hours or less, typically 4 hours or less is sufficient. In particular, when the catalyst element is uniformly distributed from the beginning by the ion implantation method or the ion doping method as in the latter case, crystallization is extremely easy to proceed.

An excellent point of the present invention is that, although a catalytic element harmful to silicon is added to the TFT, its concentration is extremely low in the active region (1 × 10 ¹⁸ cm ⁻³ or less).
That is, no matter which process is employed, the catalytic element is not directly adhered to or injected into the active region because the gate electrode exists on the active region. As a result, the reliability and characteristics of the TFT are not impaired at all. Since the annealing uses a thermal equilibrium state, there is no temperature difference when using a laser. Hereinafter, the present invention will be described in more detail with reference to Examples.

[0019]

[Embodiment 1] FIG. 1 is a sectional view showing a manufacturing process of this embodiment. First, the substrate (Corning 7059) 10
A 2000 .ANG.-thick silicon oxide base film 11 was formed thereon by sputtering. Further, the thickness is 500 to 1500 °, for example, 1500 ° by a plasma CVD method.
An intrinsic (I-type) amorphous silicon film was deposited.
Then, this amorphous silicon film is placed in a nitrogen atmosphere,
Annealing was performed at 600 ° C. for 48 hours for crystallization. After annealing, the silicon film was patterned to form island-shaped silicon regions 12, and a silicon oxide film 13 having a thickness of 1000 ° was deposited as a gate insulating film by a sputtering method. For sputtering, silicon oxide was used as a target, and the substrate temperature during sputtering was 200 to 40.
At 0 ° C., for example, 350 ° C., the sputtering atmosphere is oxygen and argon, and argon / oxygen = 0 to 0.5, for example, 0.
1 or less.

Subsequently, a silicon film (containing 0.1 to 2% of phosphorus) having a thickness of 6000 to 8000 °, for example, 6000 ° was deposited by a low pressure CVD method. It is desirable that the step of forming the silicon oxide and the silicon film be performed continuously. And pattern the silicon film,
The gate electrode 14 was formed. (Fig. 1 (A))

Next, impurities (phosphorus) were implanted into the silicon region by using a gate electrode as a mask by a plasma doping method. Phosphine (PH) as doping gas
₃ ) using an acceleration voltage of 60 to 90 kV, for example, 80 kV.
V. The dose amount is 1 × 10 ¹⁵ to 8 × 10 ¹⁵ cm ⁻² ,
For example, it was set to 2 × 10 ¹⁵ cm ⁻² . As a result, N-type impurity regions 15a and 15b were formed. (FIG. 1 (B))

Next, the silicon oxide film 13 on the impurity region is etched to expose the impurity region 15, and the average thickness is 5 to 200 Å, for example, 2
Nickel silicide film of 0 Å (formula NiSi _x, 0.4 ≦ _x
≦ 2.5, for example, x = 2.0) 16 was formed on the entire surface as shown in the figure. At a thickness of about 20 °, the film was not continuous and rather appeared as an aggregate of particles, but there is no problem in this embodiment. (Fig. 1 (C))

Thereafter, annealing was performed at 500 ° C. for 4 hours in a nitrogen atmosphere to activate the impurities. At this time, since nickel diffuses from the nickel silicide film deposited on the N-type impurity regions 15a and 15b first, recrystallization easily progressed by this annealing. Thus, the impurity regions 15a and 15b were activated.
(Fig. 1 (D))

Subsequently, a silicon oxide film 17 having a thickness of 6000.degree.
Is formed by a plasma CVD method as an interlayer insulator,
A contact hole is formed in this, and a TFT is formed by a metal material, for example, a multilayer film of titanium nitride and aluminum.
Source / drain region electrodes / wirings 18a, 18
b was formed. Finally, in a hydrogen atmosphere of 1 atm.
Annealing was performed at 30 ° C. for 30 minutes. Through the above steps, a thin film transistor was completed. (FIG. 1E) The nickel concentration in the source, drain and active regions of the obtained thin film transistor was measured by secondary ion mass spectrometry (S
IMS) method, the former was 1 × 10 ¹⁸
~ 5 × 10 ¹⁸ cm ^-3 , the latter being the measurement limit (1 × 10 ¹⁶ cm ^-3)
cm ^-3 ) or less.

[Embodiment 2] FIG. 2 is a sectional view showing a manufacturing process of this embodiment. First, the substrate (Corning 7059) 2
A base film 21 made of silicon oxide and having a thickness of 2000 ° was formed on the substrate 0 by sputtering. Furthermore, plasma CVD
Depending on the method, the thickness may be 500-1500 °, for example 1500
An intrinsic (I-type) amorphous silicon film of Å was deposited. Then, the amorphous silicon film was crystallized by annealing at 600 ° C. for 48 hours in a nitrogen atmosphere. After that, the silicon film was patterned to form an island-shaped silicon region 22.

Further, tetraethoxysilane (Si
Using (OC ₂ H ₅ ) ₄ , TEOS) and oxygen as raw materials, a silicon oxide 23 having a thickness of 1000 ° was formed as a gate insulating film of a crystalline silicon TFT by a plasma CVD method. As a raw material, trichloroethylene (C ₂ HCl ₃ ) was used in addition to the above gas. Before film formation, oxygen is flowed into the chamber at 400 SCCM, substrate temperature is 300 ° C, total pressure is 5P
a, Plasma was generated at an RF power of 150 W, and this state was maintained for 10 minutes. After that, 300S oxygen
A silicon oxide film was formed by introducing 15 SCCM of CCM and TEOS and 2 SCCM of trichloroethylene. The substrate temperature, RF power and total pressure are 300
° C, 75W, and 5Pa. After the film formation was completed, 100 Torr of hydrogen was introduced into the chamber, and hydrogen annealing was performed at 350 ° C. for 35 minutes.

Subsequently, by a sputtering method,
A tantalum film having a thickness of 3000 to 8000, for example, 6000, was deposited. Instead of tantalum, titanium, tungsten, molybdenum, or silicon may be used. However, heat resistance enough to withstand subsequent activation is required. It is desirable that the step of forming the silicon oxide 23 and the tantalum film be performed continuously. Then, the tantalum film was patterned to form a gate electrode 24 of the TFT. Further, the surface of the tantalum wiring was anodized to form an oxide layer 25 on the surface. Anodization was performed in a 1-5% solution of tartaric acid in ethylene glycol. The thickness of the obtained oxide layer was 2000 °. (Fig. 2 (A))

Next, impurities (phosphorus) were implanted into the silicon region by a plasma doping method using the gate electrode as a mask. Phosphine (PH) as doping gas
_The acceleration voltage was set to 80 kV using ₃ ). The dose is 2
× 10 ¹⁵ cm ^-2 . As a result, the N-type impurity region 2
6a and 26b were formed. At this time, the gate electrode 24 and the impurity region 26 are in an offset state due to the anodic oxide. (FIG. 2 (B))

Further, nickel ions were implanted into the silicon region by ion implantation using the gate electrode as a mask. The dose amount is 2 × 10 ¹³ to 2 × 10 ¹⁴ cm ⁻² ,
For example, it was set to 5 × 10 ¹³ cm ⁻² . As a result, the concentration of nickel in the N-type impurity regions 26a and 26b is 5 × 10 ¹⁸
cm ^-3 . (Fig. 2 (C))

After that, the impurities were activated by annealing in a nitrogen atmosphere at 500 ° C. for 4 hours. At this time, since the N-type impurity regions 26a and 26b have been implanted with nickel ions, the recrystallization easily proceeded by this annealing. Thus, impurity region 26
a, 26b were activated. (FIG. 2 (D))

Subsequently, as an interlayer insulating material, a thickness of 2000
CV using TEOS as a raw material for silicon oxide film 27
The source and drain electrodes / wirings 28a and 28 are formed by a metal material, for example, a multilayer film of titanium nitride and aluminum.
b was formed. The semiconductor circuit was completed by the above steps. (FIG. 2 (E))

The field effect mobility of the manufactured thin film transistor is 70 to 100 cm ² / V at a gate voltage of 10 V.
s, the threshold value was 2.5 to 4.0 V, and the leak current when applying a voltage of −20 V to the gate was 10 ⁻¹³ A or less.

[0033]

According to the present invention, the throughput can be improved by activating doping impurities in silicon at a low temperature of, for example, 500 ° C. and in a short time of 4 hours. In addition, 60
When a process at 0 ° C. or higher was employed, shrinkage of the glass substrate was a problem as a cause of a decrease in yield, but such a problem could be solved at a stretch by using the present invention.

This means that a large area substrate can be processed at one time. That is, by processing a large-area substrate, a large number of semiconductor circuits (such as a matrix circuit) can be cut out from one substrate, whereby the unit cost can be significantly reduced. When this is applied to a liquid crystal display, improvement of mass productivity and improvement of characteristics can be achieved. Thus, the present invention is an industrially useful invention.

[Brief description of the drawings]

FIG. 1 shows a cross-sectional view of a manufacturing process in Example 1.

FIG. 2 shows a cross-sectional view of a manufacturing process in Example 2.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 10 ... Substrate 11 ... Base insulating film (silicon oxide) 12 ... Island-like silicon region 13 ... Gate insulating film (silicon oxide) 14 ... Gate electrode (phosphorus-doped silicon) 15. ..Source and drain regions 16 ... Coating containing catalyst element (nickel silicide) 17 ... Interlayer insulator (silicon oxide) 18 ... Metal wiring / electrode (titanium nitride / aluminum)

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[Procedure amendment]

[Submission date] April 12, 2000 (2004.1.
2)

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Claims

[Correction method] Change

[Correction contents]

[Claims]

Claims (2)

[Claims] In a semiconductor device in which a semiconductor film having crystallinity is formed on an insulating surface, the semiconductor film has a pair of impurity regions having P-type or N-type conductivity, and the pair of impurity regions. Contains an element that promotes crystallization, the concentration of the element that promotes crystallization in the semiconductor film is a concentration that does not exceed 1 × 10 ²⁰ cm ⁻³ , and at least one of the pair of impurity regions A semiconductor device, wherein one impurity region is formed in a self-aligned manner with a gate electrode. 2. The semiconductor device according to claim 1, wherein the element that promotes crystallization is nickel, iron, cobalt, or platinum.