JPH10135476A - Thin film transistor and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a TFT having a high reliability and characteristics by removing a catalytic element for accelerating the crystallizing to form a grain boundary approximately perpendicular to a carrier traveling direction at substantially the center of a channel forming region. SOLUTION: A catalytic element is removed from an active layer, and resulting marks 32 at granular parts contg. the catalytic element at a high concn. again form new grain boundaries perpendicular to the carrier running direction to provide a pinning effect for suppressing a depletion layer from expanding. On a substrate 10 active regions of a crystalline Si film 12 exist and have channel forming regions self-alignedly formed by gate electrodes 15. The channel forming regions have grain boundaries approximately parallel to the carrier running direction and center grain boundaries obtained by removing the crystallization accelerating catalytic element.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a thin film transistor (T
FT) and its manufacturing method. The thin film transistor manufactured by the present invention is formed on an insulating substrate such as glass and a semiconductor substrate such as single crystal silicon. In particular, the present invention relates to a thin film transistor manufactured through a step of crystallizing an amorphous silicon film by thermal annealing.

[0002]

2. Description of the Related Art In recent years, studies have been made on an insulating gate type semiconductor device having a thin-film active layer (also called an active region) on an insulating substrate. In particular, a thin film insulated gate transistor, a so-called thin film transistor (TFT), has been enthusiastically studied. These are formed on a transparent insulating substrate and are used for controlling each pixel or for a driving circuit in a display device such as a liquid crystal having a matrix structure. The amorphous silicon TFT and the crystalline silicon TFT are distinguished according to the crystalline state.

Generally, the electric field mobility of a semiconductor in an amorphous state is small, and therefore, a TF which requires high-speed operation is required.
Not available for T. Further, in the case of amorphous silicon, the P-type electric field mobility is extremely small, so that a P-channel TFT (PMOS TFT) cannot be manufactured.
T) and complementary MOS circuit (CMOS)
Cannot be formed.

On the other hand, a crystalline semiconductor has a higher electric field mobility than an amorphous semiconductor, and therefore can operate at high speed. In crystalline silicon, not only NMOS TFTs but also PMOS TFTs can be obtained in the same manner.
An S circuit can be formed. For example, in an active matrix type liquid crystal display device, a so-called monolithic structure in which not only the active matrix portion but also peripheral circuits (drivers and the like) are formed of CMOS crystalline TFTs is used. Are known. For these reasons, research and development of TFTs using crystalline silicon have recently been active.

One of the methods for obtaining crystalline silicon is as follows.
There is a method to crystallize amorphous silicon by irradiating a laser or strong light equivalent to it.However, mass production due to instability of laser output and instability due to extremely short process time There is no prospect.

At present, a possible method that can be practically used is a method of crystallizing amorphous silicon by heat (thermal annealing method). According to this method, crystalline silicon with less variation between batches can be obtained. Usually, as the thermal annealing method, long-time annealing at a temperature of about 600 ° C. or annealing at a high temperature of 1000 ° C. or more is employed. Alternatively, as disclosed in JP-A-6-244104, when a catalyst element that promotes crystallization is used, crystallization can be achieved at a lower temperature and in a shorter time.

[0007]

Heretofore, it has been conventionally practiced that an amorphous silicon film is crystallized by a thermal annealing method, then doped with impurities, and activated again by a thermal annealing method. . However, it is also conceivable to carry out this step simultaneously. In particular, when a crystallization promoting catalyst element is used, crystallization proceeds in the lateral direction, and TF using a crystalline silicon film having excellent characteristics is used.
T can be expected to be obtained. An example is shown in FIGS.
It is shown in (D).

First, a base insulating film (usually a silicon oxide film) 11 and an amorphous silicon film 12 are deposited on a glass or quartz substrate 10 (FIG. 1A). Then, the amorphous silicon film 12 is etched. An island-shaped region (active layer) 13 is formed. Further, a gate insulating film 14 and a gate electrode 15 are formed. (Figure 1
(B))

Further, the active layer 1 of amorphous silicon is formed by ion implantation (or ion doping).
An impurity (for example, phosphorus) is introduced into 3. At this time, the gate electrode 15 serves as a mask, and impurity regions (source and drain) 16a and 16b are formed. (FIG. 1 (C) and FIG. 3 (A))

Next, the gate insulating film 14 is etched by using the gate electrode as a mask to expose the impurity regions 16a and 16b. Then, it is coated with a film 17 containing a catalyst element. When an appropriate heat treatment is performed in this state, the catalytic element first penetrates into the impurity regions (source and drain) and crystallizes this portion. Next, the catalyst element moves from the impurity region to a channel formation region sandwiched between the impurity regions, and this portion also crystallizes. Thus, the active layer 13
Crystallizes entirely. The thermal annealing temperature at this time is 60
The temperature does not need to be 0 ° C. or lower, and if a constituent material of the substrate or the TFT (gate electrode or the like) permits, a higher temperature (eg, 700
To 1000 ° C.) (FIG. 1 (D))

[0011] However, the T
In FT, the presence of a crystallization promoting catalyst element poses a problem. As described above, in the crystallization / activation process, the crystal proceeds from the impurity region (source, drain) into the central channel formation region, but the catalyst element moves to the tip of crystal growth, so that the final Actually, it ends almost at the center of the channel forming region.

The catalytic element becomes granular as shown in FIGS. 3B and 4A. In many cases, it will be silicide and show high conductivity. On the other hand, silicon becomes a crystal 34 which is long in the direction of crystallization, and the grain boundary 33 is substantially parallel to the direction connecting the source and the drain (the direction of travel of the carrier). (FIG. 3 (B) (conceptual sectional view) and FIG. 4 (B)
(Conceptual diagram of top surface)) In order to enhance reliability and characteristics, it is necessary to remove a catalytic element.

[0013]

As a result of the research by the present inventors,
In order to satisfy the above object, after thermal annealing, a silicon oxide having a thickness that has a halogen compound (for example, hydrogen chloride) and allows the catalyst element to pass through the silicon surface but does not etch the silicon film by the halogen compound It has been clarified that the catalyst element can be removed from the silicon film by performing the heat treatment in an atmosphere and a temperature at which the film is formed.

Naturally, in order to obtain a silicon oxide film having an appropriate thickness for the above purpose, an appropriate oxygen partial pressure of the atmosphere varies depending on the temperature. Further, hydrogen or water may be contained in the atmosphere, but since these promote the etching of the silicon film, a lower concentration is preferable. In the present invention,
As the temperature of the heat treatment, 450 to 700 ° C., preferably 5
Although it is assumed that the temperature is 50 to 600 ° C., in this temperature range, the partial pressures of nitrogen and a rare gas are 20 to 95%, preferably 50 to 95%.
If 70% and the partial pressure of oxygen is 5 to 40%, the above condition is satisfied.

Of course, if the temperature range is different from the above range, the optimum partial pressure of the gas is also different from the above range. However, in general, if the temperature is higher than the above temperature, the etching of silicon proceeds,
The reaction does not proceed at low temperatures. Also, the concentration of the halogen compound varies depending on the substance. However, in the case of hydrogen chloride which is generally easy to use, a sufficient effect is obtained if the content is 0.5% or more.

By the above treatment, the catalyst element (for example, nickel) is removed from the active layer (including the source, drain, and channel formation region) (FIG. 1E), and the catalyst element existing in the channel formation region is reduced. The trace 32 of the granular portion included in the density becomes a new grain boundary. This grain boundary exists perpendicular to the carrier traveling direction, and has a pinning effect for suppressing the expansion of the depletion layer. Therefore, not only a TFT having no catalytic element removal step but also a TF obtained by using a crystal which is similarly oriented using a catalytic element.
Compared with T (for example, Japanese Patent Publication No. 7-66425), higher reliability and characteristics can be obtained. (FIG. 1 (E), FIG. 3
(C) and FIG. 4 (B))

The TFT obtained by the above processing has the following configuration. That is, it has an active region of a crystalline silicon film formed on a substrate, the active region has a channel forming region formed in a self-aligned manner by a gate electrode,
The channel forming region has a grain boundary substantially parallel to the carrier traveling direction and a grain boundary at a substantially central portion thereof, and the grain boundary at the central portion is formed by removing a catalytic element that promotes crystallization. It is obtained.

In the above structure, the catalyst elements are Ni (nickel), Pd (palladium), Pt (platinum), Cu
One or more types may be selected from (copper), Ag (silver), Au (gold), In (indium), Sn (tin), P (phosphorus), As (arsenic), and Sb (antimony). Further, the catalyst element may be selected from Group VIII, IIIb, IVb and Vb elements.

Further, in order to fabricate the TFT having the above structure, the following steps may be performed. (1) The concentration of the catalyst element on the substrate is 1 × 10 ¹⁷ atoms / c
forming an amorphous silicon film less than m ³ (2) ion-implanting N-type or P-type impurities into the amorphous silicon (3) closely contacting the amorphous silicon film and covering the amorphous silicon film and the gate electrode; Forming a film of a substance having a catalytic element that promotes crystallization. (4) Activating impurities introduced into the amorphous silicon film by thermally annealing the silicon film, and forming a channel forming region below the gate electrode. (5) Introduction of a gas containing a halogen compound and oxygen
A fifth step of removing the catalyst element from the silicon film by performing heat treatment at 50 to 700 ° C.

Instead of the step (3), a method of implanting ions of a catalytic element may be adopted. In that case only, steps (2) and (3) may be interchanged. If a step of forming a gate electrode is provided between the steps (1) and (2), the impurity can be implanted in a self-aligned manner. In the above step (3), the coating of the substance having a catalytic element is formed by a sputtering method (Japanese Patent Laid-Open No.
104, etc.), a vapor phase growth method (JP-A-7-335).
548) or a spin coating method (JP-A-7-130652).

[0021]

【Example】

Embodiment 1 FIG. 1 shows a cross-sectional view of a manufacturing process of this embodiment. First, a 2000-nm-thick silicon oxide base film 11 was formed on a substrate (quartz) 10 by a plasma CVD method. Further, by a plasma CVD method, a thickness of 500 to
An intrinsic (I-type) amorphous silicon film 12 of 1500 °, for example, 500 ° was deposited. It was confirmed by secondary ion mass spectrometry that the concentration of the catalytic element in the amorphous silicon film was less than 1 × 10 ¹⁷ atoms / cm ³ .
(Fig. 1 (A))

This is etched to form an island-shaped silicon region 13, and a silicon oxide film 14 having a thickness of 1000 ° is deposited as a gate insulating film by a plasma CVD method. Subsequently, a thickness of 300 mm is formed by a low pressure CVD method.
0 to 8000 °, for example, 6000 ° silicon film (0.
Containing 1-2% phosphorus). It is desirable that the step of forming the silicon oxide and the silicon film be performed continuously. Then, the gate electrode 15 was formed by etching the silicon film. (FIG. 1 (B))

Next, impurities (phosphorus) were implanted into the silicon region by a plasma doping method using the gate electrode as a mask. Phosphine (PH) as doping gas
₃ ) using an acceleration voltage of 60 to 90 kV, for example, 80 kV.
V. The dose amount is 1 × 10 ¹⁵ to 8 × 10 ¹⁵ cm ⁻² ,
For example, it was set to 2 × 10 ¹⁵ cm ⁻² . As a result, N-type impurity regions 16a and 16b were formed. (Fig. 1 (C))

Next, the silicon oxide film 14 on the impurity region is etched to expose the impurity region 16, and the thickness is 5 to 200 °, for example, 2
0Å nickel silicide film (chemical formula NiSi _x, 0.
4 ≦ x ≦ 2.5, for example, x = 2.0) 17 was formed on the entire surface as shown in the figure. At a thickness of about 20 °, the film was not continuous and rather appeared as an aggregate of particles, but there is no problem in this embodiment. (Figure 1
(D))

After that, the impurities were activated by annealing at 550 ° C. for 4 hours in a nitrogen atmosphere. At this time, nickel diffuses from the nickel silicide film deposited on the N-type impurity regions 16a and 16b first, so that the recrystallization easily progressed by this annealing. Thus, the impurity regions 16a and 16b were activated. In addition, nickel spreads to the channel formation region,
Finally, the island-shaped silicon region 12 was entirely crystallized. Next, the temperature is raised to 900 ° C.,
Hold for hours.

Next, the substrate temperature was lowered to 600.degree. The atmosphere was adjusted so that the partial pressure of nitrogen was 88%, the partial pressure of oxygen was 10%, and the partial pressure of hydrogen chloride was 2%. The nickel was removed by leaving it in this state for 10 to 60 minutes. (FIG. 1E) Finally, a silicon oxide film 18 having a thickness of 6000.degree. Is formed as an interlayer insulator by a plasma CVD method, and a contact hole is formed in the silicon oxide film 18 to form a metal material, for example, a multilayer of titanium nitride and aluminum. Depending on the film, the source region of the TFT,
Drain region electrodes / wirings 19a and 19b were formed.
Finally, annealing was performed at 350 ° C. for 30 minutes in a hydrogen atmosphere at 1 atm. Through the above steps, a thin film transistor was completed. (FIG. 1 (F))

[Embodiment 2] FIG. 2 is a sectional view showing a manufacturing process of this embodiment. First, the substrate (Corning 7059) 2
A base film 21 made of silicon oxide and having a thickness of 2000 ° was formed on the substrate 0 by sputtering. Furthermore, plasma CVD
Depending on the method, the thickness may be 200 to 1500 °, for example, 800
An intrinsic (I-type) amorphous silicon film 22 of Å was deposited. The concentration of the element corresponding to the catalyst element in this amorphous silicon film was 1 × 10 ¹⁷ atoms / cm ^3.
Was confirmed by secondary ion mass spectrometry. (Fig. 2 (A))

Next, the silicon film was patterned to form an island-like silicon region 23. Further, tetraethoxysilane (Si (OC ₂ H ₅ ) ₄ , TEO
Using S) and oxygen as raw materials, a gate insulating film having a thickness of 1000
The silicon oxide 24 of Å was formed. As a raw material, trichloroethylene (C ₂ HCl ₃ ) was used in addition to the above gas.
Before film formation, oxygen was supplied to the chamber at 400 SCCM, plasma was generated at a substrate temperature of 300 ° C., a total pressure of 5 Pa, and an RF power of 150 W, and this state was maintained for 10 minutes. After that, 300 SCCM of oxygen and 15 SCC of TEOS were put in the chamber.
M and trichlorethylene were introduced at 2 SCCM to form a silicon oxide film. The substrate temperature, RF power, and total pressure were 300 ° C., 75 W, and 5 Pa, respectively. After the film formation was completed, 100 Torr of hydrogen was introduced into the chamber, and hydrogen annealing was performed at 350 ° C. for 35 minutes.

Subsequently, by a sputtering method,
A tantalum film having a thickness of 3000 to 8000, for example, 6000, was deposited. Instead of tantalum, titanium, tungsten, molybdenum, or silicon may be used. However, heat resistance enough to withstand subsequent activation is required. It is desirable that the step of forming the silicon oxide 24 and the tantalum film be performed continuously. Then, the tantalum film was patterned to form a gate electrode 25 of the TFT. (Figure 2
(B))

Next, impurities (phosphorus) were implanted into the silicon region using the gate electrode as a mask by a plasma doping method. Phosphine (PH) as doping gas
_The acceleration voltage was set to 80 kV using ₃ ). The dose is 2
× 10 ¹⁵ cm ^-2 . As a result, the N-type impurity region 2
6a and 26b were formed. (FIG. 2 (C)) Furthermore, nickel ions were implanted into the silicon region by ion implantation using the gate electrode as a mask. The dose was 1 × 10 ¹⁴ to 2 × 10 ¹⁵ atoms / cm ² , for example, 5 × 10 ¹⁴ atoms / cm ² . As a result, the concentration of nickel in the N-type impurity regions 26a and 26b is 5 × 10 ¹⁹
It became about atoms / cm ³ . (FIG. 2 (D))

Thereafter, the impurities were activated by annealing in a nitrogen atmosphere at 550 ° C. for 4 hours. At this time, since the N-type impurity regions 26a and 26b have been implanted with nickel ions, the recrystallization easily proceeded by this annealing. Thus, impurity region 26
a, 26b were activated. Nickel also reached the channel formation region, and eventually the entire island-like silicon region 23 was crystallized.

The substrate is taken out, the silicon oxide film 24 is etched using the gate electrode 25 as a mask, and the impurity region 2 is removed.
6a and 26 were exposed. For the etching, a dry etching method was used. Next, the substrate temperature was set to 550 ° C., and the atmosphere was adjusted so that the partial pressure of nitrogen was 88%, the partial pressure of oxygen was 10%, and the partial pressure of hydrogen chloride was 2%. In this state
The nickel was removed by standing for 60 minutes. (FIG. 2 (E))

Finally, as an interlayer insulator, a thickness of 2000 mm
CV using TEOS as a raw material for silicon oxide film 28
D, a contact hole is formed therein, and source and drain electrodes / wirings 29a and 29a are formed by a metal material, for example, a multilayer film of titanium nitride and aluminum.
b was formed. Through the above steps, a TFT was completed.
(FIG. 2 (F))

[Embodiment 3] FIG. 5 is a sectional view showing a manufacturing process of this embodiment. First, a 2000-mm-thick silicon oxide base film 4 is formed on a substrate (quartz) 40 by plasma CVD.
1 was formed. Further, as in the other embodiments, the thickness 20
Island regions 42a and 42b of an intrinsic (I-type) amorphous silicon film of 0 to 1500 °, for example, 800 °, a gate insulating film 43 of silicon oxide covering them, and gate electrodes 44a and 44b of amorphous silicon doped with phosphorus.
Was formed. Gate insulation of a crystalline silicon TFT by a plasma CVD method using oxygen as a raw material (FIG. 5A)

Next, impurities (phosphorus and boron) were implanted into the silicon region using the gate electrode as a mask by a plasma doping method. As a doping gas, phosphine (PH ₃ ) and diborane (B ₂ H ₆ ) are used, and a known CM is used.
OS forming technology was adopted. The acceleration voltage is 80 kV for the former,
The latter was 65 kV, and the dose was 1 × 10 ¹³ atoms / cm ^{3 for} the former and 5 × 10 ¹⁵ atoms / cm ³ for the latter. As a result, the N-type low concentration impurity regions 45a, 45b and P
Mold high concentration impurity regions 46a and 46b were formed.
(FIG. 5 (B))

Then, the gate electrodes 44a, 4a are formed by using a known side wall forming technique (for example, JP-A-8-18055).
A side wall 47 of silicon oxide was formed on the side surface of 4b. And
An extremely thin film 48 of nickel acetate was formed by spin coating. (FIG. 5C) Next, an impurity (phosphorus) was again implanted into the silicon region 42a by the plasma doping method using the gate electrode 44a and the side wall 47 as a mask. Phosphine (PH ₃ ) is used as the doping gas, and the acceleration voltage is 10 k.
V and the dose amount were 2 × 10 ¹⁵ atoms / cm ³ . As a result, N-type high concentration impurity regions 49a and 49b were formed. On the other hand, the low-concentration impurity region 45c under the side wall 47 remains as it is. As a result, a double drain structure was obtained in the island-shaped silicon region 42a. (FIG. 5 (D))

Thereafter, the impurities were activated by annealing in a nitrogen atmosphere at 900 ° C. for 1 hour. At this time, since the N-type and P-type impurity regions are in contact with the nickel film obtained by decomposition of nickel acetate, first, they are recrystallized by annealing, and then nickel reaches the channel formation region. Finally, the island-like silicon regions 42a and 42b were entirely crystallized. Next, the temperature was lowered to 600 ° C., and the atmosphere was adjusted so that the partial pressure of nitrogen was 88%, the partial pressure of oxygen was 10%, and the partial pressure of hydrogen chloride was 2%. The nickel was removed by leaving it in this state for 10 to 60 minutes. (FIG. 5E)

Finally, as an interlayer insulating material, a thickness of 6000Å
Silicon oxide film 50 is formed by a plasma CVD method,
A contact hole was formed in this, and source / drain electrodes / wirings 51a to 51d were formed using a metal material, for example, a multilayer film of titanium nitride and aluminum. Through the above steps, the N-channel TFT 52n and the P-channel TFT 52p are completed. (FIG. 5 (F))

[0039]

According to the present invention, by introducing a catalytic element for promoting crystallization of amorphous silicon into an impurity region, a specific direction (parallel to a traveling direction of carriers) is applied to a channel crystal region.
A long silicon crystal grain is formed on the substrate, and then a catalyst element is removed, thereby forming a grain boundary almost perpendicular to the carrier traveling direction almost at the center of the channel forming region. By using a silicon film whose direction and the like are determined, a TFT having high reliability and characteristics can be obtained. Thus, the present invention is an industrially useful invention.

[Brief description of the drawings]

FIG. 1 shows a cross-sectional view of a manufacturing process in Example 1.

FIG. 2 shows a cross-sectional view of a manufacturing process in Example 2.

FIG. 3 shows a conceptual diagram of introduction and removal of a catalytic element (cross-sectional view).

FIG. 4 shows a conceptual diagram of introduction and removal of a catalytic element (top view).

FIG. 5 shows a cross-sectional view of a manufacturing process in Example 3.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 10 ... Substrate 11 ... Base insulating film (silicon oxide) 12 ... Amorphous silicon film 13 ... Island-shaped silicon region 14 ... Gate insulating film (silicon oxide) 15 ... Gate electrode (phosphorus) Doped silicon 16 Impurity region (source / drain region) 17 Coating containing catalyst element (nickel silicide) 18 Interlayer insulator (silicon oxide) 19 Metal wiring / electrode (Titanium nitride / aluminum) 20 ... substrate 21 ... underlying insulating film (silicon oxide) 22 ... amorphous silicon film 23 ... island silicon region 24 ... gate insulating film (silicon oxide) 25. ..Gate electrode (tantalum) 26 ... impurity region (source / drain region) 28 ... interlayer insulator (silicon oxide) 29 ... metal wiring / electrode (titanium nitride / aluminum) 31) A portion where the catalytic element (nickel) is deposited 32 ... A trace from which the catalytic element (nickel) is removed 33 ... A grain boundary parallel to the carrier flowing direction 34 ... A silicon crystal grain 40 ... Substrate 41 ... Base insulating film (silicon oxide) 42 ... Silicon-shaped silicon region 43 ... Gate insulating film (silicon oxide) 44 ... Gate electrode (phosphorus-doped silicon) 45 ... -Low-concentration N-type impurity region 46-High-concentration P-type impurity region 47-Side wall (silicon oxide) 48-Coating containing nickel (nickel acetate) 49-High-concentration N-type impurity region 50 ... interlayer insulator (silicon oxide) 51 ... metal wiring / electrode (titanium nitride / aluminum) 52 ... N-type and P-type TFT

Claims (13)

[Claims] An active region of a crystalline silicon film formed on a substrate has a channel forming region formed in a self-aligned manner by a gate electrode, and the channel forming region has a carrier. Having a grain boundary substantially parallel to the direction of travel and a grain boundary at a substantially central portion thereof, wherein the grain boundary at the central portion is obtained by removing a catalytic element that promotes crystallization. A thin film transistor characterized by the above-mentioned. 2. The method according to claim 1, wherein the catalyst element is Ni,
Pd, Pt, Cu, Ag, Au, In, Sn, P, A
A thin film transistor, which is one or more elements selected from s and Sb. 3. The method according to claim 1, wherein the catalyst element is VIII.
A thin film transistor, which is one or more elements selected from Group III, Group IIIb, Group IVb, and Group Vb elements. 4. A catalyst element having a concentration of 1 × 10 ¹⁷ on a substrate.
A first step of forming an amorphous silicon film of less than atoms / cm ^3, a second step of ion-implanting N-type or P-type impurities into the amorphous silicon film, A third step of forming a film of a substance having a catalytic element that promotes crystallization by covering the amorphous silicon film and the gate electrode; and thermally annealing the silicon film to remove impurities introduced into the amorphous silicon film. A fourth step of activating and crystallizing a channel formation region formed under the gate electrode, and introducing a gas containing a halogen compound and oxygen and performing heat treatment at 450 to 700 ° C.
A fifth step of removing the catalyst element from the silicon film. 5. The method according to claim 1, wherein the concentration of the catalytic element is 1 × 10 ¹⁷ on the substrate.
A first step of forming an amorphous silicon film of less than atoms / cm ^3, a second step of ion-implanting N-type or P-type impurities into the amorphous silicon film, and a catalyst for promoting crystallization in the silicon film A third step of implanting elemental ions, and thermal annealing of the silicon film to activate impurities introduced into the amorphous silicon film and to crystallize a channel forming region formed below the gate electrode. By introducing a gas containing a halogen compound and oxygen in the fourth step and performing heat treatment at 450 to 700 ° C.,
A fifth step of removing the catalyst element from the silicon film;
A method for manufacturing a thin film transistor, comprising: 6. The method according to claim 4, wherein Ni, Pd, Pt, Cu, Ag, Au, In,
A method for manufacturing a thin film transistor, comprising using one or more elements selected from Sn, P, As, and Sb. 7. The method for manufacturing a thin film transistor according to claim 4, wherein one or more elements selected from Group VIII, IIIb, IVb, and Vb elements are used as the catalyst element. . 8. The method for manufacturing a thin film transistor according to claim 4, further comprising a step of forming a gate electrode between the first step and the second step. 9. The gas according to claim 4, wherein the gas introduced into the fifth step has a partial pressure of nitrogen and a rare gas of 20.
A method for manufacturing a thin film transistor, wherein the partial pressure of oxygen is 5 to 40%. 10. The method for manufacturing a thin film transistor according to claim 4, wherein the gas introduced in the fifth step contains 0.5% or more of hydrogen chloride. 11. The method for manufacturing a thin film transistor according to claim 4, wherein the coating of the substance having a catalytic element is formed by a sputtering method. 12. The method for manufacturing a thin film transistor according to claim 4, wherein the film of the substance having a catalytic element is formed by a vapor deposition method. 13. The method for manufacturing a thin film transistor according to claim 4, wherein the film of the substance having a catalytic element is formed by a spin coating method.