JP2000294798A - Thin film transistor and semiconductor circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a method for efficiently manufacturing a semiconductor circuit wherein a thin film transistor(TFT) and a thin film diode(TFD) are combined. SOLUTION: An island-like silicon regions 32a, 32b are formed on a substrate 30 and a gate insulating film 33 and a gate electrodes 34a-34c are formed thereon. Phosphorus is injected using the gate electrodes 34a-34c as a mask, and a catalyst element (e.g. Ni) is successively injected, and then boron whose amount being more than that of the phosphorus is injected using a resist 36 as a mask to simultaneously form an n-type region 37a, a p-type region 37b of a TFT, an n-type region 38n, and a p-type region 38p of a TFD. The catalyst is diffused by annealing it and a crystal silicon TFT wherein crystallization is progressed except an intrinsic region 38i of the TFD is efficiently manufactured.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor circuit (for example, an image sensor) having a thin film transistor (TFT) and a thin film diode (TFD) and a method for manufacturing the same. A semiconductor circuit manufactured by the present invention is formed on an insulating substrate such as glass or a semiconductor substrate such as single crystal silicon. In particular, the present invention relates to a semiconductor circuit having a TFT and a TFD manufactured through crystallization and activation by thermal annealing.

[0002]

2. Description of the Related Art Thin film semiconductor devices such as thin film transistors and thin film diodes are classified into amorphous devices and crystalline devices according to the type of silicon used.
Amorphous silicon has a low production temperature and is excellent in mass productivity, but is inferior to crystalline silicon in physical properties such as field-effect mobility and electrical conductivity. Therefore, a crystalline semiconductor element is required to obtain high-speed operation characteristics. Was. Recently, a circuit (for example, an integrated image sensor circuit) in which an optical sensor using a thin film diode is driven by a thin film transistor using crystalline silicon which can operate at high speed has been proposed.

[0003]

FIG. 4 shows an example of a conventional procedure for manufacturing a circuit in which a TFD and a TFT are combined. A base insulating film 42 is formed on a glass substrate 41, an amorphous silicon film is formed thereon, and this is annealed at a temperature of 600 ° C. or more for a long time to be crystallized and patterned to form an island-shaped silicon region 43. Get. Then, a gate insulating film 44 is formed, and further, gate electrodes 45N,
5P is formed. (FIG. 4 (A))

Then, an N-type impurity region 46N and a P-type impurity region 46P are formed by using a known CMOS fabrication technique. In this impurity introduction step, impurities are introduced in a self-aligned manner with respect to the gate electrode. After impurity implantation,
Activation of impurities is performed by means such as laser annealing and thermal annealing. (FIG. 4 (B))

Next, a first interlayer insulator 47 is formed,
A contact hole is formed in this, and electrodes / wirings 48a, 48b, 48c and an electrode 48d of an amorphous silicon diode are formed on the source and drain of the TFT. (FIG. 4 (C)) Next, P-type, I-type (intrinsic), and N-type amorphous silicon films 49P, 49I, and 49N are sequentially stacked and patterned to form a junction of a diode. (FIG. 4
(D) Finally, a second interlayer insulator 50 is formed, a contact hole is formed therein, and an electrode 51 of an amorphous silicon diode is formed, thereby completing the circuit. (FIG. 4
(E))

In a conventional method requiring such a procedure,
Since a silicon film and an interlayer insulator, each of which is required to be formed for a long period of time, need to be formed of two layers each, in addition to the N layer and the P layer, there is a problem that the throughput is reduced. In addition, in the plasma CVD method and the low pressure CVD method used in these film formations, a dead time of an apparatus for maintenance is long, and the extra steps cause a further decrease in throughput.

In addition, a temperature of 600 ° C. or more is required for crystallization of a silicon film used for a crystalline silicon TFT, and a long time of 24 hours or more is required for the crystallization. For mass production, several crystallization equipments are required, and there is a problem that a huge capital investment is reflected in the cost. The present invention overcomes the above problems by simultaneously forming a silicon film used for a crystalline silicon TFT and a silicon film used for a TFD, and using only one interlayer insulator. The present invention provides a technique for crystallizing a silicon film at the above temperature and in a short time that does not substantially cause a problem.

[0008]

As a result of the research by the present inventors,
It has been found that the crystallization can be promoted by adding a small amount of a catalyst material to the silicon film in a substantially amorphous state, the crystallization temperature can be reduced, and the crystallization time can be shortened. Nickel (Ni), iron (Fe), cobalt (Co), and platinum (Pt) are suitable as catalyst elements. Specifically, films, particles, clusters, etc. having these catalyst elements alone or compounds such as silicides are formed in close contact with or below the amorphous silicon film, or the amorphous silicon film is formed by a method such as ion implantation. These catalyst elements can be crystallized by introducing these catalytic elements into the film and then thermally annealing them at a suitable temperature, typically at a temperature of 580 ° C. or less.

It is a matter of course that the higher the annealing temperature, the shorter the crystallization time. Further, the higher the concentration of the catalytic element, the lower the crystallization temperature and the shorter the crystallization time. In the study of the present inventor, in order for crystallization to proceed, the concentration of at least one of these elements is 1 × 10 ¹⁷ cm ⁻³ , preferably 5 × 10 ¹⁸ cm ⁻³ .
It turns out that it is necessary to be present at least ^-3 .

[0010] On the other hand, since the above-mentioned catalyst materials are all unfavorable materials for silicon, it is desired that their concentrations be as low as possible. In our study, the concentration of these catalyst materials combined to achieve sufficient reliability and properties, especially when utilized as the active region, was 2%.
It is desired not to exceed × 10 ²⁰ cm ⁻³ . On the other hand, it has been clarified that the presence of a relatively large amount in the source and drain does not cause any problem.

Further, such a catalytic element has an effect of crystallizing the periphery by diffusing during the annealing. For example, when annealing is performed at 550 ° C. for 4 hours, these catalytic elements diffuse around 10 to 20 μm and crystallize around. Therefore, if the width of the gate electrode of the TFT is 20 μm, preferably 10 μm or less,
Before and after the introduction of the N-type or P-type impurities, the catalyst element is similarly introduced into the source and the drain, and this is annealed, whereby the crystallization progresses in the lateral direction and the active region where the catalyst element is not introduced. (A channel formation region) can also be crystallized. In general, in this method, the concentration of the catalytic element in the active region is lower than the concentration of the catalytic element in the source and the drain. This lateral crystallization depends on the annealing temperature and time, and the concentration of the catalytic element. Therefore, by optimizing these, the crystalline silicon region and the amorphous silicon region can be freely formed. For example, two types of TFT gate electrodes having a width of 5 μm and a width of 30 μm are prepared.
It is also possible to use a crystal silicon TFT of 5 μm and an amorphous silicon TFT of 30 μm.

The present inventor has paid attention to the effect of the catalytic element, and by utilizing this effect, it has become possible to lower the conductivity of the impurity region by annealing at a lower temperature for a shorter time. According to the present invention, the impurity region, the active region of the TFT, and the intrinsic region of the TFD are crystallized at a lower temperature than the conventional one by utilizing the characteristics of the crystallization by the catalyst material.
They have found a method that can be activated to simplify the problematic process, that is, to reduce the number of film forming steps. The outline is shown below. Film formation of amorphous silicon film '' Introduction of catalytic element (by ion implantation or ion doping method) (may be formed by forming a film containing a catalytic element on silicon film) Film formation of insulating film (gate insulating film) Gate of TFT Formation of mask material for electrodes and TFD Introduction of doping impurities (by ion implantation or ion doping method) Activation of doping impurities (at 600 ° C. or less, within 8 hours) Formation of interlayer insulator Formation of source and drain electrodes of TFT

Alternatively, an amorphous silicon film is formed. An insulating film (gate insulating film) is formed. A TFT gate electrode and a TFD mask material are formed. Doping impurities are introduced (by ion implantation or ion doping). (By ion implantation or ion doping) (Alternatively, a film containing a catalytic element may be formed on a silicon film.) Activation of doping impurities (at 600 ° C. or less, within 8 hours) Formation of interlayer insulator TFT source and drain Formation of electrodes

In these steps, the order of the latter and 'can be reversed. In order to precisely control the concentration of the catalyst element, a means such as an ion implantation method is preferable. For crystallization and activation, 6
A temperature of 00 ° C. or less, typically 550 ° C. or less is sufficient, and an annealing time of 8 hours or less, typically 4 hours or less is sufficient. In particular, when the catalyst element was uniformly distributed from the beginning by the ion implantation method or the ion doping method, crystallization was extremely easy to proceed.

In the present invention, the structure of the TFD will be briefly described. In contrast to the conventional TFD having a layer structure, the TFD of the present invention has a planar (planar) structure. . In the present invention, the active region of the TFT and the intrinsic region of the TFD start from the same amorphous silicon film. For this reason, conventionally, it has been necessary to form two silicon films, but in the present invention, it is sufficient to form a single silicon film. The N layer and the P layer, which have been conventionally required, can be obtained by forming the N layer and the P layer simultaneously and planarly at the time of the impurity doping of the TFT. That is, when an N-type impurity is implanted into a TFT, an N-type region of the TFD is formed, and when a P-type impurity is implanted into the TFT, a P-type region of the TFD is formed. As a result,
The interlayer insulator also has one layer.

Such a planar TFD has an unprecedented feature. When a conventional TFD (having a shape as shown in FIG. 4) is used, for example, as an optical sensor, the direction of the electric field generated inside the semiconductor is perpendicular to the light irradiation surface, and the light irradiation intensity is reduced. The directions were not uniform, and electrons and holes were generated efficiently and could not be taken out. Further, the TFD may be short-circuited due to a pinhole between the layers. In the present invention, since the direction of the electric field generated in the TFD is parallel to the light irradiation surface, the light intensity in the direction of the electric field is constant, the photoelectric conversion efficiency is improved, and a short circuit is unlikely to occur.

Further, in the present invention, a thin amorphous silicon film having a thickness of 100 nm or less that is not crystallized by ordinary thermal annealing is also crystallized due to the action of the catalytic element. The thickness of the crystalline silicon film is required to be 100 nm or less, preferably 50 nm or less from the viewpoint of preventing pinholes and insulation failure of the gate insulating film at the step portion of the TFT, disconnection of the gate electrode, and the like. Conventionally, this method could not be realized by a method other than laser crystallization. However, according to the present invention, it could be realized by thermal annealing even at a low temperature. Needless to say, this contributes to further improvement in yield. In addition, even when the TFD is used as an optical sensor, the use of a thin semiconductor layer improves the SN ratio and the photoelectric conversion efficiency. Hereinafter, the present invention will be described in more detail with reference to Examples.

[0018]

[Embodiment 1] FIG. 1 is a sectional view showing a manufacturing process of this embodiment. First, the substrate (Corning 7059) 10
A 200-nm-thick silicon oxide base film 11 was formed thereon by a sputtering method. Further, an intrinsic (I-type) amorphous silicon film having a thickness of 50 to 150 nm, for example, 150 nm was deposited by a plasma CVD method. Next, nickel ions were implanted into the obtained amorphous silicon film by an ion implantation method. The dose is 1 × 10 ¹³
５5 × 10 ¹⁴ cm ⁻² , for example, 5 × 10 ¹³ cm ⁻² .
As a result, 5 × 10 ¹⁸
Nickel was implanted at a concentration of about cm ^-3 . (Figure 1
(A))

Next, patterning was performed by photolithography to form island-like silicon regions 12a (for TFT) and 12b (for TFD). Further, a silicon oxide film 13 having a thickness of 100 nm was deposited as a gate insulating film by a sputtering method. For sputtering, silicon oxide was used as a target, the substrate temperature during sputtering was 200 to 400 ° C., for example, 250 ° C., the sputtering atmosphere was oxygen and argon, and argon / oxygen = 0 to 0.
0.5, for example, 0.1 or less. Then, decompression C
According to the VD method, a thickness of 600 to 800 nm, for example, 60
A 0 nm silicon film (containing 0.1-2% phosphorus) was deposited. It is desirable that the step of forming the silicon oxide and the silicon film be performed continuously. Then, the silicon film is patterned to form TFT gate electrodes 14a, 14b.
Then, a TFD mask material 14c was formed. (Figure 1
(B))

Next, as shown in FIG. 1C, a photoresist mask 15a was formed, and impurities (phosphorus) were implanted into the silicon region by a plasma doping method using the gate electrode as a mask. Phosphine (PH ₃ ) was used as the doping gas, and the accelerating voltage was 60 to 90 kV.
For example, it was set to 80 kV. Dose amount is 1 × 10 ¹⁵ to 8 × 1
It was set to 0 ¹⁵ cm ^-2 , for example, 2 × 10 ¹⁵ cm ^-2 . As a result, an N-type impurity region 16a of the TFT and an N-type impurity region 17n of the TFD were formed. (Fig. 1 (C))

Next, as shown in FIG. 1D, a photoresist mask 15b was formed, and impurities (boron) were implanted into the silicon region by a plasma doping method using the gate electrode as a mask. Diborane (B ₂ H ₆ ) is used as a doping gas, and the accelerating voltage is 40 to 80 k.
V, for example, 65 kV. Dose amount is 1 × 10 ¹⁵ -8
× 10 ¹⁵ cm ^-2 , for example, 5 × 10 ¹⁵ . As a result, a P-type impurity region 16b of the TFT and a P-type impurity region 17p of the TFD were formed. TFD N-type region 17
An intrinsic region 17i is left between the n and P type regions 17p. (Fig. 1 (D))

Thereafter, annealing was performed at 500 ° C. for 4 hours in a reducing atmosphere to activate the impurities. This annealing facilitated crystallization and activated doping impurities. After the crystallization, the TFD mask material 14c was removed. (FIG. 1 (E))

Subsequently, a silicon oxide film 18 having a thickness of 600 nm is formed.
Is formed by a plasma CVD method as an interlayer insulator,
A contact hole is formed in this, and a TFT is formed by a metal material, for example, a multilayer film of titanium nitride and aluminum.
Electrodes / wirings 19a, 19b, 19c, TFD electrodes
Wirings 19d and 19e were formed. Finally, annealing was performed at 350 ° C. for 30 minutes in a hydrogen atmosphere at 1 atm. The semiconductor circuit was completed by the above steps. (Figure 1
(F))

In this step, as can be seen from the figure, both the silicon film and the interlayer insulator could be made into one layer. As a result, the film formation process was greatly reduced. Also, TFT
Of the active region and the intrinsic region of the TFD were measured by secondary ion mass spectrometry (SIMS). As a result, nickel of 1 × 10 ^{18 to} 5 × 10 ¹⁸ cm ⁻³ was detected.

FIG. 2A shows a TFD portion in the semiconductor circuit of this embodiment. When this TFD is used as an optical sensor, light enters from above. This TFD
FIG. 2B is an energy band diagram along AA ′ of FIG.
Is shown as In general, crystalline silicon has low photosensitivity. To improve this, as shown in FIG. 2C, after removing the TFD mask 14c,
A semiconductor film 17a having high photosensitivity, such as hydrogenated amorphous silicon having a thickness of about 800 nm, for example, 300 nm, may be formed in close contact with the intrinsic region 17i.

For example, when amorphous silicon is used, a large amount of carriers are generated in the amorphous silicon film 17a by light irradiation from above because the light absorption coefficient is larger than that of the intrinsic region 17i of crystalline silicon below. Then, it drifts to the intrinsic region 17i of crystalline silicon and is separated by the electric field applied thereto.

In the configuration shown in FIG. 2C, carriers are generated in the amorphous semiconductor film 17a, and at the same time, carriers are generated in the crystalline silicon semiconductor film 17i according to the wavelength dependence of the photosensitivity. Therefore, light in a wider wavelength range can be converted into electricity. When an amorphous silicon film is used as the amorphous semiconductor film 17a, carbon, nitrogen, oxygen, or the like may be added thereto to change the wavelength dependence of the photosensitivity.

If the energy band width of the amorphous semiconductor film 17a is wider than that of the intrinsic region 17i, the carrier generated in the intrinsic region 17i will
a, and the carriers generated in the amorphous semiconductor film 17a move to the intrinsic region 17i along the gradient of the energy band. Therefore, the generated carrier can be more efficiently taken out.

[Embodiment 2] FIG. 3 is a cross-sectional view showing a manufacturing process of this embodiment. A 200-nm-thick silicon oxide base film 31 was formed on a substrate (Corning 7059) 30 by a sputtering method, and an amorphous silicon film was formed by a plasma CVD method. Then, the amorphous silicon film is patterned to form the island-shaped silicon regions 32a.
(For TFT) and 32b (for TFD). Further, tetraethoxysilane (Si (OC ₂ H ₅ )
₄ , TEOS) and oxygen were used as raw materials, and a silicon oxide 33 having a thickness of 100 nm was formed as a gate insulating film by a plasma CVD method. As a raw material, trichloroethylene (C ₂ HCl ₃ ) was used in addition to the above gas. Before the film formation, oxygen was flowed into the chamber at 400 ml / min, and
Plasma was generated at 00 ° C., a total pressure of 5 Pa, and an RF power of 150 W, and this state was maintained for 10 minutes. Thereafter, the chamber was filled with oxygen at 300 ml / min and TEOS at 15 ml / m.
In, trichlorethylene was introduced at a rate of 2 ml / min to form a silicon oxide film. The substrate temperature, RF power, and total pressure were 300 ° C., 75 W, and 5 Pa, respectively. After the completion of the film formation, 1.33 × 10 ⁴ Pa was placed in the chamber.
Of hydrogen was introduced, and hydrogen annealing was performed at 350 ° C. for 35 minutes.

Subsequently, by a sputtering method,
A tantalum film having a thickness of 600 to 800 nm, for example, 600 nm was deposited. It is desirable that the step of forming the silicon oxide 33 and the tantalum film be performed continuously. Instead of tantalum, chromium, molybdenum, tungsten, titanium or the like may be used, but all of them need to be able to withstand a later annealing step. Then, by patterning the tantalum film, the TFT gate electrodes 34a, 34b, T
An FD mask material 34c was formed. At this time, the width (= channel length) of the gate electrode of the TFT is 5 to 10 μm,
The width of the mask material of D was 20 to 50 μm. Further, the surface of this tantalum wiring was anodized to form an oxide layer on the surface. Anodization was performed in a 1-5% solution of tartaric acid in ethylene glycol. The thickness of the obtained oxide layer was 200 nm. (FIG. 3 (A))

Next, impurities (phosphorus) were implanted into the silicon region by a plasma doping method. Phosphine (PH ₃ ) was used as the doping gas, and the accelerating voltage was 6
0 to 90 kV, for example, 80 kV. The dose is 1 ×
10 ¹⁵ to 8 × 10 ¹⁵ cm ⁻² , for example, 2 × 10 ¹⁵ cm ⁻²
And Thus, an N-type impurity region 35 was formed. (FIG. 3B) Subsequently, nickel ions were implanted by an ion implantation method. The dose was 1 × 10 ^{13 to} 5 × 10 ¹⁴ cm ⁻² , for example, 5 × 10 ¹³ cm ⁻² . As a result, nickel was implanted into the amorphous silicon film at a concentration of about 5 × 10 ¹⁸ cm ⁻³ . (FIG. 3 (C))

Further, the left TFT (N-channel type TF)
T) and the region to the right of the TFD (N-type region)
Mask with dist 36, and again do plasma doping method
And the silicon area of the right TFT (P-channel TFT)
In the region (P-type region) on the left side of TFD and TFD,
Element) was injected. As a doping gas, diborane (B
_TwoH₆), The acceleration voltage is set to 50 to 80 kV, for example, 6
5 kV. Dose amount is 1 × 10¹⁵~ 8 × 10¹⁵cm
^-2For example, 5 × 10 more than the previously implanted phosphorus ¹⁵cm
^-2And As a result, the N-type impurity region 37 of the TFT is formed.
a, the P-type region 37b and the TFD N-type region 38n;
A P-type region 38p was formed. (FIG. 3 (D))

Thereafter, the impurities were activated by annealing at 500 ° C. for 4 hours in a hydrogen reducing atmosphere of 0.1 to 1 atm. At this time, since nickel has diffused into the regions 37a, 37b and 38p, 38n into which nickel has been previously implanted, crystallization easily progressed by this annealing, and doping impurities were activated. Also,
Nickel diffused into the active region of the TFT, and crystallization proceeded. On the other hand, in the intrinsic region 38i of the TFD, particularly in the central portion, no nickel was present in silicon, and there was no diffusion from the surroundings, so that no crystallization occurred. That is, TFT
In the TFD, the impurity region and a part of the intrinsic region in contact with the impurity region crystallized, and the central portion of the intrinsic region 38i was in an amorphous state. (FIG. 3
(E))

Subsequently, a silicon oxide film 39 having a thickness of 200 nm is formed.
Is formed by a plasma CVD method as an interlayer insulator,
A contact hole is formed in this, and a TFT is formed by a metal material, for example, a multilayer film of titanium nitride and aluminum.
Electrodes / wirings 40a, 40b, 40c, TFD electrodes
Wirings 40d and 40e were formed. Finally, annealing was performed at 350 ° C. for 30 minutes in a hydrogen atmosphere at 1 atm. The semiconductor circuit was completed by the above steps. (FIG. 3
(F))

In this embodiment, the mask material 34c of TFD is used.
Are insulated from other gate electrode wirings and are in a floating potential state. However, in this case, the operation of the TFD may be hindered by accumulation of some charges. if,
If stable operation is required, the potential may be the same as that of the P-type region or the N-type region of the TFD. Further, in this embodiment, since the mask material 34c exists on the intrinsic region 38i, when the TFD is used as an optical sensor, light needs to be incident from the substrate side. In the case of this embodiment, it is difficult to make the amorphous semiconductor film adhere to the intrinsic region in order to improve the photosensitivity as shown in FIG. 2C which is a variation of the first embodiment. Unlike FIG. 1, there is no problem in the intrinsic region 38i because an amorphous state portion having good photosensitivity remains.

[0036]

According to the present invention, a crystalline silicon TFT is provided.
Thus, the number of processes for manufacturing a semiconductor circuit having TFD and TFD was reduced, and mass productivity was improved. Further, the present invention also provides a method of crystallizing silicon at a low temperature of 500 ° C. and a short time of 4 hours, for example.
Throughput can be improved. In addition, conventionally, when a process at 600 ° C. or higher was employed, shrinkage or warpage of a glass substrate had been a problem as a cause of a decrease in yield. However, such a problem can be solved at a stretch by using the present invention. Resulting in.

This means that a large area substrate can be processed at one time. That is, by processing a large-area substrate, a large number of integrated circuits and the like can be cut out from one substrate, whereby the unit cost can be significantly reduced. Thus, the present invention is an industrially useful invention.

[Brief description of the drawings]

FIG. 1 shows a cross-sectional view of a manufacturing process in Example 1.

FIG. 2 shows a TFD obtained in Example 1 and a band diagram thereof.

FIG. 3 shows a cross-sectional view of a manufacturing process in Example 2.

FIG. 4 shows a conventional manufacturing process example (cross-sectional view).

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 10 ... Substrate 11 ... Base insulating film (silicon oxide) 12 ... Island-like silicon region 13 ... Gate insulating film (silicon oxide) 14 ... Gate electrode and mask material (phosphorus-doped silicon) 15: doping mask (photoresist) 16: source / drain region of TFT 17: impurity region / intrinsic region of TFD 18: interlayer insulator (silicon oxide) 19: metal wiring Electrode (titanium nitride / aluminum)

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[Procedure amendment]

[Submission date] March 27, 2000 (2003.
7)

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Name of invention

[Correction method] Change

[Correction contents]

Patent application title: Thin film transistor and semiconductor circuit

[Procedure amendment 2]

[Document name to be amended] Statement

[Correction target item name] Claims

[Correction method] Change

[Correction contents]

[Claims]

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 27/146 H01L 29/78 613A 21/336 618F 627G

Claims (8)

[Claims] 1. A thin film transistor comprising: a source region and a drain region formed by introducing a P-type impurity into crystalline silicon; and a channel formation region located between the source region and the drain region. The thin film transistor, wherein the source region and the drain region include a catalyst element and phosphorus. 2. The thin film transistor according to claim 1, wherein said P-type impurity is boron. 3. The thin film transistor according to claim 2, wherein the concentration of the phosphorus in the source region and the drain region is lower than the concentration of the boron in the source region and the drain region. 4. The thin film transistor according to claim 1, wherein the channel formation region contains the catalyst element. 5. The method according to claim 1, wherein the concentration of the catalyst element contained in the source region and the drain region is 1 × 10 ¹⁷ cm ⁻³ or more, and 2 × 10 ²⁰ cm ⁻³ or more. a thin film transistor having a ^{diameter of} less than cm ^-3 . 6. The thin film transistor according to claim 1, wherein the catalyst element is nickel, iron, cobalt, or platinum. 7. A P-channel TFT having a first source region, a first drain region, and a first channel formation region located between the first source region and the first drain region; A second source region, a second drain region and the second
And a N-channel TFT having a second channel formation region located between the source region and the second drain region, wherein the first source region and the first drain region are p-type. The second source region and the second drain region include an n-type crystalline semiconductor doped with an n-type impurity; the first source The CM and the first drain region have a catalytic element and phosphorus introduced therein.
OS. 8. The CMOS according to claim 7, wherein the p-type crystalline semiconductor and the layer of the first channel formation region contain silicon.