JP3535463B2 - Method for manufacturing semiconductor circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor (TFT) having a non-single crystal semiconductor thin film and a method for manufacturing the same. The thin film transistor manufactured by the present invention is formed on either an insulating substrate such as glass or a semiconductor substrate such as single crystal silicon. In particular, the present invention relates to a thin film transistor manufactured through crystallization and activation by thermal annealing.

[0002]

2. Description of the Related Art Recently, research has been conducted on an insulating gate type semiconductor device having a thin film active layer (also called an active region) on an insulating substrate. In particular, thin-film insulating gate transistors, so-called thin film transistors (TFTs), have been eagerly studied. These are distinguished as an amorphous silicon TFT or a crystalline silicon TFT depending on the material / crystal state of the semiconductor used. Crystalline silicon is non-single-crystal, not single-crystal.

Generally, the electric field mobility of a semiconductor in an amorphous state is small, and therefore TF which requires high speed operation.
Not available for T. Further, in amorphous silicon, since the P-type electric field mobility is extremely small, a P-channel type TFT (PMOS TFT) cannot be manufactured. Therefore, an N-channel type TFT (NMOS TF) is not produced.
T) combined with complementary MOS circuit (CMOS)
Cannot be formed.

On the other hand, a crystalline semiconductor has a larger electric field mobility than an amorphous semiconductor, and therefore can operate at high speed. With crystalline silicon, not only NMOS TFTs but also PMOS TFTs can be obtained, so CMO
It is possible to form S circuits. Further, it has been pointed out that it is preferable to provide an LDD (low-concentration drain) structure such as that used in a MOSIC of a single crystal semiconductor in order to obtain better characteristics.

[0005]

In order to obtain an LDD structure, the following process is necessary. Island-shaped semiconductor region, formation of gate insulating film Formation of gate electrode Introduction of low-concentration impurities (by ion implantation or ion doping) Formation of mask for LDD region (anisotropic etching or gate of insulating film covering gate electrode) Introduction of high-concentration impurities (by ion implantation or ion doping) Activation of impurities (by laser annealing or thermal annealing)

The biggest problem among these processes is the process. Laser annealing is a method of activating amorphous silicon by irradiating a laser or strong light equivalent to it, but because of the instability of the laser output and the instability resulting from an extremely short process There is no prospect for mass production. Further, since the laser light is irradiated from above the gate electrode, the LDD region is blocked by the mask formed in the process of, and sufficient activation cannot be expected.

At present, the method which is considered to be practically applicable is a method of activating impurities in silicon by heat. In this method, the LDD region is also sufficiently activated, and there is little variation between batches. However, in order to activate the impurities in the silicon film, it is usually necessary to perform annealing at a temperature of about 600 ° C. for a long time or annealing at a high temperature of 1000 ° C. or more. If the latter method is adopted, the substrate that can be selected is limited to quartz, and the substrate cost becomes very high. With the former method, there is more room to choose a substrate, but if an inexpensive substrate is used, shrinkage of the substrate during thermal annealing becomes a problem, and it is pointed out that the yield will decrease due to mask misalignment, etc. It has been demanded. Specifically, it is desired to carry out at a strain temperature of various alkali-free glass used as a substrate or lower (preferably a temperature lower than the strain temperature of glass by 50 ° C. or higher). The present invention is intended to provide an answer to such a difficult task.

[0008]

As a result of the research conducted by the present inventor,
It was revealed that the addition of a trace amount of a catalytic element to the substantially amorphous silicon coating can promote crystallization, lower the crystallization temperature, and shorten the crystallization time. Nickel (Ni), iron (Fe), cobalt (Co), and platinum (Pt) are preferable as the catalyst element. Specifically, a simple substance of these catalytic elements, or a compound coating of such a silicide or the like is adhered to amorphous silicon, or these catalytic elements are introduced into the amorphous silicon film by a method such as an ion implantation method. It can be crystallized by thermal annealing at a suitable temperature, typically below 580 ° C.

As a matter of course, the higher the annealing temperature, the shorter the crystallization time. In addition, the higher the concentration of nickel, iron, cobalt, and platinum, the lower the crystallization temperature and the shorter the crystallization time. According to the research by the present inventor, in order to promote crystallization, the concentration of at least one of these elements is 1 × 10 ¹⁵ cm ⁻³ or more,
It has been found that it is necessary to preferably exist at 5 × 10 ¹⁸ cm ⁻³ or more.

On the other hand, all of the above catalyst materials are unfavorable materials for silicon, so it is desirable that the concentration thereof be as low as possible. In the study of the present inventors, it is desired that the total concentration of these catalyst materials does not exceed 2 × 10 ¹⁹ cm ⁻³ .

The present inventor has paid attention to the effect of this catalytic element, and found that the above problem can be solved by utilizing it. That is, in the present invention, the crystallization temperature is lowered and the activation (recrystallization) temperature of the doping impurities is lowered by introducing these catalytic elements into silicon which has been made amorphous by introducing impurities. . In particular, according to the research by the present inventor, crystallization was extremely easy to proceed when the catalytic element was evenly distributed from the beginning by the ion implantation method or the ion doping method. Typically, it can be sufficiently crystallized and activated at a temperature of 550 ° C. or lower, and the annealing time is 8
Within hours, typically within 4 hours, has been found to be sufficient.

Further, it was difficult to crystallize a silicon film having a thickness of 1000 Å or less by the conventional crystallization by thermal annealing, but in the present invention, it is extremely easy to crystallize at a lower temperature in a shorter time. I was able to. 10
Thin active area TFTs of less than 00Å, especially less than 500Å
In addition to having excellent characteristics, the semiconductor device has the advantages that the step difference is small and therefore there are few defects in the step portion of the gate insulating film or the gate electrode, and the yield is high. However, conventionally, there is no method other than crystallization by laser annealing because crystallization is difficult. The present invention is epoch-making in that the technical area which has been monopolized by laser annealing can be implemented by thermal annealing and the yield can be improved for the above reasons. Hereinafter, the present invention will be described in more detail with reference to examples.

[0013]

[Embodiment] [Embodiment 1] FIG. 1 shows the manufacturing process of this embodiment.
A sectional view is shown. First, the substrate (Corning 7059) 10
2000 Å thick silicon oxide by sputtering method
A bare base film 11 was formed. Furthermore, plasma CVD method
Depending on the thickness 500-1500Å, for example 1500Å
The intrinsic (I-type) amorphous silicon film 12 of
On top of that, a 200 Å-thick acid layer was formed by sputtering.
A silicon oxide film 13 was deposited. Then, the silicon film
Nickel ions were implanted by the on implantation method. Doe
The amount is 2 x 10¹³~ 2 x 10¹⁴cm^-2, For example 5 × 10
¹³cm^-2And As a result, the amorphous silicon film 1
2 nickel concentration is 5 × 10¹⁸cm ^-3To the extent
It was In this process, a nickel silicide film is deposited on 5-100Å
You can also substitute by doing. However, in that case, oxidation
It is desirable not to have the silicon film 13. (Fig. 1 (A))

Then, this amorphous silicon film was annealed in a nitrogen atmosphere at 550 ° C. for 4 hours to be crystallized. After annealing, the silicon film was patterned to form island-shaped silicon regions 12a, and a silicon oxide film 14 having a thickness of 1000 Å was deposited as a gate insulating film by a sputtering method. In sputtering, silicon oxide is used as a target, the substrate temperature during sputtering is 200 to 400 ° C., for example 250 ° C., the sputtering atmosphere is oxygen and argon, and argon / oxygen = 0 to 0.
5, for example, 0.1 or less.

Subsequently, a silicon film (containing 0.1 to 2% of phosphorus) having a thickness of 3000 to 8000 Å, for example, 6000 Å was deposited by the low pressure CVD method. It is desirable that the steps of forming the silicon oxide and the silicon film are continuously performed. Then, pattern the silicon film,
The gate electrode 15 was formed. (Fig. 1 (B))

Next, impurities (phosphorus) were implanted into the silicon region by plasma doping using the gate electrode as a mask. As doping gas, phosphine (PH
₃ ) is used and the acceleration voltage is 60 to 90 kV, for example 80 kV.
It was set to V. The dose is 1 × 10 ¹³ to 8 × 10 ¹³ cm ^-2 ,
For example, it is set to 2 × 10 ¹³ cm ⁻² . As a result, N type low concentration impurity regions 16a and 16b were formed. (Fig. 1
(C))

Subsequently, the substrate was immersed in a citric acid solution (1 to 5%), and a current was passed through the gate electrode to grow an anodic oxide layer 17 on the surface of the gate electrode. The thickness of the anodic oxide was preferably 1000 to 5000Å, particularly 2000 to 3000Å. Here, it is set to 2500Å. Then, again, impurities (phosphorus) were implanted into the silicon region by plasma doping using the gate electrode and the surrounding anodic oxide as a mask. Phosphine (PH ₃ ) was used as a doping gas, and the acceleration voltage was set to 60 to 90 kV, for example, 80 kV. The dose amount is 1 × 10 ¹⁵ to 8 × 10 ^15.
cm ⁻² , for example, 2 × 10 ¹⁵ cm ⁻² . As a result,
N-type high-concentration impurity regions 18a and 18b are formed.
In addition, the anodic oxide served as a mask, and the low-concentration impurity regions (LDD) that were previously formed remained in some areas. (Fig. 1
(D))

Thereafter, the impurities were activated by annealing at 500 ° C. for 4 hours in a nitrogen atmosphere. The activation temperature is preferably lower than the crystallization temperature. This is to reduce the shrinkage of the substrate as much as possible. At this time, since nickel was distributed in the silicon film, recrystallization easily proceeded despite the low temperature annealing. Thus, the impurity regions 16a, 16b and 1
8a, 18b could be activated. What should be noted here is that this activation process is performed by thermal annealing, so that the laser annealing method cannot sufficiently activate L.
DD is also activated. The crystallinity of the impurity region and the active region was also continuous.

Then, a silicon oxide film 19 having a thickness of 6000Å is formed.
Is formed by plasma CVD as an interlayer insulator,
A contact hole is formed in this, and the TFT is made of a metal material, for example, a multilayer film of titanium nitride and aluminum.
The electrodes / wirings 20 in the source region and the drain region were formed. Finally, annealing was performed at 350 ° C. for 30 minutes in a hydrogen atmosphere of 1 atm. The thin film transistor was completed through the above steps. (FIG. 1 (E)) When the nickel concentration was examined by the secondary ion mass spectrometry (SIMS) method, both the impurity region and the active region of the TFT were detected at a concentration of 1 × 10 ^{18 to} 5 × 10 ¹⁸ cm ^−3. Was done.

[Embodiment 2] FIG. 2 shows a cross-sectional view of a manufacturing process of this embodiment. First, the substrate (Corning 7059) 2
An underlayer film 22 of silicon oxide having a thickness of 2000 Å was formed on the substrate 1 by sputtering. Furthermore, plasma CVD
Depending on the method, the thickness is 500-1500Å, for example 500Å
Intrinsic (I-type) amorphous silicon film was deposited.
Then, this silicon film was patterned to form an island-shaped silicon film 23.

Furthermore, tetra-ethoxy-silane (Si
Using (OC ₂ H ₅ ) ₄ , TEOS) and oxygen as raw materials, a 1000 Å thick silicon oxide 24 was formed as a gate insulating film of a crystalline silicon TFT by a plasma CVD method. As the raw material, trichlorethylene (C ₂ HCl ₃ ) was used in addition to the above gas. Oxygen 400SCCM flow into the chamber before film formation, substrate temperature 300 ° C, total pressure 5P
a, plasma was generated with an RF power of 150 W, and this state was maintained for 10 minutes. After that, 300S oxygen is added to the chamber.
A silicon oxide film was formed by introducing 15 SCCM of CCM and TEOS and 2 SCCM of trichloroethylene. The substrate temperature, RF power, and total pressure are each 300
C., 75 W, 5 Pa. After the film formation was completed, 100 Torr of hydrogen was introduced into the chamber, and hydrogen annealing was performed at 350 ° C. for 35 minutes.

Subsequently, by the sputtering method,
A tantalum film having a thickness of 3000 to 8000Å, for example, 6000Å was deposited. Instead of tantalum, titanium, tungsten, molybdenum, or silicon may be used. However, the heat resistance is required to withstand the subsequent activation. It is desirable that the steps of forming the silicon oxide 24 and the tantalum film be continuously performed. Then, the tantalum film was patterned to form the gate electrode 26 of the TFT. The width (= channel length) of the gate electrode was set to 5 to 20 μm. (Fig. 2
(A))

Next, an amorpha is formed by an ion implantation method.
Impurities in the silicon region using the gate electrode as a mask
(Phosphorus) was injected. The acceleration voltage was 80 kV. Doze
The amount is 2 × 10¹³cm^-2And As a result, N type low concentration
Impurity regions 26a and 26b are formed. (Fig. 2
(B)) Subsequently, the gate electrode is mass-machined by the ion implantation method.
Nickel was injected as a black metal. The dose amount is 2 × 10¹³~
2 x 10¹⁴cm^-2, For example 1 × 10¹⁴cm^-2And This
As a result, the concentration of nickel in the amorphous silicon region 23
The degree is 1 × 10 ¹⁹cm^-3It became about. (Fig. 2 (C))

Next, the surface of this tantalum wiring was anodized to form an oxide layer 27 on the surface. Anodization was performed in a 1-5% ethylene glycol solution of tartaric acid. The thickness of the obtained oxide layer was 2000Å. Then, impurities (phosphorus) were implanted again by ion implantation using the gate electrode as a mask. The acceleration voltage was 80 kV, and the dose amount was 2 × 10 ¹⁵ cm ^-2 . As a result, N
High-concentration impurity regions 28a and 28b of the mold are formed.
(Fig. 2 (D))

After that, the amorphous silicon film was crystallized and impurities were activated by annealing at 500 ° C. for 4 hours in a nitrogen atmosphere. At this time,
N-type impurity regions 28a, 28b and 26a and 26
Since nickel was implanted into b, activation proceeded easily by this annealing. On the other hand, nickel was not injected into the active region under the gate electrode, but nickel diffused from the impurity region 26, so that crystallization proceeded. Complete crystallization was possible with a channel length of 10 μm or less. However, it was difficult to completely crystallize with a longer channel length. However, when the annealing temperature was set to 550 ° C., crystallization of the active region was observed even with a channel length of 20 μm. It has been clarified that it is better to raise the annealing temperature or lengthen the annealing time in order to promote such lateral crystallization.

Subsequently, as an interlayer insulator, the thickness is 2000 Å
CV using TEOS as the raw material for the silicon oxide film 29 of
Then, a source hole and a drain electrode / wiring 30 were formed from a metal material, for example, a multilayer film of titanium nitride and aluminum, by forming the contact hole by the D method. The semiconductor circuit is completed through the above steps. (Fig. 2
(E))

The field effect mobility of the manufactured thin film transistor is 70 to 100 cm ² / V at a gate voltage of 10V.
s, the threshold value was 2.5 to 4.0 V, and the leak current when a voltage of -20 V was applied to the gate was 10 ^-13 A or less.

[0028]

INDUSTRIAL APPLICABILITY According to the present invention, throughput is achieved by crystallization of an amorphous silicon film and activation of doping impurities in silicon at a low temperature of 500 to 550 ° C. and a short time of 4 hours. Can be improved. In addition, conventionally, when a process of 600 ° C. or higher is adopted, shrinkage of the glass substrate has been a cause of a decrease in yield, but by using the present invention, such a problem can be solved at once. .

This means that a large area substrate can be processed at one time. That is, by processing a large-area substrate, a large number of semiconductor circuits (matrix circuits, etc.) can be cut out from one substrate, and the unit price can be significantly reduced. When this is applied to a liquid crystal display, mass productivity and characteristics can be improved.

Although two examples are shown in the present specification, it is particularly noted that in the process of example 2, the crystallization of the amorphous silicon film and the activation of the impurities are performed at the same time. Conventionally, as shown in Example 1, it was usual to introduce impurities and perform activation after crystallization. However, in such a method, the process is duplicated, and discontinuity of crystal growth occurs in the active region formed by the first crystallization and the source and drain recrystallized after the impurity is introduced, which adversely affects the reliability. Brought. Simultaneous crystallization and activation as in Example 2 brought about an effect of simplifying the process (and accompanying increase in throughput) and improving reliability by continuity of crystallinity. Thus, the present invention is an industrially useful invention.

[Brief description of drawings]

1A to 1C are cross-sectional views of a manufacturing process of Example 1.

2A to 2C are cross-sectional views of a manufacturing process of Example 2.

[Explanation of symbols]

10 ... Substrate 11 ... Base insulating film (silicon oxide) 12 ... Amorphous silicon film 13 ... Silicon oxide film 12a ... Island silicon region 14 ... Gate insulating film (silicon oxide) 15 ... ..Gate electrode (phosphorus-doped silicon) 16 ... Low-concentration impurity region (LDD) 17 ... Anodic oxide (silicon oxide) 18 ... Source / drain 19 ... Interlayer insulator (silicon oxide) ) 20 ... Metal wiring / electrode (titanium nitride / aluminum)

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁷ Identification code FI H01L 21/265 P (56) Reference JP-A-6-333951 (JP, A) JP-A-5-55246 (JP, A) C. Hayzelden, J .; L. Batstone, R.A. C. Cammarata, In situ tranmission electron microscopy studies of silicide-media ted crystallize of amorphous, Appl. Phys. Lett. , January 13, 1992, Vol. 60 No. 2, p. 225-227 (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 21/336 H01L 21/20 H01L 29/786

Claims (6)

(57) [Claims] 1. An amorphous film on a substrate having an insulating surface.
A recon film is formed, and TEOS is used as a raw material on the amorphous silicon film.
A silicon oxide film is formed by a plasma CVD method , a gate electrode is formed on the silicon oxide film, and the amorphous silicon is formed using the gate electrode as a mask.
An impurity is introduced into the film at a first concentration, and
Si is formed in the fas silicon film at a concentration of 2 × 10 ¹⁹ cm ^-3 or less.
An anisotropic film is formed by introducing an element that promotes crystallization of the silicon, forming an insulating film covering the gate electrode.
Forming a mask of a low-concentration impurity region by means of etching to make the amorphous silicon film higher than the first concentration.
The impurity is introduced at a second concentration of
Crystallization of the amorphous silicon film and activation of the impurities
A method for manufacturing a semiconductor circuit , which is characterized by performing characterization. 2. An amorphous film on a substrate having an insulating surface.
A recon film is formed, and a gate insulating film is formed on the amorphous silicon film.
Then , a gate electrode is formed on the gate insulating film, and the amorphous silicon is formed using the gate electrode as a mask.
An impurity is introduced into the film at a first concentration, and
Si is formed in the fas silicon film at a concentration of 2 × 10 ¹⁹ cm ^-3 or less.
An anisotropic film is formed by introducing an element that promotes crystallization of the silicon, forming an insulating film covering the gate electrode.
Forming a mask of a low-concentration impurity region by means of etching to make the amorphous silicon film higher than the first concentration.
The impurity is introduced at a second concentration of
Crystallization of the amorphous silicon film and activation of the impurities
Performed sex of a plasma CVD using TEOS as a raw material as an interlayer insulating film
Method to form a silicon oxide film and contact the interlayer insulating film.
And forming a source electrode and a drain electrode.
Method for manufacturing a semiconductor circuit. 3. An amorphous film on a substrate having an insulating surface.
A recon film is formed, and TEOS is used as a raw material on the amorphous silicon film.
A silicon oxide film is formed by a plasma CVD method , a gate electrode is formed on the silicon oxide film, and the amorphous silicon is formed using the gate electrode as a mask.
An impurity is introduced into the film at a first concentration, and
Si is formed in the fas silicon film at a concentration of 2 × 10 ¹⁹ cm ^-3 or less.
An anisotropic film is formed by introducing an element that promotes crystallization of the silicon, forming an insulating film covering the gate electrode.
Forming a mask of a low-concentration impurity region by means of etching to make the amorphous silicon film higher than the first concentration.
The impurity is introduced at a second concentration of
Crystallization of the amorphous silicon film and activation of the impurities
Performed sex of a plasma CVD using TEOS as a raw material as an interlayer insulating film
Method to form a silicon oxide film and contact the interlayer insulating film.
And forming a source electrode and a drain electrode.
Method for manufacturing a semiconductor circuit. 4. A any one of claims 1 to 3, wherein the element is a method for manufacturing a semiconductor circuit according to claim nickel, iron, the cobalt, or platinum. 5. A any one of claims 1 to 4, wherein the gate electrode includes a tantalum, the gate electrode, the method for manufacturing a semiconductor circuit, wherein the thickness is 300 to 800 nm. 6. The element according to any one of claims 1 to 5, wherein the element is introduced by an ion implantation method.
A method for manufacturing a semiconductor circuit.