WO1998057372A1 - LATERALLY CRYSTALLIZED TFTs AND METHODS FOR MAKING LATERALLY CRYSTALLIZED TFTs - Google Patents

Abstract

A technique to achieve vertical integration of CMOS devices. A Germanium seed (20) is deposited in hole (16) in an insulating oxide layer (14) on top of an amorphous silicon film (12). The hole may be over the source and/or drain regions of a thin film transistor. The structure is annealed causing lateral crystallization resulting in the formation of large grain polysilicon.

Description

LATERALLY CRYSTALLIZED TFTs AND METHODS FOR MAKING LATERALLY CRYSTALLIZED TFTs

INTRODUCTION

This invention was made with Government support under Contract No. MDA 972-95-1-0004 awarded by ARPA. The Government has certain rights in these inventions.

CROSS REFERENCE TO RELATED APPLICATION

This application is based on U.S. Provisional Application Serial No. 60/049,172 filed June 10, 1997, assigned to the assignee of this application and incorporated herein by reference.

FIELD OF THE INVENTION

The invention relates generally to the field of Thin Film Transistors (TFTs) in crystallized amorphous silicon through controlled nucleation of grains and more

particularly to novel methods for forming such devices utilizing techniques which are

simple and utilize a low thermal budget.

BACKGROUND OF THE INVENTION

Increasing chip area and decreasing feature size has resulted in interconnect

delay becoming a significant fraction of the overall chip delay. Numerous techniques are

under consideration to decrease interconnect delay, including the use of low resistivity

interconnect materials, low-k dielectrics, and increased packing density using various

techniques to increase the level of achievable integration for a given device generation. Of these, the increase of packing density using vertical integration of devices is particularly interesting, as it offers the additional benefits of decreasing block-level

routing complexity (through the ability to layer blocks) and dramatically decreasing the consumed silicon real-estate. Various simple vertically integrated cells have been demonstrated in the past, such as vertically integrated SRAM cells.

Vertical integration of devices using thin film transistors (TFTs) is a promising means of achieving 3-D integration. Unfortunately, TFT performance is

typically substantially worse than that of bulk devices, limiting the use of such cells to only non-critical paths. Additionally, for deep submicron VLSI applications, statistical variation in device performance is introduced by the random distribution of grains in the device, since the grain size is on the order of the device size. This variation in performance results in an unacceptable degradation in uniformity. Uniformity can be improved by reducing the grain size; however, this degrades device performance substantially. In the conventional active matrix liquid crystal display (AMLCD) technology,

the pixel transistors are fabricated in amorphous Si on glass and the row and column

drivers are other circuits, such as, controllers are made in single crystal Si. The circuits

are then externally connected to the display. This increases the weight, size and cost of the display. The potential to integrate the scan and data drivers and other circuitry and

thereby reduce the cost of liquid-crystal displays has been one of the major reasons for

pursuing polycrystalline Silicon (poly-Si) TFTs. Amorphous Si TFTs have very low

mobility and poor long term reliability and hence can't be used for these applications.

For very high resolution displays, even the pixel transistors will have to have better

performance. Hence it will be imperative that TFTs should be fabricated on the same substrate (glass) as the rest of the display and should have low leakage, high mobility, low power consumption and high reliability. While high-temperature (> 600°C) poly-Si

TFT technology is in manufacturing for high-definition view finder and projection display applications, its use has been restricted to very small sized displays due to the high-cost of quartz substrates. It is evident that the TFTs will have to be fabricated in poly-Si with the boundary condition of limited thermal budget compatible with glass substrates. The current approach being investigated to fabricated poly-Si TFTs is to

deposit Si in amorphous form and then convert it to polycrystalline form through thermal or laser processing. The conventional thermal processing requires higher temperatures (> 600°C) and long times (many tens of hours), making it unusable for glass substrates.

Laser processing is a beam scanning process and hence slow and expensive. Both these techniques still result in random placement of grains and grain boundaries resulting in large statistical variation in device properties.

A method to achieve large grain TFTs with a control over the location of the grain is therefore highly desirable. Lateral solid phase crystallization using a seeding

agent to precisely nucleate the grains is an extremely promising means of achieving this. Metal induced crystallization has been studied in the past, using metals such as nickel.

Unfortunately, the integration of such a process into a CMOS technology may be

problematic due to the deleterious effect of nickel on device performance. A metal- contamination-free technique to achieve lateral crystallization could be integrated into

a standard CMOS process with significantly less difficulty. SUMMARY OF THE INVENTION

Therefore, novel techniques are presented herein for achieving such single

crystal grain growth. Both techniques presented herein have the common objective of recrystallizing amorphous silicon to make it as close to perfect as possible, utilizing low temperature, solid-phase crystallization. Both techniques are promising for achieving

3-D integration and AMLCD driver integration.

In the first technique, a novel seeding technique is used which is a low

thermal budget, low cost, simple and CMOS-compatible process, and therefore extremely promising for achieving 3-D integration. According to this method, germanium is used as a seeding agent to crystallize amorphous silicon films. This results in large grain polysilicon having spatially specified grains. It is therefore possible to

fabricate high performance thin film transistors (TFT) with excellent control over the position of grain boundaries.

In an alternative approach, a thick patterned light absorber like amorphous silicon (a-Si) is placed over the amorphous thin Si in which a TFT is to be formed. This

is then subjected to an RTA step to nucleate a grain in the amorphous film, and then to

a low temperature, solid phase crystallization step (LT-SPC). This results in formation

of near single crystal grains in the crystallized thin Si film.

The methods share the common approach of laying down an amorphous

silicon (a-Si) film, and then crystallizing it, using alternative approaches to control the region of crystallization. The resulting crystal may be used either as the drain of an

active device, or alternatively the entire active device may be formed in a single grain Other features and advantages of the present invention would become apparent to a person of skill in the art who studies the present invention disclosure given with respect to the following figures.

BRIEF DESCRIPTION OF THE DRAWINGS

Figure 1 describes the process flow for a germanium seeded laterally crystallized TFT;

Figure 2 is an Atomic Force Micrograph showing elevated polycrystalline seed points after defect etch;

Figure 3 is a plan- view TEM showing growth of seeded grains with seed structure boundary overlaid in white;

Figure 4 shows electrical characteristics of (a) NMOS and (b) PMOS TFTs;

Figure 5 shows variations in field effect mobility with channel length;

Figure 6 shows variations in mobility improvement with device size; Figure 7 shows a schematic view of lateral crystallization in the device

channel;

Figure 8 is a schematic view of prior art device structures;

Figure 9 is the process flow for an alternative method using patterned

absoφtion of light for seeding and lateral crystallization to enable formation of TFTs;

Figure 10 illustrates heat transfer within a process utilizing light absoφtion for selective heating;

Figures 11 A and 1 IB illustrate the difference in transfer characteristics for

devices of two sizes; Figure 12 illustrates the extent of crystallization by showing variation in mobility improvement versus channel length and width; and

Figures 13A-13D illustrate the use of patterned absorption masking to enhance device characteristics.

DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT

The solid phase crystallization (SPC) of amorphous silicon to polysilicon occurs through the processes of nucleation and grain growth. Clusters of a critical size nucleate within the amoφhous matrix and subsequently enlarge. Both nucleation and

grain growth are characterized by specific activation energies. For the solid phase crystallization of amoφhous silicon by homogenous nucleation, the activation energy of grain growth is less than that of nucleation. Therefore, the amount of nucleation relative to grain growth decreases with decreasing temperature. To maximize grain size, it is

desirable to minimize the nucleation/grain growth ratio. Therefore, solid phase

crystallization is typically done at a low temperature. The disadvantage of this technique

is that the crystallization may take a long time (several hours at 600 °C). A large fraction of this time consists of the time before any nucleation has occurred, called the incubation time. Efforts have been made to reduce the incubation time without sacrificing

conditions favorable to the maximization of grain size.

While the long incubation time associated with the amorphous to

(poly)crystalline transition is generally a disadvantage associated with low temperature

SPC, it can be exploited to achieve lateral crystallization. In this process, nucleation is artificially induced in selected regions of the amoφhous films using seeding agents. The

nuclei formed at these seed sites enlarge with the rest of the film is still in the incubation stage. Therefore, it is possible to form abnormally large grains with controlled location of the grain. The laterally crystallized grains cannot grow infinitely; after the passage of the incubation time, homogenous nucleation is induced in the rest of the film.

Silicon-germanium (SiGe) alloys exhibit a variation in thermodynamic properties from those of silicon to those of germanium. In fact, the thermal properties

exhibit a dependence that is often almost linearly related to the ratio of the melting points of silicon and germanium, scaled to the germanium fraction of the film. This

phenomenon applies to crystallization as well; silicon-germanium alloys crystallize faster than pure silicon at a given temperature. This fact has been used to reduce the

incubation time of amorphous silicon films for thin film transistors by replacing the amorphous silicon with a bi-layer of SiGe and Si. This same fact can also be used to enable the use of germanium as a seeding agent for the lateral crystallization of amoφhous silicon; the germanium reacts with the Si to form a SiGe layer at the Ge-Si interface, which nucleates the lateral crystallization.

Volumetrically, the germanium needed to induce nucleation in silicon is quite

small. Given the exponential dependencies involved, the formation of a small amount

of high Ge-fraction alloy at the interface is sufficient to cause nucleation. Additionally,

Ge is not an excessively fast difϊuser in Si, unlike typical metallic seeding agents.

Therefore, any effect of Ge is essentially confined to the Ge-Si interfacial region and its

surroundings.

These phenomena detailed above can be utilized to enable the germanium- seeded lateral crystallization of amoφhous silicon to fabricate high-performance TFTs.

Referring first to Figures 1 through 4, a process utilizing germanium (Ge) as

a seeding agent for the solid phase crystallization of amoφhous silicon will be described. According to the process, germanium is deposited in one or more selected regions; with heating lateral crystallization then occurs with grains growing out, away from the germanium seed.

Referring specifically to Figure 1, in the first step an amoφhous silicon layer 12 is deposited on an oxidized silicon substrate 10. A sacrificial oxide layer 14, is then

deposited and patterned using known techniques; the patterning defines open windows at 16 where the germanium will be deposited.

As the next step, germanium is selectively deposited, for example by low pressure chemical vapor deposition (LPCVD) utilizing the oxide mask 14. Poly-Ge can

be deposited at low temperatures (less than 400°), therefore Si remains amorphous.

Thus the next step shows deposition of germanium 20, 22 in two regions defined by the

oxide layer 14. After the germanium deposition, the Si film is crystallized at low temperature to form crystals 30, the low temperature inhibiting self nucleation within the remaining Si film. Grains 30 grow laterally from the seeding points due to the lower

activation energy associated with the Ge-Si interface. By placing the seeding points 20,

22 in the source drain regions of a TFT generally indicated at 40 in the next step, it is

possible to laterally crystallize into the channel 42. These last three steps represent the only significant modifications to a conventional high-temperature TFT process flow.

They involve two extra depositions (of the sacrificial oxide and the germanium) and a lithography step (to pattern the seed holes). Immediately after Ge deposition, the wafers

were annealed in argon at 500°C-550°C to fully crystallize the channel films. This immediate crystallization also removes the need to perform a wafer cleaning step after

Ge deposition, which would be complicated by the fact that Ge etches in most common

cleaning solutions. The immediate crystallization was thus used to eliminate this step entirely. For comparison, wafers without any Ge seeding were crystallized simultaneously. After crystallization, the Ge is removed using a standard H₂SO₄:H₂O₂ cleaning step. Thus the seeding technique is flilly CMOS compatible. A TFT 40 may now be defined using known techniques. The crystallization is a low temperature process. The thermal budget involved can be tailored to meet the needs of individual

applications and device dimensions. An alternative approach may use a single germanium seeding point 50 producing crystallization into the device channel from one side only.

Devices were fabricated on oxidized silicon wafers to test the potential for

3-D integration. lOOnm amoφhous Si was deposited by LPCVD at 500°C followed by

50 nm sacrificial SiO₂. Seeding holes were patterned in the SiQ were stripped using H₂SO₄:H₂O₂ and HF respectively. Planar topgate TFTs were then fabricated, positioning the seeding points in the source/drain regions of the devices. 30nm thermally-grown SiO₂ was used as a gate dielectric and 250nm in situ doped polysilicon was used as the gate electrode. For comparison, TFTs without seeding were also fabricated using an

identical process.

To determine the extent of crystallization into the channel films, AFM images

were taken of defect-etched seeded films after a partial crystallization. The seed points used for these test structures were 2μm diameter circular holes. Enough crystallization was performed to form the SiGe alloy without causing too much lateral crystallization,

enabling estimation of seeding efficiency. As is evident from the AFM image, as shown

in Figure 2, polycrystalline silicon is formed at the seed point, and is not etched as

rapidly as the surrounding amoφhous film, resulting in a height differential. Focused EDAX of the same film indicates the presence of less than 1% Ge within the seeded

regions, and its total absence in the remaining Si.

A plan-view TEM of a further-annealed seeding region is shown in Figure 3. It is evident from this figure that grains are formed in the seeded region, and extend into the still-amoφhous matrix. The size of the seed holes used in this work (lμm and

larger) have been scaled to smaller dimensions and materials tests performed, indicating that the seed hole size does not represent a limiting factor on scaling of the technology.

Note that numerous grains may grow out of each seed point, depending on the size of the point. These grains have numerous defects within them. Some of these defects are annealed out during the subsequent high temperature processing.

Electrical characteristics of 0.9μm/0.7μm NMOS and PMOS devices are

shown in Figure 4. It is evident that there is substantial improvement in device performance. The seeded devices shown in these plots were seeded in both the source and drain regions. To compare the performance of the seeded devices with the unseeded devices, various device parameters were calculated, and are summarized in Table I.

TABLE I

SUMMARY OF DEVICE CHARACTERISTICS (W/L=0.9μM/0.7μM)

Clearly, the seeded devices are superior to the unseeded ones. In particular, on-state

performance shows substantial improvement. However, off-state and sub-threshold

performance only show marginal improvement, suggest the presence of leakage causing defects within the channel. NMOS and PMOS devices show asymmetric improvement; the NMOS devices show substantially more improvement in on-state performance than shown in PMOS devices. This is probably related to the distribution of trap states within

the bandgap, and the relative impact of the reduction of grain boundary populations on

the same.

To determine the extent of lateral crystallization, the variation in mobility with device dimensions was analyzed. The variation in mobility vs. channel length for both dual-seeded (seeded in both the source and the drain) and single-seeded (seeded in only

the drain) vs. control devices is shown in Figure 5. From this figure, it is apparent that seeded devices perform better than unseeded devices in all cases. The extent of improvement increases dramatically for smaller devices. For larger devices, dual seeded

structures are superior. However, a crossover occurs, and single-seeded devices are better at shorter channel lengths.

The effect of overall device geometry on seeding efficiency was also analyzed. The variation in mobility improvement is shown as a function of both channel length and

width in Figure 6. Note that the smallest devices show the most improvement, as noted above. A crucial factor affecting the implementation of any lateral crystallization

technology is that of uniformity. The mobility distribution achieved using the two

seeding structures is compared to unseeded devices in Table II. TABLE II

SUMMARY OF ΓRA- WAFER MOBILITY UNIFORMITY

The efficiency of seeding is apparent from Figure 2; every seed point exhibits

the existence of polycrystalline material. These nucleated regions result in the formation of laterally crystallized grains away from the seed point into the device channel. Different orientations have different growth rates, and therefore, high growth rate orientations tend to dominate. This leads to the prevalence of a majority of devices with essentially one laterally crystallized grain extending into the channel from each seed

point, resulting in the relatively good uniformity detailed in Table II for dual-seeded devices.

The difference in performance and uniformity obtained from dual-seeded and single-seeded devices is explained upon consideration of the effect of device geometry

upon performance. For large devices, the laterally crystallized region is a relatively small

fraction of the overall channel; typical laterally crystallized grains have been found to be approximately lμm long. Therefore, the resulting improvement in performance is

marginal. Since the dual seeded devices have two laterally crystallized regions, they exhibit better performance than the single-seeded devices, which have only one laterally

crystallized region. As the channel length and width are reduced, the laterally

crystallized region becomes a larger fraction of the overall devices. This is shown

schematically in Figure 7. For extremely small devices, the channel becomes almost a single grain (for the single-seeded devices) or two grains (for the dual-seeded structures). This results in the crossover in performance noted in Figure 5. Since a grain boundary is inherently located in the channel of the dual-seeded devices, this is a limiting factor in the performance enhancement achievable using a dual-seeding scheme. The uniformity of dual-seeded small devices is better than unseeded devices because the two seeded grains impinge to form a two-grain structure in the majority of devices. This is because the overall laterally crystallized region can extend as much as

2μm, due to the summation of the two grains, and is therefore much larger than the channel dimensions. In single-seeded devices, on the other hand, the grain size is the same or less than the device size (upon inclusion of the separation of the seed point from the channel, approximately 0.7μm). Therefore, though performance is improved in many devices, uniformity is poor due to the statistical variations in the extent of lateral crystallization. This also explains the one-sided population distribution noted in Table II. Based on the results and analysis detailed above, it is apparent that excellent performance can be obtained using this technology, through the elimination of grain

boundaries from within the channel of the devices. As shown in Figure 8, existing

technologies crystallize the entire film 90 which forms the channel of the device. Film 90 has been crystallized using lasers, rapid thermal annealing (RTA) or long furnace anneals. The result is multiple grain boundaries 92 within the channel 94 itself. Such

boundaries inevitably cause degradation in the performance of the device; further, the

occurrence or location of these boundaries 92 cannot be controlled. In contrast, even

from the large devices detailed in this work, in which the complete removal of grain

boundaries is prevented by the maximum achievable grain size, it is apparent that substantial performance improvement is achievable. Further scaling to smaller devices should enable complete lateral crystallization of the channel. However, as is apparent from Figure 3, several intra-grain defects are still in existence. These degrade the device performance to below that of bulk devices, and result in the poor sub-threshold slope noted in Table I.

To develop this technology to its frill potential, it will be necessary to reduce the number of intra-grain defects within the channel. One way of achieving this is through the replacement of silane with disilane, allowing for more optimized low temperature, high deposition rate (and therefore more amoφhous) films. This will result in a lower density of defects through a reduction in the nucleation rate, and also in an

increased average grain size. The increase in average grain size will result in improved uniformity for smaller devices. Furthermore, the use of this technology in deep- submicron devices, as mandated by VLSI, should enable the fabrication of extremely high performance devices offering good uniformity. The overall thermal budget used in the crystallization process is low. The

maximum temperature excursion is 550 °C, excluding the gate oxidation step.

Replacement of this thermal oxide dielectric with a high quality deposited dielectric will

further reduce the thermal budget, making the process fully compatible with the bulk

devices existing on lower levels. Obviously, interconnection of multiple layers of active

devices is a significant challenge. Two levels of devices could be interconnected using

modified conventional interconnect and plug technologies. Advances in plug technologies should enable the interconnection of these devices, resulting in the

development of a vertically integrated, high performance CMOS technology for next-

generation giga-scale integration applications. The device technology described in this work may also find application in the fabrication of high performance pixel and

integrated driver circuitry for flat-panel display applications.

Figures 9-12 illustrate the method for making laterally crystallized polysilicon

TFTs using patterned light absoφtion masks. The method is based on the desire for a technique to nucleate a channel film without exposing the non-nucleated film to the same thermal cycle. Such a process appears in Figure 9.

At tungsten-halogen lamp wavelengths used in RTA, silicon is a poor

absorber of light; a large fraction of the light is transmitted through the thin silicon film.

This results in inefficient heating of the substrate. Additionally, substantial heat is lost to the surroundings through convective and radiative losses. The ability to locally increase the heating of the silicon through increased light absorption is facilitated using patterned thick layers of an absorbing material over the region to be nucleated; heat is

conducted to this region from the absorbing layer, resulting in a temperature gradient in

the channel film away from the heat absorbing seed point. This is shown schematically in Figure 10, which shows the heat transfer within the system. This temperature gradient, induced by the patterned absorption masks, results in nucleation under the

mask without exposing the surrounding region to the same thermal cycle. This system

can therefore be used for controlled seeding and grain-size enhancement using lateral

crystallization. In the process of Figure 9, lOOnm amoφhous silicon 110 was deposited on the fused silica substrates 112 by LPCVD at 525°C/1000mtor from SiH₄. An etch stop

layer 114 of 20nm LPCVD SiO₂ (LTO) was deposited on top of the amoφhous silicon

112, followed by 300nm of an amoφhous silicon masking layer 116. Amoφhus silicon was used for simplicity; materials with higher absoφtion coefficients, such as SiGe, could be used to enhance the masking effect.

The masking layer was patterned to form islands 120 over the regions to be used as the TFT drains. The wafers were then subjected to an RTA nucleation step.

Wafers with no masking layer were found to nucleate in 380 seconds. Wafers with a

blanket masking layer were found to nucleate in 75 seconds. Interestingly, the substrate temperature was found to be essentially the same in both cases, 750 °C, indicative of a substantial vertical temperature gradient. Device wafers with patterned masking layers

were nucleated in 300 seconds. This verifies the heat loss to the surrounding unmasked films through a conductive process, and establishes the presence of a temperature gradient. Using a test pattern of broad (1mm) lines and spaces, the selective nucleation was visually identifiable, with the unmasked regions being more opaque than the masked regions upon mask removal.

During nucleation, a seed 125 is formed under the mask 120.

After nucleation, the wafers were crystallized in a furnace at 500-550°C in argon, causing growth of the seeds into crystals 130 where an active device or the

source or drains of an active device can be formed. The masking layers were then etched off. The etch stop SiO₂ was removed in HF, and standard top-gate self-aligned

planar TFTs were fabricated using a glass-compatible (<600°C) process, similar to that

described above, using the crystal 130 as the drain of the finished TFT.

For comparison, control devices were fabricated using low temperature-SPC

and RTA.

Electrical measurements were performed on the devices to determine

performance characteristics. Device transfer characteristics for a 2μm/2μm device are shown in Figure 11(A). Characteristics are summarized in Table II. Maximum performance enhancement was achieved for small devices. Device transfer characteristics for a 20μm/20μm device is shown in Figure 11(B). A measure of the extent of lateral crystallization can be obtained by analyzing the variation in performance improvement with device geometry; this is done in Figure 12, showing the variation in mobility improvement vs. channel length and width.

In all cases, seeded devices have better performance than unseeded devices.

The increase in performance improvement with decreasing device size is explained by the fact that the laterally crystallized region of the channel is an increasing fraction of the channel length and width with decreasing geometry. Therefore, this technique works best for small devices. For larger devices, there is still some improvement achieved using the absoφtion masks. This is explained by the fact that the laterally crystallized region extends into the drain field of the TFT for devices of all sizes. This reduces

scattering in the same, improving performance in all cases. Additionally TEM analysis

indicates that all grains are elongated slightly, including those wholly formed away from

the absoφtion masks. It is suspected that this phenomenon is a result of the temperature gradient experienced by the film during RTA. This elongation of grain may also partially explain the improvement in performance seen in larger devices.

The main advantage of this seeding technique in comparison to other

techniques is in its simplicity. Since no seeding material is in physical contact with the

channel film, this is a non-contact seeding technique, suffering from no potential contamination issues. Additionally, since the seeding is performed using commonly available equipment and materials, and involves only one extra lithographic step, the cost of implementation of this technique is expected to be low.

Patterned absoφtion masking is also promising as a technique to tune the device characteristics across a single substrate. Lateral crystallization as demonstrated

in this work can be used to fabricate high performance TFTs. Controlled seeding of large grains enhances performance without causing substantial statistical variation in channel structure (Figure 13B). Unmasked structures can be used to fabricate standard

TFTs (Figure 13 A). A fully masked structure can be used to cause extensive nucleation throughout the TFT (Figure 13C), resulting in a small-grain TFT structure with low

statistical variation in mobility, useful when small TFTs are desired. To facilitate the use of lateral crystallization on larger TFTs, a matrix of masking points can be used (Figure 13D), resulting in a larger average grain size.

Both these seeding techniques can also be used for making high performance TFTs in polycrystalline Si for application such as active matrix flat panel displays. By

controlled seeding and solid phase crystallization of amoφhous Si, the grain size can be

enhanced in a polycrystalline Si TFT and the random placement of grain boundaries,

which cause large statistical fluctuations in device properties, can be minimized. The seeding can be done in the most critical regions of a TFT, such as, the drain region.

Hence the grains will nucleate at the drain and grow into the channel. The grain

boundaries will be away from the drain where the electric field is the highest.

Although the present invention has been described with reference to preferred embodiments, workers skilled in the art will recognize that changes may be made in form and detail without departing from the spirit and scope of the invention. Therefore, the

scope of the present invention is defined by the following claims.

Claims

CLAIMSWHAT IS CLAIMED IS:

1. A method for seeding and crystallization of amoφhous silicon comprising: depositing an amoφhous silicon film on a substrate;

depositing and patterning a sacrificial oxide on said amorphous silicon, said patterning step defining at least one opening for the deposition of germanium; depositing germanium in said at least one opening; crystallizing said amoφhous silicon at a temperature to inhibit self nucleation within said silicon while causing germanium seeded grain growth within said silicon to

form individual crystals in said amoφhous silicon; and removing the germanium.

2. A method as claimed in Claim 1 including the further step of forming

a TFT utilizing one of said individual crystals.

3. A method as claimed in claim 2 where a drain of said TFT is formed

in one of said crystals.

4. A method as claimed in claim 2 where said TFT is formed in one of

said crystals.

5. A method as claimed in claim 2 where said TFT is formed in two said

crystals emanating from source and drain.

6. A method as claimed in claim 1 wherein said germanium is deposited from GeH₄.

7. A method as claimed in claim 6 wherein said germanium was deposited by LPCVD.

8. A method as claimed in claim 1 wherein said amorphous silicon is crystallized at 500-600┬░C.

9. A method as claimed in claim 2 wherein said TFT is formed as a

standard planar top-gate self-aligned TFT.

10. A method for seeding and crystallization of amorphous silicon comprising: depositing a first amoφhous silicon film on a substrate;

depositing an oxide layer on said silicon film;

depositing a light absorber film and patterning seed defining islands over a

desired location on each of said crystallization site; crystallizing said amoφhous silicon at a temperature to substantially inhibit nucleation within said silicon while causing lateral grain growth within said silicon under

said light absorber to form at least one individual crystal under said light absorber in said

amoφhous silicon; and

removing said light absorber film.

11. A method as claimed in claim 10 including the further step of forming

a TFT utilizing one of said individual crystals.

12. A method as claimed in claim 11 where a drain of said TFT is formed in one of said crystals.

13. A method as claimed in claim 11 where said TFT is formed in one of said crystals.

14. A method as claimed in claim 11 where said TFT is formed in two

said crystals emanating from source and drain.

15. A method as claimed in claim 10 wherein a seed is formed under each of said islands during a nucleating step performed after said depositing step.

16. A method as claimed in claim 15 wherein said crystallizing step

includes imposing light on said substrate including said light absorber islands to cause

crystallization of said seed.

17. A method as claimed in claim 1 wherein multiple seeding points are

used from source to drain in a TFT to obtain a polycrystalline TFT with controlled

location and size of grains.

18. A method as claimed in claim 10 wherein a matrix of masking points

d to establish multiple large crystals in a gate region of a device.